4 69 61 8 2 5 1 6 t w f do ( 0 0 2 A7 B7 經濟部智慧时產局負工消費合作社印製 五、發明說明（丨） 本發明是有關於…-種用以改善半導體金屬內連線之氮 化矽保護層之電漿處理方法，且特別是有關一種消除陷入 孔洞（voids)內之光阻的方法；其光阻在金屬沉積的下一階 段中將可能出氣（outgas)而造成金屬侵蝕。此方法也密化 (increase the densification)了氮化砂層而減少氮化砍層中 造成介層短路的針孔數闫。 在超大規模積體（Ultra Large Scale Integration, ULSI) 的電路上，金屬內連線（metal interconnections)中的多層内 連線了在半導體晶片上的半導體元件。內連線中的不同層 是藉由數層的絕緣質來分隔，例如電漿加強氣相沉積 (plasma-enhanced chemical vapor deposited, PECVD)之氧化 ΐ夕層以及氮化砂層。由於輕離子，例如，鈉所產生的污染 將降低其中半導體元件的電子特性，氮化矽層也成爲避免 污染的保護層。·-般而言，絕緣層和保護層需要低溫的沉 積製程（低於40(TC)，因爲鋁/銅合金所形成的金屬佈線具 有（大約6 0 0 “C )低溶點。 令人遺憾的是，雖然爲滿足超大型積體電路的較高裝 構密度，而將形成內連線的金屬佈線距離拉近，這卻增加 了縱橫比（aspect ratio)，而在接著沉積的非共形 (nonconformal)絕緣層或保護層中形成孔洞。在低溫下以 電漿加強氣相沉積氮化矽的保護層而形成非共形層時，這 些孔洞將變得特別普及。 參考第1圖及第2圖可淸楚的了解孔洞的形成或鎖孔 的問題。請參照弟1圖’桌】圖係繪示在基底1 8中一部 3 ------------i 裝--------訂------- —a (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 經濟部智慧財產局員工消費合作社印製 4 69 61 8 2S16twfl . doc/ 002 A7 __JB7____— 五、發明說明（7) 分的剖視圖，其繪示了具有兩個短間隙並相互內連線的金 屬佈線2〇。在金屬佈線20上首先沉積一電漿加強氣相沉 積之氧化矽層22，其作爲沉積氮化矽層24中的解應力層 (stress-release layer)。如同第1圖所描述，在短間隙的金 屬佈線之頂端角落，沉積氮化矽層的沉積流動比在金屬佈 線之間的凹陷處還高；因此形成了具有鎖孔形的孔洞34。 接下來，當光阻層26被沉積並在基底18上其餘位置以微 影的方式形成介層洞（via hole)3時，殘留光阻將陷入氮化 矽層24之區域30下方的孔洞34中。隨後當受困光阻在 金屬沉積步驟中出氣時，殘留光阻的不完全去除將造成污 染以及金屬層的侵蝕。這將造成一個嚴重的問題，例如， 爲了在隨機存取記憶體（DRAM)晶片上產生墊金屬（pad metal)電性接點，而將介層孔蝕刻至第二層金屬佈線（M2) 的時候。第2圖係具有氮化砂層24之金屬佈線20的俯視 圖，其描述了光阻陷入的一種方式。 當使用旋轉塗佈法（spin coating)塗佈液態的光阻時， 此光阻將會進入在金屬佈線20角落的開口 32。接著，在 蝕刻介層孔、去除光阻以及沉積下一個金屬層後，受陷在 孔洞34(第I圖）的光阻，將在保護層24中沿著接線處30 出氣或噴出光阻：這造成下一金屬層的侵蝕以及可靠性的 問題。使用低溫電漿加強氣相沉積製程的另一個問題乃是 保護層24的多孔性，這使保護層較容易產生針孔，所以 造成活動離子的穿透而導致金屬與金屬之間的短路。 在美國專利案號5,554,418中Ito等人提到沉積保護層 4 ^紙張又度適用中國國家標準<CNS)A4規格⑵G X 297 .-------------ί 裝·-------訂--------- (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 469 61 8 2 5 1 6 t w f 1 . d o c /.. Ο Ο 2 _B7_ 五、發明說明（$ ) 的方法，包括在樹脂或塑膠材質的基底上沉積一層以化學 氣相沉積法沉積之氧化矽，並且教授一種沉積氧化物的方 法，其不會攻擊下方基底。然而，ito沒有教授一種解決 與上述有關鎖.孔問題的方法。 在美國專利案號5,296,404中Akahori等人提到沉積氮 化金屬層的另-種方法，但在此案中也沒提到鎖孔的問 題。 因此，短間隙金屬佈線上的氮化矽保護層仍有待改進， 這包括了避免光阻從孔洞出氣以及減少在保護層中造成電 性短路的..針_孔。 本發明的主要目的就是在金屬內連線上，以電漿處理 氣化矽表面來提供一種改，進式_電漿加強氣相沉積之氮化矽 薄層（約爲3-5干埃）。這種方法消除了鎖孔的形成，所以 避免光阻陷入短間隙金屬佈線間的氮化矽層孔洞中。 本發明的另一目的是運用電漿處理製程來同時密化氮 化矽層；既然用以消除針孔的較薄氮化矽保護層較不可能 通過針孔測試（因爲一個氮化薄層具有較多連續針孔），這 將減少保護層中針孔的數目。 總結以上所述，此發明係要在同一電漿加強化學氣 相沉積系統內_提供一系列的製程步驟，這些步驟包括在短 間隙金屬佈線上沉積解應力氧化矽層與氮化矽層，以及隨 後的電漿處理製程。 本發明首先提供一個半導體基底，該基底包括具有 場效電晶體（field effect transistors, FETs)之部分完整的積 -------------i裳--------訂---------故 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公釐） 經濟部智慧財產局員工消費合作社印製 469 61 8 25 I6twfl.doc/002 五、發明說明（V ) 體電路以及內連線金屬層。在隨機存取記憶體元件上形成 銲墊連接點之前，雖然氮化矽層一般上被當作第二次定義 金屬佈線上的保護層，當所需之物係短間隙金屬佈線上的 氮化砂層，此方法大致上就能被採用。接著，在基底上沉 積如鋁/銅的一金屬層，並將其定義成短間隙之金屬佈線； 而金屬佈線上的氧化矽層沉積將爲隨後沉積之氮化矽層提 供一解應力層。在同一電漿加強氣相沉積系統中’在改變 反應混合氣體後沉積氮化砂層。氮化砍一般而言係呈非共 形並產生鎖孔；這是因爲當氮化矽比一些關鍵厚度更厚 時，其沉積特性在金屬佈線的頂端將提供一種比在金屬佈 線間的凹陷處更高之沉積物質的流動。而一較薄的氯.化J夕 層可將鎖孔的問顆減辛最低；爲減少在氮化砂層中針孔的 數目，根據此發明所提出的方法，在沉積氮化砂薄層後隨 即展開《ϋ盤.淸Kradio frequency purge)，並在氮化砂層上 利甩飩_氣，如氦（He)或氬（Ar)或是兩者的混合.氣it進行 漿處理=以傳統技術的沉積與微影此光阻後，將介層孔蝕 刻至金屬佈線，並在含氧的電漿灰化過程（plasma ashing in oxygen)中剝除此光阻而不留下任何光阻殘餘物。電漿處理 密化了氮化矽保護層，所以在氮化矽中產生較少的針孔， 其針孔將造成可靠性的顧慮。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： --------------^ 裝--------訂.-------- "請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用t國國家標準（CNS)A4規格（210 x 297公餐） 經濟部智慧財產局員工消費合作社印製 469618 2!3l6t wfi . doc/ 002 A7 五、發明說明（S ) 第1圖是習知技藝的一剖視圖，圖中繪示了在氮化矽 保護層中以傳統沉積方式形成通道洞孔（channel voids)。 第2圖是在第1圖中習知技藝的俯視圖，圖中繪示了 在金屬佈線角落的一開口，其開口能使光阻在旋塗式沉積 (spin-on deposition)中進入並陷入通道介層孑L。 第3圖至第5圖，係依照本發明所繪示的方法，在金 屬佈線上製作保護層之製程剖視圖。 窗施例 本發明是關於一種在短間隙金屬佈線上製造改良式氮 化矽保護層的方法，用以在超大型積體電路的半導體基底 上形成金屬內連線。此方法運用在單一電漿加強氣相沉積 系統中所進行的製程步驟，該系統包括用以減少氮化矽保 護層中針孔數目的一系列電漿處理步驟。雖然本方法特別 適用於尺寸爲0.35微米（m)至0.25微米以及第二層金屬 間隙在0.575與0.475微米之間的動態隨機存取記憶體科 技，一個熟知此技藝者應相當淸楚此方法可廣泛的應用在 其餘電路之短間隙金屬佈線。 請參照第3圖，圖中繪示半導體基底18的部份剖視圖； 第3圖顯示具有積體電路的半導體基底之頂端部分，但此 圖爲了簡化圖樣，並沒有繪出其下電路結構。基底18 — 般是以具有結晶方向<100>的單晶矽所組成’此基底係用 來產生主動區元件。在將所需金屬沉積和微影以形成金屬 內連線前，爲要隔離其中積體電路與下一層金屬內連線， 沉積一絕緣層1 9。 7 本紙張又度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） _----；--------ΐ ·裝--------訂---------線< I (請先閲讀背面之注意事項再填寫本頁) 469 618 2516twfl . doc / 0 0 2 山 ______ 五、發明說明（6 ) 仍請參照第3圖，下·靥金屬內連線的形成是藉由在 絕緣基底1 8上沉積一金屬層2 0。-般而言，此金屬是由 鋁/銅合金所組成，其金屬可藉由物理氣相沉積法（Physical vapor deposition, PVD)，如濺鍍法（sputtering)來沉積’並 依據不同的金屬層形成不同的厚度。舉例來說，假如此金 屬層形成隨機存取記憶體中的第二金屬層，其厚度將在 5000與9000埃之間。 仍參照第3圖，並以本發明的方式在金屬佈線20上沉 積-氧化矽層22此氧化矽層22爲隨後沉積的氮化矽層 24(繪示於第4圖中），提供一解應力層。接著，在同一電 漿加_強化學氣祖沉積的系統裡_二進行氮化矽保護層之沉積4 69 61 8 2 5 1 6 twf do (0 0 2 A7 B7 Printed by the Consumers' Cooperative of the Smart Time Production Bureau of the Ministry of Economic Affairs. 5. Description of the invention (丨) The present invention relates to ... Plasma treatment method for silicon nitride protective layer of wire, and in particular, a method for eliminating photoresist trapped in voids; the photoresist may cause outgas in the next stage of metal deposition Metal erosion. This method also increases the densification of the nitrided sand layer and reduces the number of pinholes that cause short-circuiting of the interlayer in the nitrided layer. On Ultra Large Scale Integration (ULSI) circuits Multi-layer interconnects in metal interconnections connect semiconductor components on semiconductor wafers. The different layers in interconnects are separated by several layers of insulation, such as plasma-enhanced vapor deposition ( plasma-enhanced chemical vapor deposited (PECVD) oxide oxide layer and nitrided sand layer. Due to light ions, for example, the pollution caused by sodium will reduce the electronic characteristics of semiconductor components, silicon nitride layer Be a protective layer to avoid pollution. In general, the insulating layer and protective layer require a low-temperature deposition process (less than 40 (TC), because the metal wiring formed by the aluminum / copper alloy has (about 6 0 0 "C) Low melting point. Unfortunately, although the metal wirings forming the interconnects have been brought closer to meet the higher device density of very large integrated circuits, this has increased the aspect ratio, and Holes are formed in subsequently deposited nonconformal insulating or protective layers. These holes will become particularly popular when the protective layer of vapor deposited silicon nitride is strengthened with plasma at low temperatures to form a non-conformal layer . Refer to Figure 1 and Figure 2 for a clear understanding of the formation of holes or keyholes. Please refer to Figure 1 'table' Figure 1 is shown in the base 1 of a 3 ------- ----- i Packing -------- Order ------- --a (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 69 61 8 2S16twfl .doc / 002 A7 __JB7 ____— V. Description of the invention (7) is a sectional view showing a metal wiring 20 having two short gaps and interconnected with each other. A plasma-enhanced vapor-deposited silicon oxide layer 22 is first deposited on the metal wiring 20, which As a stress-release layer in the deposited silicon nitride layer 24. As described in FIG. 1, at the top corners of the short-gap metal wiring, the deposition flow of the deposited silicon nitride layer is higher than that of the depression between the metal wirings; therefore, a keyhole-shaped hole 34 is formed. Next, when the photoresist layer 26 is deposited and via holes 3 are formed in a lithographic manner on the rest of the substrate 18, the residual photoresist will fall into the hole 34 below the region 30 of the silicon nitride layer 24 in. Subsequently, when the trapped photoresist is outgassed in the metal deposition step, incomplete removal of the residual photoresist will cause pollution and erosion of the metal layer. This will cause a serious problem. For example, in order to generate pad metal electrical contacts on a random access memory (DRAM) chip, the via hole is etched into the second layer of metal wiring (M2). time. Fig. 2 is a top view of the metal wiring 20 having the nitrided sand layer 24, which illustrates one way in which the photoresist is trapped. When the liquid photoresist is applied using a spin coating method, the photoresist will enter the opening 32 at the corner of the metal wiring 20. Next, after the via hole is etched, the photoresist is removed, and the next metal layer is deposited, the photoresist trapped in the hole 34 (FIG. I) will emit gas or spray photoresist along the junction 30 in the protective layer 24: This causes problems with erosion of the next metal layer and reliability. Another problem of using low-temperature plasma to strengthen the vapor deposition process is the porosity of the protective layer 24, which makes the protective layer more prone to pinholes, which causes the penetration of mobile ions and causes a short circuit between metals. In U.S. Patent No. 5,554,418, Ito et al. Mentioned that the deposited protective layer 4 ^ paper is again applicable to the Chinese National Standard < CNS) A4 Specification ⑵G X 297 .------------- ------- Order --------- (Please read the phonetic on the back? Matters and then fill out this page) Printed by the Consumer Consumption Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 469 61 8 2 5 1 6 twf 1 doc / .. Ο Ο 2 _B7_ 5. The method of invention description ($) includes depositing a layer of silicon oxide deposited by chemical vapor deposition on a resin or plastic substrate, and teaching a method of depositing oxides. It will not attack the underlying substrate. However, Ito did not teach a solution to the above-mentioned problem with lock holes. Akahori et al., In U.S. Patent No. 5,296,404, mention another method of depositing a nitrided metal layer, but also do not mention the problem of keyholes in this case. Therefore, the silicon nitride protective layer on the short-gap metal wiring still needs to be improved. This includes avoiding photoresist gas from the holes and reducing electrical shorts in the protective layer. The main purpose of the present invention is to provide a modified, plasma-enhanced thin layer of silicon nitride (approximately 3-5 dry angstroms) by plasma treatment of the surface of vaporized silicon on the metal interconnects. . This method eliminates the formation of keyholes, so that the photoresist is not trapped in the silicon nitride layer holes between the short-gap metal wiring. Another object of the present invention is to use a plasma processing process to simultaneously densify the silicon nitride layer; since the thinner silicon nitride protective layer to eliminate pinholes is less likely to pass the pinhole test (because a thin nitride layer has More continuous pinholes), which will reduce the number of pinholes in the protective layer. Summarizing the above, this invention is to provide a series of process steps in the same plasma enhanced chemical vapor deposition system. These steps include the deposition of a stress-relieving silicon oxide layer and a silicon nitride layer on a short-gap metal wiring, and Subsequent plasma treatment process. The present invention first provides a semiconductor substrate, which includes a part of a complete product having field effect transistors (FETs). -Order --------- So (please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (2) 0 X 297 mm) Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 469 61 8 25 I6twfl.doc / 002 V. Description of the invention (V) Body circuit and interconnected metal layer. Before the formation of pad connection points on the random access memory device, although the silicon nitride layer is generally used as the second definition of the protective layer on the metal wiring, when the required material is nitrided on the short-gap metal wiring Sand layer, this method can be generally used. Next, a metal layer such as aluminum / copper is deposited on the substrate and defined as a metal wiring with a short gap; and the deposition of the silicon oxide layer on the metal wiring will provide a stress relief layer for the subsequently deposited silicon nitride layer. In the same plasma-enhanced vapor deposition system ', a nitrided sand layer is deposited after changing the reactive gas mixture. Nitriding cuts are generally non-conformal and create keyholes; this is because when silicon nitride is thicker than some critical thicknesses, its deposition characteristics at the top of the metal wiring will provide a depression than between metal wiring. Higher sedimentary material flow. And a thin layer of chlorine. Can reduce the number of pinholes to the minimum; in order to reduce the number of pinholes in the nitrided sand layer, according to the method proposed in this invention, after depositing a thin layer of nitrided sand Then, "Kradio frequency purge) was launched, and the radon gas, such as helium (He) or argon (Ar), or a mixture of the two, was blasted on the nitrided sand layer. Gas slurry processing = traditional technology After the photoresist is deposited and lithographed, the via holes are etched to the metal wiring, and the photoresist is stripped away without leaving any photoresist residue in the plasma ashing in oxygen process. . Plasma treatment densifies the silicon nitride protective layer, so fewer pinholes are created in the silicon nitride, which will cause reliability concerns. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: ----- --------- ^ Loading -------- Order .-------- " Please read the notes on the back before filling this page) This paper size is applicable to country t Standard (CNS) A4 specification (210 x 297 meals) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 469618 2! 3l6t wfi .doc / 002 A7 V. Description of the invention (S) Figure 1 is a cross-sectional view of the conventional art In the figure, channel voids are formed in a silicon nitride protective layer by a conventional deposition method. Figure 2 is a top view of the conventional technique in Figure 1. The figure shows an opening in the corner of the metal wiring. The opening allows the photoresist to enter and sink into the channel during spin-on deposition. Interlayer 孑 L. Figures 3 to 5 are cross-sectional views of a process for making a protective layer on a metal wiring according to the method shown in the present invention. Window Example The present invention relates to a method for manufacturing an improved silicon nitride protective layer on a short-gap metal wiring for forming a metal interconnect on a semiconductor substrate of a very large integrated circuit. This method uses process steps performed in a single plasma enhanced vapor deposition system, which includes a series of plasma processing steps to reduce the number of pinholes in the silicon nitride protective layer. Although this method is particularly suitable for dynamic random access memory technology with a size of 0.35 micrometers (m) to 0.25 micrometers and a second layer of metal gap between 0.575 and 0.475 micrometers, a person familiar with this technique should be quite aware that this method Widely used in short-gap metal wiring of other circuits. Please refer to FIG. 3, which illustrates a partial cross-sectional view of the semiconductor substrate 18. FIG. 3 illustrates a top portion of a semiconductor substrate having an integrated circuit. However, in order to simplify the drawing, the underlying circuit structure is not illustrated. The substrate 18 is generally composed of a single crystal silicon having a crystal orientation < 100 >. This substrate is used to generate an active region device. Before the required metal is deposited and lithographically formed to form a metal interconnect, an insulating layer 19 is deposited to isolate the integrated circuit therein from the next metal interconnect. 7 This paper is again applicable to China National Standard (CNS) A4 specification (21〇χ 297 mm) _----; ------- Line < I (Please read the notes on the back before filling this page) 469 618 2516twfl .doc / 0 0 2 Mountain ______ 5. Description of the invention (6) Still refer to Figure 3, The lower and inner metal interconnects are formed by depositing a metal layer 20 on the insulating substrate 18. -In general, this metal is composed of an aluminum / copper alloy, and the metal can be deposited by physical vapor deposition (PVD), such as sputtering, and according to different metal layers Formed in different thicknesses. For example, if such a metal layer forms a second metal layer in a random access memory, its thickness will be between 5000 and 9000 Angstroms. Still referring to FIG. 3, a silicon oxide layer 22 is deposited on the metal wiring 20 in the manner of the present invention. The silicon oxide layer 22 is a subsequently deposited silicon nitride layer 24 (shown in FIG. 4), which provides a solution. Stress layer. Next, a silicon nitride protective layer is deposited in the same plasma plus strong chemical gas deposition system.
步驟以及後續之電漿處理步驟。此製程順序係在由美國加 州應用物質機構所生產的P5000型電漿加強化學氣相沉積 反應裝置內進行，而其製程的變數則呈現在以下表格I (請先閱讀背面之注音？事項再填寫本頁) ------- I 訂 中 表格I 欄 \ I k 經濟部智慧財產局貝工消費合作社印製 1 2 3 4 5 步驟 氧化砂 穩定 氮化矽 穩定 密實化 1)時間 3.0 10 45 10 50-100 2)壓力 2.5 4.2 4.2 3.0 3.0 3)能量 230 0 690 0 50-250 4)氧化氮 1600 0 0 0 0 5)氫化硅 90 270 265 0 0 本紙張尺度適用中國國家標準（CNS)A4規格<210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 69 61 8 2516twfl . doc/'002 五、發明說明（"7) 6)氨 0 1 10 1 10 0 0 7)氮 0 4000 4000 0 0 8)氦或氬 0 0 0 400-700 400-700 9)間隙 430 600 600 600 600 10)溫度 400 400 400 400 400 第1欄至第5欄分別顯示氧化矽層22之化學氣相沉積 (第1欄），氣體交換中的穩定步驟（第2欄），氮化矽之化 學氣相沉積步驟（第3欄），隨後將混合氣體換成氦的穩定 步驟（第4欄），以及電漿處理（密化）步驟（第5欄）。第1列 至第列則顯示製程的變數，其中時間是以秒（seconds) 測量，壓力是以毫托耳（milliToir)測量，能量是以瓦特（Watts) 測量，電漿加強化學氣相沉積室的上電極與下晶座（bottom susceptor)之間的間隙是以毫升（mils)測量，溫度則是以度 (degree centigrade, t)測量；而第4列至第8列所呈現的 乃是以標準每分鐘立方公分（standard cubic centimeters per minute, seem)來測量第1欄至第5欄之製程步驟中氧化氮 (N2〇)、矽甲烷（SiH4)、氨_(NH3)、氮(N,)、氦（He)或氬之各 氣體或混合氣體的氣體流暈。電漿處理中氦流速的範圍係 在標準每分鐘400與700立方公分之間；而電漿處理的射 頻能量則較可能在50與200瓦特之間。化學氣相沉積法 所沉積之氧化矽層22(第1欄），厚度約在200與500埃之 間，但其厚度較明確爲300埃。沉積的氮化矽24(請參考 第3圖），厚度則依據金屬間的L間隙，但當L間隙分別 本紙張尺度適用中國國家標準（CNS)A4規格（2.10 x 297公釐） -------------{裝-----------------I X請先閱讀背面之法意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 469 618 2 5 1 6 t w f 1 . d o c / 0 0 2 ^ ___B7___ 五、發明說明（） 是在0.475與0.575微米之間，其較佳的圍度約在_1_000逛 5000埃之間。 因爲沉積的特性，氮化矽層24 —般上呈非共形並通常 形成通道孔洞。此乃沉積的特性所致，係因爲在金屬佈線 的頂端比在金屬佈線間凹陷之.處具有更高的沉積物質流動 性。氮化矽薄層的使用將鎖孔的問題減至最低，而根據以 上發明的製程方式，在沉積氮化矽（第3欄）後使用附加電 漿處理步驟（第5欄），將減少氮化矽層中針孔的數目。此 改善之處部分是因爲在氮化矽表面鍵結鬆弛的原子被濺擊 並重新沉積至其他位置’另一個原因則是以表格I之第5 欄之電漿慮理步驟處理氮化矽可使之更爲緻密所致。在中 (第5欄），另一鈍氣，如氬能代替氦；而氬與氦的混合氣 體也將產生相同的效果。 仍請參照第4圖，在保護層24上以旋塗方式形成光阻 層20，並以傳統微影與蝕刻技術在保護層24與氧化層22 中形成介層孔3，以暴露出金屬佈線20。較佳的介層孔3 的倉虫刻係利用反應性離子蝕刻（reactive ion etching)或高密 度電獎触刻（high-density plasma etching);其中，高密度 電漿蝕刻是利用包含四氟化碳（CF4)、三氟化甲烷（CHF3)、 以及載氣爲氦或氬的混合氣體。 請參照第5圖，光阻26的剝除是藉由含氧的電漿灰化 過程，並且不留下任何光阻殘餘在鎖孔區30’。而以上所 敘述的電漿處理之步驟順序也將產生具有較少針孔且較緻 密化的氮化矽。 本紙張尺度適用11國國家標準（CNS)A4規格（21ϋχ 297公釐） 一請先間讀背面Μ注意事瑣再填窵本Steps and subsequent plasma processing steps. This process sequence is performed in a P5000 plasma enhanced chemical vapor deposition reaction device produced by the Applied Materials Institute of California, and the process variables are presented in Form I below (please read the note on the back? (This page) ------- I Column I in the order form \ I k Printed by Shelley Consumer Cooperative, Intellectual Property Bureau, Ministry of Economic Affairs 1 2 3 4 5 Step Oxidation Sand Stabilized Silicon Nitride Stable Density 1) Time 3.0 10 45 10 50-100 2) Pressure 2.5 4.2 4.2 3.0 3.0 3) Energy 230 0 690 0 50-250 4) Nitric oxide 1600 0 0 0 0 5) Silicon hydride 90 270 265 0 0 This paper size applies to Chinese national standards (CNS ) A4 specifications < 210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 69 61 8 2516twfl .doc / '002 V. Description of the invention (" 7) 6) Ammonia 0 1 10 1 10 0 0 7 ) Nitrogen 0 4000 4000 0 0 8) Helium or Argon 0 0 0 400-700 400-700 9) Gap 430 600 600 600 600 10) Temperature 400 400 400 400 400 Columns 1 to 5 show the silicon oxide layer 22 Chemical vapor deposition (column 1), stabilization steps in gas exchange (column 2), chemical vapors of silicon nitride Deposition step (col. 3), followed by the stabilizing step into the mixed gas of helium (column 4), and plasma processing (densifying) step (column 5). Columns 1 to 1 show process variables, where time is measured in seconds, pressure is measured in milliToir, energy is measured in Watts, and the plasma-enhanced chemical vapor deposition chamber The gap between the upper electrode and the bottom susceptor is measured in milliliters (mils), and the temperature is measured in degrees (degree centigrade, t); columns 4 to 8 show Standard cubic centimeters per minute, seem to measure nitrogen oxide (N2〇), silicon methane (SiH4), ammonia (NH3), nitrogen (N, ), Helium (He) or argon gas or mixed gas flow halo. The range of helium flow rates in plasma processing is between 400 and 700 cm3 per minute; plasma energy is more likely to be between 50 and 200 watts. The silicon oxide layer 22 (column 1) deposited by the chemical vapor deposition method has a thickness between about 200 and 500 angstroms, but its thickness is more specifically 300 angstroms. The thickness of the deposited silicon nitride 24 (please refer to Figure 3) is based on the L-gap between metals. However, when the L-gap is respectively the Chinese standard (CNS) A4 specification (2.10 x 297 mm) for this paper size --- ---------- (Installation ----------------- IX Please read the legal and legal matters on the back before filling this page) Employees ’Consumption of Intellectual Property, Ministry of Economic Affairs Printed by the cooperative 469 618 2 5 1 6 twf 1. doc / 0 0 2 ^ ___B7___ 5. The description of the invention () is between 0.475 and 0.575 microns, and its preferred range is between _1_000 and 5000 angstroms. Due to the nature of the deposition, the silicon nitride layer 24 is generally non-conformal and typically forms a via hole. This is due to the nature of the deposition, which is due to the higher mobility of the deposition material at the top of the metal wirings than at the recesses between the metal wirings. The use of a thin layer of silicon nitride minimizes the problem of keyholes. According to the process method of the invention above, the use of an additional plasma treatment step (column 5) after the deposition of silicon nitride (column 3) will reduce nitrogen The number of pinholes in the silicon layer. This improvement is partly due to the atoms loosened on the silicon nitride surface being spattered and re-deposited to other locations'. Another reason is that the silicon nitride can be treated with the plasma treatment steps in column 5 of Table I. Make it more dense. In (column 5), another inert gas such as argon can replace helium; a mixed gas of argon and helium will also produce the same effect. Still referring to FIG. 4, a photoresist layer 20 is formed on the protection layer 24 by spin coating, and a via hole 3 is formed in the protection layer 24 and the oxide layer 22 by a conventional lithography and etching technique to expose the metal wiring. 20. The preferred hamster engraving of the interstitial hole 3 uses reactive ion etching or high-density plasma etching. Among them, the high-density plasma etching uses tetrafluoride Carbon (CF4), methane trifluoride (CHF3), and a mixed gas with helium or argon as the carrier gas. Referring to Fig. 5, the stripping of the photoresist 26 is performed by a plasma ashing process containing oxygen, and no photoresist is left in the keyhole area 30 '. The sequence of steps described above for the plasma treatment will also result in more dense silicon nitride with fewer pinholes. The size of this paper applies to the national standard (CNS) A4 specifications of 11 countries (21ϋχ 297mm).
--------訂---------I Λ' 經濟部智慧財產局員工消費合作社印製-------- Order --------- I Λ 'Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
t； j 6 1 B 25l6twfl.doc/002 __B7______ 五、發明說明（^ ) 爲能更了解包括電漿處理步驟（表格I的第5欄）的發 明製程之優點，以下表格Π顯示在不同厚度的氮化矽中（第 1欄至第3欄），以第i列至第5列中的增加射頻能量爲函 數的針孔瑕庇之百分比（Percentage of pinhole failures)。針 孔的察覺是藉由將氮化矽保護層板浸入溫度爲45°C，重量 比爲10%的氫氧化鉀（potassium hydroxide，K0H)溶液裡 30分鐘；當氫氧化鉀進入針孔時，這將造成金屬佈線20 的換色。表格Π顯示在電漿處理步驟中，當氮化矽厚度爲 3〇〇〇與5000埃之間，而射頻能量由0增加至250瓦特的 瑕疵率百分比之改變。 表格Π 鈍電漿處理針^ FL測試結果 氮化矽厚度 5Κ 4Κ 3Κ 射頻能量 瑕疵百分比 瑕疵百分比 瑕疵百分比 0瓦 30 70 100 50瓦 20 55 100 100瓦 10 50 100 150瓦 0 0 75 200瓦 0 15 95 250瓦 10 40 100 從表格中可以淸楚看見，當5000埃氮化矽層的射頻 能量在含氦的電漿處理步驟中由0瓦特增加至200瓦特t; j 6 1 B 25l6twfl.doc / 002 __B7______ 5. Description of the Invention (^) In order to better understand the advantages of the invention process including the plasma processing step (column 5 of Form I), the following table Π is shown in different thicknesses. Percentage of pinhole failures in silicon nitride (columns 1 to 3) as a function of increasing RF energy in columns i to 5. The pinhole was detected by immersing the silicon nitride protective sheet in a solution of potassium hydroxide (potassium hydroxide) at a temperature of 45 ° C and a weight ratio of 10% for 30 minutes. When potassium hydroxide entered the pinhole, This will cause a color change of the metal wiring 20. Table Π shows the percentage change in the defect rate when the silicon nitride thickness is between 3000 and 5000 angstroms and the RF energy is increased from 0 to 250 watts during the plasma processing step. Table Π Plasma treatment needle ^ FL test result Silicon nitride thickness 5K 4K 3K RF energy defect percentage defect percentage defect percentage 0 watt 30 70 100 50 watt 20 55 100 100 watt 10 50 100 150 watt 0 0 75 200 watt 0 15 95 250 watts 10 40 100 It can be clearly seen from the table that when the radio frequency energy of a 5000 angstrom silicon nitride layer is increased from 0 watts to 200 watts in a plasma processing step containing helium
II 本紙張尺度適用中國國家標i (CNS)A4規格（210 X 297公釐} " -- <請先閱讀背面之注意事項再填寫本頁) 469 61 8 25l6twfl.doc/002 八7 H7 五、發明說明（/17 ) 時，針孔瑕疵率將由30%減至〇% ;而當4〇〇〇埃氮化砂 層的射頻能量由100瓦特增加至150瓦特時，針孔瑕疵率 將由50%減至0% ;但若是氮化矽層犀度低於3000埃’ 此方法就比較無效，因爲太薄的保護層具有高針孔瑕疵率 之百分比。 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者’在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾’因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 -----:--------裝---- <請先閱讀背面之注意事項再填寫本頁) 訂---------41. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國固家標準（CNS)A4規格（210x 297公釐）II This paper size applies to China National Standard i (CNS) A4 (210 X 297 mm) "-< Please read the notes on the back before filling this page) 469 61 8 25l6twfl.doc / 002 8 7 H7 5. In the description of the invention (/ 17), the pinhole defect rate will be reduced from 30% to 0%; and when the RF energy of a 4000 Å nitrided sand layer is increased from 100 Watts to 150 Watts, the pinhole defect rate will be changed from 50 % To 0%; but if the silicon nitride layer is less than 3000 angstroms', this method is more ineffective, because the too thin protective layer has a high percentage of pinhole defects. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching 'Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. -----: -------- install ---- < Please read the notes on the back before filling this page) Order --------- 41. Intellectual Property Bureau, Ministry of Economic Affairs The paper size printed by the employee consumer cooperative is applicable to China Solid Standard (CNS) A4 (210x 297 mm)