TW469547B - Thin film interposer and method for manufacturing thereof - Google Patents

Thin film interposer and method for manufacturing thereof Download PDF

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Publication number
TW469547B
TW469547B TW88116929A TW88116929A TW469547B TW 469547 B TW469547 B TW 469547B TW 88116929 A TW88116929 A TW 88116929A TW 88116929 A TW88116929 A TW 88116929A TW 469547 B TW469547 B TW 469547B
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Taiwan
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layer
thin film
conductive
item
substrate
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TW88116929A
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Chinese (zh)
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Chiou-Shiung Jeng
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Innotest Inc
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Abstract

A thin film interposer includes a multi-layer thin film structure of and conductive bumps located at two sides thereon. The multi-layer thin film structure includes stacking dielectric layers and conductive layers. The method for manufacturing the thin film interposer first provides a substrate. A sacrifice layer is subsequently formed on the substrate in order to manufacture the first set of conductive bumps. The multi-layer thin film structure is then manufactured on the surface of the sacrifice layer, and the second set of conductive bumps is then formed on the surface thereof. Finally the substrate and the sacrifice layer are removed.

Description

469547 。 ____案號_8811692Q _年月日_修正_ 五,發明說明(1) 發明領域 本發明是關於連接界面,特別是指兩面具有凸塊 (bump)之薄膜連接界面(thin film interp〇ser)。 發明背景 隨著積體電路的高度集積化及功能不斷地強化,半導 體晶粒上之電路接點大幅地增加且密集,這種趨勢必須配 合成熟的構裝技術才能夠得以實現。 目前發展出的球柵陣列(Ball Grid Array ; BGA)構裝 及覆晶結構能夠符合構裝多腳化的需求,但是在安469547. ____Case No_8811692Q _Year Month Day_Amendment__ V. Description of the Invention (1) Field of the Invention The present invention relates to connection interfaces, especially thin film interposers with bumps on both sides. . BACKGROUND OF THE INVENTION With the high integration of integrated circuits and the continuous enhancement of their functions, the number of circuit contacts on semiconductor chips has increased significantly and become denser. This trend must be matched with mature construction technology to achieve this. The currently developed Ball Grid Array (BGA) structure and flip-chip structure can meet the requirements of multi-pin structure, but

路板(PCB)的過程仍存在著困擾,這是因為在電路P 卜作=岔度的電路接點具有相當的困難度及複雜 =,有必要針對習知技術提出改良,以求完善。 發明目的與概述 本舍明之主要目的即在接屮一績 作半導體裝置I 1,、連接界面,能夠 叮耻衣直兴具他裝置組裝的中介。 本發明之另一目的在接屮 插喃时、± 整半;體裝置之電路接點種p;=)連接界面1夠調 根據本發明,—.¾腺 位於其兩面之呼多導電、接界面包括-多層薄膜結構及 導電免凸塊’其中多層結構具有-…固 (via)。 序堆$ ’介電層内並包含多個導電枉 製作此薄膜連接界面的古土政认 ^ :層’並且利用該犧牲層材表面形成-犧There is still a problem in the process of the PCB. This is because the circuit contacts in the circuit P are quite difficult and complicated. It is necessary to propose improvements to the conventional technology to improve it. Purpose and summary of the invention The main purpose of Ben Sheming is to succeed as semiconductor device I 1, and to connect the interface, so that he can use intermediaries to assemble other devices. Another object of the present invention is ± half when connecting and inserting; the circuit contact type of the body device is p; =) the connection interface 1 is adjustable according to the present invention,-the ¾ gland is located on both sides thereof, and is conductive and connected. The interface includes a multi-layer thin film structure and a conductive bump-free bump, wherein the multi-layer structure has a ... ... via. The sequence stack contains a plurality of conductive 内 s in the dielectric layer, and the ancient soil recognition of the thin film connection interface is made ^: layer, and the surface of the sacrificial layer is used to form

第4頁 在多層薄胆t: ! 導電層形成多層薄膜結構,接著 結構之表面製作第—導 饵,接耆 I 一 .,且導電凸塊’最後再將底 46 954 泰號 88116929 年 月 曰 修正 五、發明說明(2) 材及犧牲層移除。 底下配合圖式及詳細說明,當更能瞭解本發明之特徵 及内容。 圖號說明 10 12 2 14 14 4 18 18 4 2 0 2 2 2 4 0 4 3 4 4 5 0 5 12 5 4 4 2 4 3 4 6 12 12 4 14 2 16 18 2 底材 穿孔 介電層 導電柱 介電層 導電柱 導電層 導電柱 多層薄膜結構 介電層 導電凸塊 多層薄膜結構 導電柱 導電凸塊 犧牲層 導電凸塊 接觸子L 導電層 接觸孔 導電凸塊 介電層 薄膜連接界面 導電層 導電柱 導電凸塊 介電層 導電層 導電凸塊 詳細說明 第一圖至第六圖描述本發明一較佳實施例之製作流 程。首先如第一圖所示,在一底材1 0表面形成一犧牲層 1 2 ,底材1 0為鋁板、玻璃或塑膠。在本實施例中,犧 牲層1 2為光阻,利用遮罩(mask)對犧牲層1 2進行蝕 刻,形成多個穿孔1 2 2 ,並在其中製作導電凸塊1 2Page 4: Multi-layer thin layers: The conductive layer forms a multi-layer thin film structure, and then the surface of the structure is made into a first-guide bait, which is connected to I-. And the conductive bumps are finally bottomed. 46 954 Thai 88881929 Amendment V. Description of the Invention (2) Material and sacrificial layer are removed. With the drawings and detailed descriptions below, the features and contents of the present invention can be better understood. Drawing number description 10 12 2 14 14 4 18 18 4 2 0 2 2 2 4 0 4 3 4 4 5 0 5 12 5 4 4 2 4 3 4 6 12 12 4 14 2 16 18 2 substrate perforated dielectric layer conductive Pillar dielectric layer conductive pillar conductive layer conductive pillar multilayer film structure dielectric layer conductive bump multilayer film structure conductive pillar conductive bump sacrificial layer conductive bump contactor L conductive layer contact hole conductive bump dielectric layer film connection interface conductive layer The conductive pillar conductive bump dielectric layer conductive layer conductive layer conductive bump detailed description FIGS. 1 to 6 illustrate a manufacturing process of a preferred embodiment of the present invention. First, as shown in the first figure, a sacrificial layer 12 is formed on a surface of a substrate 10, and the substrate 10 is an aluminum plate, glass, or plastic. In this embodiment, the sacrificial layer 12 is a photoresist, and the mask is used to etch the sacrificial layer 12 to form a plurality of perforations 1 2 2, and a conductive bump 12 is formed therein.

4 6 9 5 4¾ 88116929_年月日_魅_ 五、發明說明(3) 4 ,製作導電凸塊1 2 4可以利用電鍍或無電極電鍍在穿 孔1 2 2累積金屬,例如金、鎳或者鋁。其中,若使用電 鍍製作導電凸塊1 2 4 ,較佳的方式係在形成犧牲層1 2 之前,先在底材1 0表面形成一易與底材1 0剝離之剝離 層,例如鋁粉等導電類的材料。 接著在犧牲層1 2表面製作多層薄膜結構。首先形成一介 電層1 4 ,如第二圖所示,介電層1 4具有足夠之機械強 度,較佳者為聚亞醯胺(Polyimide)。將介電層1 4塗 佈在犧牲層1 2表面的方法之一係使用旋轉塗佈(Sp i η Coating )進行。下一步驟便根據導電凸塊1 2 4之圖 案,蝕刻介電層1 4形成多個接觸孔1 4 2 ,並在其中製 作導電柱1 4 4與導電凸塊1 2 4接觸。較佳者,導電柱 1 4 4為鎢。 完成製作導電柱1 4 4之後,於介電層1 4表面根據 電路圖案形成導電層1 6 ,成為如第三圖所示之狀態,其 中,導電層1 6為金屬,較佳者為鋁、銅、鋁銅合金或鋁 矽銅合金。形成導電層1 6的方法可分成物理氣相沉積技 術(P V D )以及化學氣相沉積技術(C V D),然後再根據電路 圖案I虫刻出線路。另一種方法係在介電層1 4表面沉積遮 蔽層,接著根據電路圖案蝕刻遮蔽層,並於遮蔽層被蝕去 的部份填入金屬,再將遮蔽層全部去除。 接著在導電層1 6上再形成一介電層1 8 ,並且依前 述步驟製作接觸孔1 8 2 ,以及成長導電柱1 8 4 ,成為 如第四圖所示之狀態。後續依所需的線路再製作導電層及 介電層而形成一多層薄膜結構,其過程如前面所述。4 6 9 5 4¾ 88116929_ 年月 日 _Character__ 5. Description of the invention (3) 4 To make conductive bumps 1 2 4 You can use electroplating or electrodeless plating to accumulate metals in the perforations 1 2 2 such as gold, nickel or aluminum . Among them, if the conductive bumps 1 2 4 are made by electroplating, a better way is to form a release layer on the surface of the substrate 10 which is easy to peel off from the substrate 10 before forming the sacrificial layer 12, such as aluminum powder, etc. Conductive materials. Next, a multilayer thin film structure is formed on the surface of the sacrificial layer 12. First, a dielectric layer 14 is formed. As shown in the second figure, the dielectric layer 14 has sufficient mechanical strength, preferably polyimide. One method of applying the dielectric layer 14 to the surface of the sacrificial layer 12 is to use spin coating. In the next step, the dielectric layer 14 is etched to form a plurality of contact holes 1 4 2 according to the pattern of the conductive bumps 1 2 4, and conductive pillars 1 4 4 are formed therein to be in contact with the conductive bumps 1 2 4. Preferably, the conductive pillars 1 4 4 are tungsten. After the fabrication of the conductive pillars 1 4 4 is completed, a conductive layer 16 is formed on the surface of the dielectric layer 14 according to the circuit pattern, and becomes the state shown in the third figure. Among them, the conductive layer 16 is a metal, preferably aluminum, Copper, aluminum copper alloy or aluminum silicon copper alloy. The method of forming the conductive layer 16 can be divided into a physical vapor deposition technique (PVD) and a chemical vapor deposition technique (CVD), and then the wiring is carved according to the circuit pattern I. Another method is to deposit a masking layer on the surface of the dielectric layer 14, and then etch the masking layer according to the circuit pattern, and fill the masked portion with metal, and then remove the masking layer completely. Next, a dielectric layer 1 8 is formed on the conductive layer 16, and the contact holes 1 8 2 are formed according to the foregoing steps, and the conductive pillars 1 8 4 are grown into the state shown in the fourth figure. Subsequent fabrication of a conductive layer and a dielectric layer according to the required circuit to form a multilayer thin film structure, the process is as described above.

4 6 9 5 4· 7案號RR^]gg2Q 年 月__s_修正 五、發明說明(4) 完成製作多層薄膜結構之後’接下來根據其表面介電 層1 8内之導電柱184之圖案’在介電層1 8表面製作 導電凸塊1 9與導電柱1 8 4接觸’如第五圖所示。製作 導電凸塊1 9可以如同形成導電凸塊1 2 4之步驟,即利 用一光阻形成數穿孔,再於穿孔累積金屬’或者利用I β Μ 的C 4蒸鑛製程,或者以網板印刷(s c r e e η P r i n t i n g )來 製作導電凸塊1 9 e 製程 底材1 Ο 第六圖所 就第 可以對應 18 4, 電凸塊1 電路板的 導體裝置 配置的情 者,藉由 導體裝置 接點,換 應之薄膜 過去一塊 上顯然具 也有助益 移除, 示之兩 六圖所 南_密度 導電層 2 4, 電路接 與電路 况下, 導電層 重新走 言之, 連接界 電路板 有較大 著便將 得到如 塊1 9 導電柱 面之導 般印刷 作為半 電路板 。再 面之半 之電路 由相對 相較於 在應用 去除, 界面。 導電凸 且透過 至下表 對應一 以用來 不改變 置安裝 連接界 電路板 裝置藉 路板, 本發明 或模組 這裡,薄膜連接界面大致完 並利用蝕刻液將犧牲層1 2 面具有導電凸塊之薄膜速接 示之裝置而言,其上表面之 電路接點之半導體裝置,並 16及導電柱144電連接 導電凸塊124的配置可以 點,換句話說,這個裝置可 板之間的一個中介,能夠在 提供高密集接點數的電子裝 1 6可以提供安裝至此薄膜 線(R e - R 〇 u t丨n g ),以對應 電路接點配置不同的半導體 面,均可以安裝至同一塊電 僅能適用一種半導體裝置, 的彈性,這對於多晶片封裝4 6 9 5 4 · 7 case number RR ^] gg2Q year __s_ amendment V. description of the invention (4) after completing the production of a multilayer thin film structure 'next according to the pattern of the conductive pillars 184 in the surface dielectric layer 18 'Producing a conductive bump 19 on the surface of the dielectric layer 18 and making contact with the conductive pillar 1 8 4' is shown in the fifth figure. The production of conductive bumps 19 can be the same as the steps of forming conductive bumps 1 2 4 by using a photoresist to form a number of perforations, and then accumulating metal in the perforations' or by using a C 4 vaporization process of I β Μ, or printing on a screen. (Scree η P rinting) to make conductive bumps 1 9 e process substrate 1 〇 The sixth figure can correspond to the 18, the electrical bump 1 circuit board configuration of the conductor device, the conductor device contacts Obviously, the changed film on the past can also help to remove it. As shown in the two or six pictures, the density of the conductive layer 2 4, the circuit connection and circuit conditions, the conductive layer is re-introduced, the connection circuit board has a As a result, it will be printed as a half-circuit board like the guide of a 19 conductive cylinder. The remaining half of the circuit is removed from the interface compared to that in the application. The conductive bumps are transmitted to the following table and correspond to one for mounting and connecting the circuit board device borrow circuit board without change. In the present invention or module, the thin film connection interface is almost completed and the sacrificial layer 1 2 has conductive bumps on the surface using an etching solution. As for the device of the film quick connection shown in the block, the configuration of the semiconductor device on the upper surface of the circuit contact, and the 16 and the conductive post 144 electrically connected to the conductive bump 124 can be configured, in other words, this device can An intermediary, capable of providing high-density electronic components 16 can be provided to this thin film line (R e-R 〇ut 丨 ng), different semiconductor surfaces corresponding to the circuit contact configuration can be installed on the same piece Electricity can only be applied to one type of semiconductor device, which is flexible for multi-chip packages

第7頁 46 95 4 7 案號 88116929 曰 修正 五、發明說明(5) 強化。如第七圖所示,其製作了複數個導電層2 0 ,相鄰 之導電層20之間具有介電層22 ,並藉由介電層22内 之導電柱2 2 2彼此連接。這種具有複數個導電層2 0的 結構可以提供增加其他額外的功能,例如分擔半導體裝置 之電路佈局。 ' 這種兩面均具有導電凸塊的薄膜連接界面並且具有增 進信號傳輸速度的優點。如第八圖所示,一薄膜連接界面 3 0上提供半導體裝置A,B及C安裝,半導體裝置A, B及C之間的信號可以藉由底下的薄膜連接界面3 0傳 遞,其信號的傳輸路徑較短,有助於增加信號處理的速 度。 在其他的實施例中,形成導電層與介電層的次序不同 所產生之薄膜連接界面係如第九圖與第十圖所示。第九圖 所示裝置之多層薄膜結構4 0之二面均為導電層4 2 ,其 係在製作多層薄膜結構4 0時,依序形成導電層4 2及介 電層43 ,使多層薄膜結構40二面為導電層42 ,二導 電層4 2之間利用介電層4 3内的導電柱4 3 2電連接, 而導電凸塊4 4及4 6則分別與其連接之導電層4 2接 觸。 而第十圖所示之裝置之多層薄膜結構5 0之底面為介 電層5 1 ,上表面為導電層5 2 ,這是在製作多層薄膜結 構50的過程中,先形成介電層5 1並製作導電柱5 1 2 之後,再形成導電層5 2 ,使底面之導電凸塊5 4與導電 柱5 1 2相連接,經由導電層5 2與上表面之導電凸塊5 6電連接。在另一種實施例中,亦可以依序先形成導電層Page 7 46 95 4 7 Case No. 88116929 Amendment V. Description of Invention (5) Strengthening. As shown in the seventh figure, a plurality of conductive layers 20 are fabricated, and a dielectric layer 22 is provided between adjacent conductive layers 20, and is connected to each other through conductive pillars 22 in the dielectric layer 22. Such a structure having a plurality of conductive layers 20 can provide additional additional functions, such as sharing the circuit layout of a semiconductor device. '' This thin-film connection interface with conductive bumps on both sides has the advantage of increasing the speed of signal transmission. As shown in the eighth figure, a thin film connection interface 30 is provided for mounting semiconductor devices A, B, and C. The signals between the semiconductor devices A, B, and C can be transmitted through the bottom thin film connection interface 30. The shorter transmission path helps increase the speed of signal processing. In other embodiments, the order of forming the conductive layer and the dielectric layer is different. The resulting thin film connection interface is shown in Figures 9 and 10. Both sides of the multilayer thin film structure 40 of the device shown in the ninth figure are conductive layers 42. When the multilayer thin film structure 40 is manufactured, the conductive layer 42 and the dielectric layer 43 are sequentially formed to make the multilayer thin film structure. The second side of 40 is a conductive layer 42. The two conductive layers 42 are electrically connected by the conductive pillars 4 3 2 in the dielectric layer 4 3, and the conductive bumps 4 4 and 46 are in contact with the conductive layer 4 2 connected to them. . The bottom surface of the multilayer thin film structure 50 of the device shown in the tenth figure is a dielectric layer 5 1 and the upper surface is a conductive layer 5 2. This is the process of forming the dielectric layer 5 1 in the process of manufacturing the multilayer thin film structure 50. After the conductive pillar 5 1 2 is fabricated, a conductive layer 5 2 is formed, so that the conductive bump 5 4 on the bottom surface is connected to the conductive pillar 5 1 2, and is electrically connected to the conductive bump 5 6 on the upper surface through the conductive layer 5 2. In another embodiment, the conductive layer may be formed first in sequence.

469547 案號88116929 年月日 修正469547 Case No. 88116929 Amendment

第10頁Page 10

Claims (1)

4 6 9 5 4 號 88116929_年月日__ 六、申請專利範圍 1 . 一種薄膜連接界面的製作方法,包括: 提供一底材; 在該底材表面形成一犧牲層; 於該犧牲層製作多個穿孔; 在每一該穿孔製作第一組導電凸塊; 在該犧牲層上製作多層薄膜結構,其中包括一或多個導電 層及介電層,其中該介電層並形成有接觸孔,其内有導 電柱; 在該多層薄膜結構表面製作第二組導電凸塊; 移去該底材;以及 移除該犧牲層。 2 ·如申請專利範圍第1項所述之製作方法,其中係使用 無電極電鍍或電鍍製程製作第一組導電凸塊。 3 ·如申請專利範圍第1項所述之製作方法,其中更包括 在形成該犧牲層之前,先於該底材表面形成一易與該底材 剝離且易導電之剝離層1並且在移去該底材之後,將該剝 離層移除。 4 ·如申請專利範圍第1項所述之製作方法,其中形成之 該多層薄膜結構之二面為介電層。 5 _如申請專利範圍第1項所述之製作方法,其中形成之 該多層薄膜結構之二面為導電層。 6 ·如申請專利範圍第1項所述之製作方法,其中形成之 該多層薄膜結構之最外二面分別為導電層及介電層。 7 ·如申請專利範圍第1項所述之製作方法,其中係使用4 6 9 5 4 No. 88116929_Year Month__ VI. Application for Patent Scope 1. A method for manufacturing a thin film connection interface, comprising: providing a substrate; forming a sacrificial layer on the surface of the substrate; and making on the sacrificial layer Multiple perforations; making a first set of conductive bumps at each of the perforations; making a multi-layer thin film structure on the sacrificial layer, including one or more conductive layers and a dielectric layer, wherein the dielectric layer is formed with a contact hole A conductive pillar is formed therein; a second group of conductive bumps is made on the surface of the multilayer thin film structure; the substrate is removed; and the sacrificial layer is removed. 2 · The manufacturing method as described in item 1 of the scope of patent application, wherein the first group of conductive bumps is manufactured using an electrodeless plating or plating process. 3. The manufacturing method as described in item 1 of the scope of patent application, which further includes forming a peeling layer 1 which is easy to be peeled off from the substrate and easily conductive before the surface of the substrate is formed before the sacrificial layer is formed and is being removed After the substrate, the release layer is removed. 4. The manufacturing method as described in item 1 of the scope of patent application, wherein the two surfaces of the multilayer thin film structure formed are dielectric layers. 5 _ The manufacturing method described in item 1 of the scope of patent application, wherein the two surfaces of the multilayer thin film structure formed are conductive layers. 6. The manufacturing method according to item 1 of the scope of patent application, wherein the outermost two surfaces of the multilayer thin film structure formed are a conductive layer and a dielectric layer, respectively. 7 · The production method described in item 1 of the scope of patent application, wherein 46 35 4 7 案號8811692Θ 年月曰_ 該 作 製 中 其 法 方 作 製 。之 塊述 凸所 電項 導1 組第 二圍 第範 該利 作專 圍製請 職刷申 專印如 青Γ版* ;、網8 六 電 無 以 再 , ο 孔塊 觸凸 接電 生導 產組 阻二 光第 用該 使成 係形 ’ 積 驟累 步孔 的觸 塊接 凸該 電於 導鍍 二電 第極 法 方 作 製 -I]- 之B 一 I 述用 所使 項係 IX , 第驟 圍步 0;已 AV ί 白 利塊 專凸 請電 申導 如組 玄 --口 作 製 中 其 程 製 度 蒸 4 C 的 介 亥 Α=α 層 電 導 及 層 電 介 _ . 個 括多 包或 ,i 面括 界包 接其 連 ’ 膜構 薄結 種膜 一 薄 * 層 ο多 上 面 表 及二 以之 ;膜 層薄 電層 介多 亥亥 -νδ-a 過於 穿位 枉’ 電塊 導凸 個電 多導 有組 成二 形第 並及 層組 電一 第 其 面 接 連 莫 月 薄。 之層 述電 所導 項為 ο面 1 二 第外 圍最 範之 利構 專結 請膜 申薄 如層 ,多 1該 1 中 其 面 界 接 連 膜 薄 ο 之層 述電 所介 項為 ο面IX 二 第外 圍最 範之 利構 專結 請膜 申薄 如層 • 多 2該 1—I 中 第外 圍最 範之 利構 專結 青莫 =a 申薄 如層 - 夕夕 3該 一—一中 第 圍 範。 利屬 專金 請為 申層 如電 導 4該 1 中 面層面 界電界 接介接 膜層膜 薄電薄 之導之 述為述 所別所 項分項 ο面ο 其 其 5該 1-- 1ΦΙ 其 面。 界一 接之 連金 膜合 薄銅 之矽 itls 所及 項、 4金 1 合 第銅 圍lg 奸辄 、 tnnj 矛 專 請 申 如 銅 ' 呂 為 眉 金 其 面 界 接 連 膜 薄 之 述 所 項 ο 1—1 。 第者 圍胺 範醯 利亞 專聚 請為 申層 如電 .介 6該 一―Η -β— 其 面 界 接 -gc 膜 薄 之 述 所 項 ο -—Η 第 圍 範 利。 專鎢 請為 申柱 如電 ,導 7該 IX *^146 35 4 7 Case No. 8811692 The month of the year _ The legal system in this system. The block description of the electrical item guide 1 group of the second round Fanfanli for exclusive enlistment, apply for special printing, such as green Γ version * ;, net 8 Six power can no longer be, ο the hole block touches the convex to generate electricity The product group of the second group used the contact block of the product to accumulate the step-by-step holes, and the electrode was made by the second method of the first electrode of the second electrode -I]-. IX, step 0; step AV; Bai Li block has been specially requested to apply for guidance, such as the formation of the Xuan Xuan-Oral production process steamed 4 C of the medium A = α layer conductivity and layer dielectric _. Multi-pack or, i-plane bounding boundary enclosing its connection 'Membrane structure thin junction seed film a thin * layer ο more than the above table and two; the film layer is thin and the dielectric layer is more than helium-νδ-a is too penetrating 枉' The electric block and the electric multiconductor are composed of a bimorph and a layer group of electric wires, and their surfaces are continuously connected. The conductive term of the layered electric station is ο face 1. The second most peripheral structure of the special structure is required to apply a thin film, such that the surface boundary of the layer is connected to the thin film. The layered electric field is ο face IX. The second most popular structure in the periphery is requested to be thin and thin. • 2 2 The most popular structure in the periphery of 1-I is not suitable. = A The thin as the layer-Xixi 3 the first-one in the middle. Fan. Please refer to the application for a special deposit such as conductance 4, 1 and 1 for the mid-level boundary interface, electrical interface, and the interface of the thin film and thin film. The description of each item is as follows: o 5 o 1 o 1 o 1 o surface. Jie Yilian's continuous gold film and thin copper silicon itls, 4 gold and 1 copper bronze lg treacherous, tnnj spears please apply for copper, 'Lu Weimei Jin's face film is connected to thin film. Ο 1 -1 . The third party enlists Fan Lilia's reunion, please apply for the application layer. Please refer to the item described in the description of this one—Η-β—the surface interface is connected to the -gc thin film. For tungsten, please apply for Shen Zhu, such as electricity, IX * ^ 1 第13頁Page 13
TW88116929A 1999-10-01 1999-10-01 Thin film interposer and method for manufacturing thereof TW469547B (en)

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