TW468277B - Non-volatile flash memory cell with non-symmetric starting voltage - Google Patents

Abstract

A non-volatile flash memory cell with non-symmetric starting voltage comprises: a channel area, a doped area, a floating gate and a control gate. The channel area is located in the surface of a substrate, and between a source and a drain, wherein the source and drain are all located in the surface of the substrate. The doped area is located at an end of the channel area close to the source, and the type of a plurality of first impurities doped into the doped area is the same as the type of a plurality of second impurities doped into the substrate. The control gate is located above the channel area and is insulated from the channel area. The floating gate is located between the channel area and the control gate, and is insulated from the control gate and the channel area. The non-volatile flash memory cell with non-symmetric starting voltage can be expanded in such a manner that the doped area is not used. It is applicable to have a channel area that can be divided into a first channel area closer to the source and a second channel area closer to the drain. Furthermore, the starting voltage of the first channel area is larger than that of the second channel area.

Description

ο 8 27 7 V. Description of the invention (1) 1 Field of the invention The present invention relates to a non-volatile flash memory cell with an asymmetric starting voltage, in particular by increasing the starting voltage of some channel regions. Prevents improper erasure of non-volatile flash memory cells. 5-2 Background of the Invention: Because flash memory has the characteristics of being electrically erasable and programmable, and can simultaneously access each flash memory in the entire memory array. The unit cell (ce 1 1) performs the division and program, so it has been widely used as a memory that can repeatedly read and write data, such as digital cameras, which need to store data that will not disappear due to power interruption. The basic input or output system of the film or motherboard. Therefore, how to improve the performance of flash memory and reduce the cost of flash memory has become an important issue. As shown in Figure 1A, the common flash memory cell structure is a stacked structure. It includes at least source 11, drain 1, 2, floating gate 13 and control gate (C0ntr0l gate) 14, where source 11, drain 12, and control gate 14 are respectively connected to different power sources to The flash memory is programmed, read, and erased, and the floating gates 13 and 14 are controlled by a dielectric layer on the substrate. 5

Page 5d 6 8 27 7 Fifth 'Explanation of the invention (2) Surrounded β As for the unit cell of the N-type flash memory (substrate 10 is Ν 槊 substrate)' When the data is to be written, the system Ground the source 11 and apply positive voltages to the control gates 14 and 12 respectively. At this time, since the lightly doped drain is not used, part of the electrons are scattered into the floating gate 13 due to the surrounding media. The potential barrier of the electrical layer I5 is trapped at the floating gate 13. Since the electrons located in the floating gate 13 will affect the threshold voltage of the channel region between the source 11 and the drain 12 and thus control the conduction of the channel region, they are located in the floating gate 13 The electrons represent the data and can be read by whether the channel area is conducting. When erasing the existing data in the flash memory, the source electrode 11 is grounded, and the control gate 14 is applied with a positive voltage lower than the drain electrode 12 by using 卩 〇 | 1〇1 · -Nordheim tunnel ing to make The electrons of the floating gate 13 disappear through the drain 12 to ensure that the conduction of the channel region is no longer affected by the electrons previously input to the floating gate 3. Obviously, if the floating gate 13 cannot be restored to the state before the electrons are injected during erasing, whether it is the under erase of the electrons remaining in the floating gate or not only the injected electrons are removed, even the original All the electrons belonging to the floating space 3 are removed, so that the floating gate 13 is over-erased with a positive charge 16 (0ver :), and the first B graph 'will affect the performance of the memory cell. For example, when a certain flash memory cell is over-erased, the memory cell is again; g Kuyi: * 也 目 丨 丨 # λ All I '^ Into the degree of dendrite is written into the shell material' then enter 沣The electronic meeting of the brake 丨 3

1 6 8 27 7 _ _ ________ ****---- 5. Explanation of the invention (3) Neutralized by the positive charge 16 in the floating gate 13 if the number of neutralization is so large that the remaining electrons The continuity of the channel region cannot be changed, that is, the electrons in the floating gate 13 cannot be detected when reading the data, so that this flash memory cell cannot play the role of storing data. Furthermore, if the degree of over-erase is so strong that the positive charge 16 on the floating gate 13 is so large that the channel area is automatically turned on, the flash memory cell cannot be used to store any data at this time. In addition, since the flash memory array usually contains many flash memory cells at the same time in practical applications, such as bit lines in a low-density, high-reaction-rate "NOR" structure, so a single The abnormal operation of the flash memory cell often leads to the failure of the entire flash memory array. In a note pack, it is necessary to flash into a crystal. Every time you realize it, you must remember it again and use the needle to record the process. You must be able to pass the question. In the right place, the crystal can't measure and write. There is a new one to remove the circuit. The physical test is also tested locally and added as a result. Add it without trial, and set the frontal cell mixed with the frontal cell except for the test side to regenerate the interphase. 1) The body array and try to remember the structure to test if (C recorded Yicheng added granules and flashes. It ’s been added to the crystal. It ’s another way to deal with the problem of erasing improperly is to use the so-called split pole (spiU gateh is shown in the first circle C. At this time, the channel area can be divided into two parts. One part only has the control opening η on it, and the other part has the control 17 and the floating opening 18 on it. Obviously, like the first, even if the floating gate i 8 appears in the floating gate due to improper erasure at this time. Positive electricity 6 8 27 7 • Description of the invention (4) ----- --—— There is γ stand, once the system is not located, the conduction in the channel area under the moving gate 18 cannot be controlled. Control: dynamic = 8: square: channel = domain conduction or not can still be controlled and most of the problem of improper erasure can be effectively prevented, the carrier system use efficiency is about 100 times that of the extremely hot carrier injection method The source and operation of the method inject electrons into the floating gate 18. Of course, the split gates, ie, the type 86, m and Τ have 4 variations, such as u. S_4,639 · 89 3. us 5,4 LS · 4'868, 629, etc. The split-lane theory, comparing Figure -A and Figure C can be seen, using the structure of the 8 4 flash memory cell structure ^ = structure It ’s complicated, especially the control question.] == The difference is obvious, so the process will also be Cangcho, and the cost is higher between the floating f, 1 18 and the floating 13_. Moreover, the length of the system must be longer than The premise of the same control τ, because the surface of the flash memory cell of the control pole is also longer than = degree, so the use of split closure can be seen from the previous discussion, the structure of the cell is not impossible. All kinds of flash memory are improper but will face complex process; 2 Improper, 〶 is able to prevent erasure = new flash memory Zhao Jing cell 'for this reason' must be able to be quickly written and erased, etc .: The purpose and summary of the invention of flash memory crystal 5'3:

8 27? ------V. Description of the invention (5), in the background of the present invention, the disadvantages of the traditional flash memory Zhao Jing cell: hair flash memory. ~ Machine erases improper non-volatile cell ΐ! ::: one purpose is to raise the stack flash memory without obvious changes ... to prevent flash memory from failing due to improper removal Unit cell structure. The purpose of the present invention also includes the problem of preventing and stopping the flash memory from being invalidated due to excessive erasure. The flash memory is in the structure for the aforementioned purposes. : With asymmetric starting electric miscellaneous area, floating gate and control gate ^ wherein, ^ 3, channel area, mixed surface, and located between the source and drain, in the region is located on the surface of the surface of the substrate Inside; the doped region is located in the channel region = both the pole and the drain are at the bottom and most of the first impurities doped to the doped region are close to the source, and the majority of the second impurities have the same electrical properties; Insulation and substrate doped insulation with the channel area ... The dynamic closing system is parallel to the area, and at the same time insulated from the control gate and the channel area. Between the Q-domain of the channel and the control gate, the non-volatile with a symmetrical starting voltage can still be extended to indefinite use of the doped region, as long as the channel :: memory cell

: 6 8 277 V. Description of the invention (6) The first channel region near the source and the second channel region closer to the drain, and the starting voltage of the first channel region is greater than the starting voltage of the second channel region. can. In other words, the key of the present invention is to avoid the occurrence of improper erasure, but to prevent the abnormal operation of the non-volatile flash memory cell with a channel region with a large initial voltage. 5-4 Detailed description of the invention: The inventor of the present invention pointed out a key point: To eliminate the lack of improper conduction of the channel area below the floating gate when the floating gate is erased, an effective solution mechanism is to divide the channel area into Erase the two parts that are conducted by the improper floating gate and the two parts that will not be erased by the improper floating gate, and then adjust the conduction of the channel area that is not erased by the improper floating gate. Can make the entire channel area conductive or not not affected by the improper conduction of the channel area below the floating gate. Obviously, the conventional split gate only divides the channel area into the floating gate which will be improperly erased and will not be conductive. A method of conducting by improperly removed floating gates. According to the main lack of conventional use of interstitial cells: the process is complex and the area occupied is large, due to control; the key to the conduction of the channel area is the starting voltage of the channel area, not the gate and substrate (channel area). The distance between the 'inventors of the present invention proposed another! 3 methods of segmenting the area: Do not change the stacked flash memory cell

Page 10-; 8 27 7 V. Description of the invention (7) ---------- The configuration of the control gate and floating opening 'but change the initial distribution in the channel area' with an asymmetric starting voltage The distribution segments the channel area. According to the above discussion, 'the inventor of the present invention proposes a non-volatile flash memory cell', as shown in the second diagram A, it contains at least a channel region 2 and a second channel region 22 and a source. Electrode 23, drain 24, floating gate 25 and control gate 27. The channel area is located in the surface of the substrate 20 (such as a P-type substrate) and between the source 2 3 and ί and the electrode 2 4 in the surface of the substrate 20. In this channel area, it can be divided into more The first channel region 21 near the source electrode 23 and the second channel region 22 near the electrode 24 and the start voltage of the first channel region 21 are larger than the start voltage of the second channel region 22. Control Gates 2 and 6 are located on the channel area and insulated from the channel area. Floating gates 25 are located between the channel area and control 閛 25, and are insulated from both the control gate 26 and the channel area. Of course, floating gate 23 and control gate 24 Is located in the dielectric layer 27, so that the substrate 20, the floating gate 23 and the control gate 24 are insulated from each other. Obviously, because the starting voltage of the first channel region 21 is 22 minutes lower than that of the second channel region The critical voltage is large, so when writing data to this flash memory cell, the depletion region near the end 24 will extend to the source 23, that is, the source hot carrier is injected. Method will electronics (P-type substrate

Page 11 λ ο 8 27 7 Five 'invention description (8) Minority carriers) are input to the floating gate 23', but as the number of electrons in turn increases, the input point of electrons will gradually approach the electrode 24. Because at this time the starting voltage of the first channel region 21 is large, that is, when the control gate 26 applies a voltage to make the second channel region 22 just turn on, the first channel region 21 is not turned on. Applying a larger voltage: The first channel region 21 can be turned on. Therefore, as shown in the second figure b, even if the erasure is improper (such as the occurrence of a positive charge 28 in the floating gate 25), the second channel region 22 under the floating gate 25 is abnormally connected, as long as the The starting voltage is so high that it will not be turned on by the appearance of the positive charge 28, and the entire fast memory cell will not fail. In other words, by adjusting the starting voltage of the first channel region 21, you can make The function of the flash memory cell is not affected by improper erasure during use. Of course, the data of the test process can be used to determine how large the starting voltage of the first channel area 21 must be to prevent the improper erasure. Here, the most common method for adjusting the starting voltage is to use ion implantation. Impurities 293 (such as boron ions) are driven into the channel region near the end of the source electrode 23 to form a doped region 296 (the channel region where the doped region 29 6 is located can be regarded as the first channel region 21 and pass to other parts of the region The portion can be regarded as the first channel region 22), as shown in the second D diagram (only a part of the dielectric layer 27 is drawn here). The electrical properties of the impurities doped in the doped region 296 are different from the electrical properties of the impurities in the substrate 20, and because the starting voltage is close to the state of the substrate 20 surface, the doping The thickness of the miscellaneous region 29 6 is usually greater than that of the channel region.

Page 12 468 277

The thickness is small (comparing the second D 圊 and the second A when they are driven into the substrate 20 with a large angle implantation technique.) And when the direction of the impurities 29 3 series 20 and the angle of the surface of the substrate 20 these impurities The penetration of 293 is about 20 degrees. Furthermore, because the starting voltage is inversely proportional to the floating capacitance, the area capacity of the first channel can be adjusted to be smaller than the capacity of the second channel area. That is to say, it is not necessary to form a difference. The dielectric layer of the capacitor is between the dielectric layer 25 and the substrate 20 and the electrical domain of the floating inter-gate dielectric layer and the floating inter-gate dielectric layer are used to adjust the starting voltage and pass through the ocean. Adjust the starting voltage by moving the brake. Finally, when it is necessary to erase this cell voltage and apply a negative voltage to the control gate 2 6 Nordheim tunneling will float between the 'as long as the drain 2 3 is connected to a positive power' can use Fowlor The electron of -2 5 is drawn to the drain electrode 24. Obviously, since the present invention can effectively prevent the failure of the flash memory cell caused by improper erasure, the present invention can prevent the N-type flash memory from being damaged in the NOR. Flash memory than structure is invalid due to over-erase Also, since the present invention directly modifies the structure of the BS cell to prevent improper erasure by directly modifying the flash memory, it is not necessary to use a test circuit to test the formation of a good flash memory array, which can save crystals. The grain area can also save test time and reduce costs. By comparing the second A picture, the first person circle and the first c picture, we can see that

Page 13 46 8 27 7 V. Description of the invention (ίο) The invention is basically a stockpile flash memory cell, which is controlled to be parallel to the floating gate 25 and the floating gate 25. The bottom of the control gate 26 is more than the floating gate. The top of 25 is far away from the substrate 20 'and the shapes of the two are also very simple. Both can be formed by a deposition process and a lithography etching process, and the formation of the control gate 26 does not require any process to form the first C The curved control gate 26 shown in the figure, that is, the manufacturing process of the present invention is simpler than the conventional flash memory using split gates. Furthermore, although the floating gate 23 is parallel to the substrate 20 in the second A diagram, the present invention is not limited to this. The focus of the present invention is on the asymmetry of the starting voltage in the area. The use of the starting voltage close to the source 23-terminal to prevent erasure of improper abnormal conduction β, as for both the floating gate 25 and the control gate 26. The configuration is adjustable. Finally, to increase the dielectric constant and increase the time of electrons in the floating gate 25, as shown in Figure 2C, the control gate 26 and the floating gate 25 are connected by a composite dielectric layer 29. Separated. Here the composite dielectric layer 29 is formed by overlapping three dielectric layers. The material of the middle layer is one of the following:-Nitrided or gas-oxidized and the two layers on the surface are oxidized Floor. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 14 8 277 Brief description of the diagram The first diagram A is a schematic diagram of the structure of a common stacked flash memory cell. The first diagram B is a diagram of a common stacked flash memory cell when it encounters excessive erasure. Missing schematic diagram; Figure C shows the structure of a common flash memory cell using a split gate, and Figure D shows a common flash memory cell using a split gate when it is over-erased. Missing schematic diagram; Figure A is the intention of a structure of the flash memory cell proposed by the present invention, and Figure B is the mechanism of the improper erasure prevention of the flash memory cell proposed by the present invention Schematic diagram; the second diagram C is the intention of another structure of the flash memory cell proposed by the present invention, and the second diagram D is the intention of another structure of the flash memory cell proposed by the present invention .

Page 15 3 277 Schematic representation of the main symbols: 10 substrate 11 source 12 drain 13 floating gate 14 control gate 15 dielectric layer 16 positive charge 17 control gate 18 floating gate 20 substrate 21 first Channel region 22 Second channel region 23 Source 24 Drain 25 Floating gate 26 Control gate 27 Dielectric layer 28 Positive charge 293 Impurity 296 Doped region

Page 16

Claims (1)

46 8 277 Case No. 89116493 Amendment VI. Patent Application Scope 1. A non-volatile flash memory unit cell, which includes at least: a channel region, which is located in the surface of a substrate and located in a Between the source and a drain, wherein the source and the drain are both located on the surface of the substrate; a doped region is located at an end of the channel region near the source, where doping The electrical properties of the majority of the first impurities to the doped region are the same as the electrical properties of the majority of the second impurities doped to the substrate; a control gate, which is located on the channel region and is the same as the channel region Insulation, and a floating gate, the floating gate is located between the passage area and the control gate, and is simultaneously insulated from the control gate and the passage area. 2. For the non-volatile flash memory cell of the first patent application scope, the control gate is approximately parallel to the floating gate. 3. For the non-volatile flash memory cell of item 1 of the patent application, wherein the thickness of the above-mentioned doped region is smaller than the thickness of the channel region. 4. For the non-volatile flash memory cell of item 1 of the patent application, wherein the above substrate is a P-type substrate. 5. For example, the non-volatile flash memory cell of item 2 of the patent application scope, wherein the first impurity is boron ion. 4 6 8 27 7 _Case No. 89U6493_Year_Month_Character_ 6. Application for patent scope 6. For the non-volatile flash memory cell of the patent application scope item 1, the above-mentioned first impurity is ion The implantation method hits the channel area to form the replacement area. The technique, the cell cloth, crystallinity, body angle, remembering that the question is about the fast quality of the heterogeneous wave, which is not the least, the 5th method is enclosed. Fan Zhicai Lizi Di specifically departed from the request to enter the statement as described above. 7. The crystal plane surface of the traditional Chinese medicine remembers the material and flashes. The non-material description of the quick and sexual swing to the sender. Miscellaneous one. Fan Didu Li 20 should be asked to be as big as China ’s request, the degree is 8 cell angles and 1 ο intersegment crystals, the quality of lightning, fast mediating, recurrence, non-reciprocal, inter-system, etc. * Ask the first action ma '--- ^ Fan Qili and the special gate request the system to apply the control as the 9th cell in the crystalline form of the layer to interrogate the electric fast media ^ The three layers of non-folding restatement by the Department Item level 9 qualitative frtio _ Wai £ 介 介 j 彳 合 ί-L special complex Hai f 1 ". Zhongshen LP's day aa column recalls the flash layer of the material flash material fast fe \ pm of the middle term of ο a-4 □ the first element of the fragmentation of the electrification range nitrogen oxide layer nitrogen Or please make the silicon representation as above t: Ρ · -Η 1 One cell crystal remembers itself = ° Flashing hair £ Γ Wave utp of _ r 1 Please refer to page 18 4 6 8 27 7 _ Case No. 89116493_ Year Month __ VI. Patent Application Fan Yuan where the two layers of the above three dielectric layers are oxide layers. 13. The non-volatile flash memory cell according to item 1 of the patent application, wherein the floating gate and the substrate are separated by a dielectric layer. 1 4. If the non-volatile flash memory cell of item 1 of the patent application scope, a plurality of electrons are input to the floating gate by a source hot carrier injection method. 1 5. A type of non-volatile flash memory cell including at least: a channel region, which is located in the surface of a substrate, and a source and a drain in the surface of the substrate Here, the channel region can be divided into a first channel region closer to the source and a second channel region closer to the drain, and the starting voltage of the first channel region is lower than that of the second channel. The starting voltage of the area is large;-a control gate, which is located on the channel area and is isolated from the channel area; and a floating gate, which is located between the channel area and the control gate, and The control gate is insulated from the channel area. Page 〖9 〇 8 27 7 _Case No. 89116493_year month__ Sixth, the scope of patent application First impurities. 1 8. The non-volatile flash memory unit cell according to item 17 of the scope of patent application, wherein the first impurity mentioned above is hit into the channel region by an ion implantation method. 19. The non-volatile flash memory cell according to item 17 of the patent application scope, wherein the first impurity mentioned above is driven into the first channel region by a large-angle implantation technique. 11 Crystal system. The body ’s small memory can be remembered, the flash layer ’s capacitance, the fast mass, and the electricity ’s dielectric layer. The interstitial non-brake movement is described in the floating room. The domain of the first district of Yuli asked the Tongshenzhong second as its 0. 'The 2 cells than page 20