TW466734B - Small sized semiconductor device with shared contact plug - Google Patents

Abstract

A method for producing a small sized SRAM comprises at least a shared contact plug. The method comprises: forming a gate oxide layer and a polysilicon on the surface of a semiconductor substrate as a gate of a SDRAM; forming a dielectric layer on the periphery of the gate, in which the cross-section of the upper layer of the gate is not covered by an oxide layer, and in which one side of the gate sidewall free of a spacer is also not covered by a dielectric layer; forming a gate sidewall on the silicon nitride spacer, in which a gate sidewall has only a spacer; forming a heavily doped ion region in the semiconductor substrate between the two gates, and a lightly doped drain region between the spacer bottom of the gate sidewall and the semiconductor substrate; forming a silicide on the gate and the source/drain, in which the portion of the gate sidewall having no a spacer is also covered with a silicide layer; forming an inter-metal dielectrics on the surface of the chip, and etching out a shared contact plug between the gate and the source/drain diffusion region.

Description

466734 V. Description of the Invention (l) 5 -1 Field of the Invention: The present invention relates to a static random access memory (SRAM) device, and particularly to a semiconductor device having a shared contact plug. To get small size components. 5-2 Background of the Invention: Recently, the demand for semiconductor components has rapidly increased due to the large number of electronic components used. In particular, the rapid spread of computers has increased the demand for semiconductor components. Since hundreds or thousands of transistors are required to form a complex integrated circuit ^ built on a single semiconductor wafer, in order to increase the density of electronic components in the integrated circuit 'the size of the component must be maintained, and the original characteristics of the component must be maintained. The steep reduction in component size and a simplified manufacturing method are repeated. Figure F shows a conventional static random access memory (Sra's J, Figure A. Figure A shows a traditional N-type static random access memory). As an example, the silicon substrate 100 is a P-well, the gate 140 is polycrystalline, and the gap wall is 24. The random state random access memory of ΐϊ must first define the position of the gap wall, so that t # time And complexity. Figure -B uses traditional static random storage = 'r: body as an example' and the same layers as in Figure -a are labeled with the same: except for the structure in Figure -A, this manufacturing method Add two to cut 250 and-Photoresistance ㈣G. Figure -C uses traditional static random i

Page 5 466734 Take memory as an example to show. Except for the removal and layer of the layer, the lightly doped pattern will be formed by the traditional method, which is the same as the conventional method. The first ED picture has the same layer structure, which is 280B / c. 'The same layer as in the first B figure is labeled with the same number except for the structure of the first B figure. This manufacturing method increases the etching of the barrier wall of the photoresistive part, but due to the damage of the drain region when etching the gap wall, Affects the process of components. The first D random access memory is taken as an example, and the same layer as in the first C is indicated by a number. In addition to the structure of the first C figure, the etching of the local dielectric layer 250 and the source / drain 26OB / C are taken as an example of the traditional static random access memory, and the same reference numbers are used for the first. In addition to the first D picture, the manufacturing method adds metal silicides 280A1, 280A2, and memory.

Manufacturing method for small size static random access memory. Therefore, there is an urgent need for a device that connects to SRAM). A simpler purpose and summary of the invention: Γςρ 5 In the above background of the invention, 'the existing static random access memory, many shortcomings produced by it', the main purpose of the present invention is to By using gate two = for small size static random access memory two hidden- & (^ M) and another 'manufacturing of the present invention is to provide a static random access memory (

Page 6 466734 V. Description of the invention (3) — = L ί The parasitic resistance of Γ will increase as the element shrinks. In polycrystalline silicon compounds (silicide) is to reduce the gate resistance of the gate. Provide a static random access memory (the current of the common contact plugs of the stone and the golden lips) is shunted to the metal through the contact and then enters the source / drain diffusion region, which can reduce the parasitic resistance of the gate. The clear purpose is to provide a kind of static random access memory to interpolate between the H ΐ free pole and the source / drain diffusion region, so as to obtain a larger process margin of the common contact plug. ). The random access memory (SRAM) contact plug according to the purpose state described above. Furthermore, the gate oxide surface is used to form a static and dielectric layer formed around the gate to cover it, and one of the gates The electrode side wall cover. Next, the sidewall of the nitride stone gap gate has only one gap wall. The ion region is formed between the two gates (lightly doped drain). The present invention provides a method for manufacturing a static element with a small size, which includes: A common layer and polycrystalline dream formation The gate of the memory is accessed on the semiconductor substrate. Next, one of the upper cross-sectional areas of the gate has no oxide layer, no gap wall, and no dielectric layer covering wall is formed on the side wall of the gate. In a heavily doped semiconductor substrate, and a lightly doped drain region is formed at the bottom of the spacer on the side wall of the gate 466734 V. Description of the invention (4) and the semiconductor substrate. Next, a metal silicide It is formed above the gate and source / drain, where the gate sidewall has no gaps and is also covered with a layer of metal silicide. Finally, an inter metal dielectric layer is formed over the surface of the wafer, which should The gate and source / drain diffusion regions are etched with a common contact (share (jc) ntact) plug. 5- The diagram briefly illustrates the operation of each step of the first A picture system and the conventional method. First Figure B is the action of each step of the habit. Figure 1C is the action of each step of the habit. The first picture D is the action of each step of the habit. One E Picture System-Steps, Steps The first F _ series ~ ^ Figures of manufacturing aspects of static random access memory (SRAM), which includes the shape of metal gates and spacers, manufacturing aspects of static random access memory (SRAM), which contains The formation of silicon dioxide and photoresistors is shown in the figure of static random access memory (SRAM) manufacturing, which includes photoresist etching and local gaps. The picture is of static random access memory (SRAM) manufacturing, which includes local dielectric Layer etch and fabrication of static random access memory (SRAM), which includes the formation of metal silicides c Fabrication of static random access memory (SRAM)

Page 8 466734 V. Description of the invention (5) The operation cross-sectional view of each step of the method, which includes the formation of inter-metal dielectrics. The second figure is a schematic diagram of the steps of the method for manufacturing a static random access memory (SRAM) in the embodiment of the present invention, which includes the formation of a metal gate and a dielectric layer. The third diagram is an operation schematic diagram of each step of the method for manufacturing a static random access memory (SRAM) in the embodiment of the present invention, which includes the formation of silicon nitride. The fourth diagram is an operation schematic diagram of each step of the static random access memory (SRAM) manufacturing method in the embodiment of the present invention, which includes a partition wall and a source / drawer. The fifth diagram is each step of the manufacturing method of the present invention. Forming into action. In the embodiment, the static random access memory (SRAM) is a schematic diagram, which includes a metal silicide to take out the metal dielectric layer in the memory (SRAM). The sixth diagram is Example 2 of each step of the method of the present invention. State two machines exist. Action not thinking, it contains

Representative symbols of the main parts: 100 silicon substrate 120 shallow trench isolation 140 gate 160 gate oxide 180 dielectric layer 200 lightly doped; ^ 240 nitride nitride gap Page 9 A 6 6 7 3 4 V. Description of the invention (6) 250 silicon dioxide layer 260A / B source / drain 270 photoresistor 280A1 intermetallic silicide 280A2 gate metal silicide 280B / C source / drain metal silicide 300 inner metal Dielectric layer 10 Silicon substrate 12 Shallow trench isolation region 14 Gate 16 Gate oxide 18 Dielectric layer 20 Lightly doped drain 22 Silicon nitride layer 24 Silicon nitride spacer 26A / B Source / Drain 28A1 Gate metal silicide 28A2 Gate metal silicide 28B / C Source / drain metal silicide 30 Inner metal dielectric layer 5-5 Detailed description of the invention: The sixth figure shows the static random access in the embodiment of the present invention Memory(

Page 10 46673 4 V. Sectional view of invention description (7) ---- SRAM). From the second figure to the manufacturing method of the SRAM—eight M _ f shows the same component system diagram of this static random access. Based on these patterns, the stone on the two sides of the Angstrom will be oxidized to a thickness of about 10 ° to 250 (SRAM). The silicon oxide will be used as static random access memory, s gate 0xide) 16 . Then in a low-pressure chemical vapor phase product with a thickness of about _ to 3_ angstroms, polycrystalline stone 14 in the gate oxide layer 16 soil, diffusion method or ion implantation, high concentration of phosphorus or: Rigidly build polysilicon to reduce the gate resistivity. Immediately next to the gate area of J, the wafer is subjected to a lithography process to define the pattern of the gate body of the static access memory (SRAM). It is transferred to the gate surface = resistance, and then the wafer is sent to the dry etching. Machine (player) to remove the polycrystalline silicon and the gate oxide layer on the wafer without photoresist protection. Then, the gate of the static random access memory (SRAM) is masked for implantation of arsenic (As) or ^ (P) ions, with a concentration of about 1013 to 1004 / cm2, It is used as a lightly doped drain (20), which is called r implantation. Next, the wafer implanted with the lightly doped drain electrode is sent into a thermal diffusion furnace, and the diffusion of the lin atoms is performed at a high temperature of about 900 to 1000 ° C. At the same time, the silicon atomic structure on the surface of the part of the wafer that was destroyed by ion implantation was annealed. Again, deposition by low pressure chemical vapor deposition method Page 11 466734

Layer dielectric layer 18, whose dielectric layer contains silicon and oxygen organic silicide (TE0S)

It is shown that the position of the spacer is defined, and then silicon nitride 22 with a thickness of about 1 500 angstroms is deposited by a low-pressure pore phase method. The metal gate side wall of the dielectric layer 18 has no spacer. There is no silicon nitride deposition. The fourth figure shows that silicon nitride is etched by anisotropic etching to form a spacer wall 24 on the gate sidewall, and one of the gate sidewalls has only one spacer. The dielectric layer is removed, followed by heavy doping of source / drain 26A / B, using phosphorus or arsenic as an ion source, implanting high-concentration and deep-depth ions into the wafer, the concentration is about the concentration About 丨 〇15 / cm2, which is called N + implantation. The fifth figure shows that a layer of titanium metal is deposited by a magnetron DC sputtering method with a thickness of about 200 to 100 angstroms, and then a part of the high temperature is used for deposition. The titanium film reacts with the drain and the silicon on the source and polycrystalline silicon on the gate to form silicon titanate. The titanium remaining after not participating in the reaction or after the reaction is removed by wet etching. At the gate 28A1, 28A2, the source / Drain 28B / C Three metal silicides are left on the surface of the three poles, namely silicon titanate. It is shown that: Plasma-enhanced CVD is used to deposit an inner metal dielectric layer 30, and then the positions of the common contact plugs are defined by a lithography and etching process, and then chemical mechanical polishing is used. (Chemical mechanical polishing)

Page 12 46673 4 V. Description of the invention (9) The planarization of the dielectric layer of the internal gold alloy. In the implementation of this embodiment, a shared contact plug is etched between the gate and the source / drain diffusion region, which can provide a small-sized static random access memory (SRAM) device and a relatively small Simplified manufacturing method_. The hair: of: ί, for the preferred embodiment of the present invention. , Not to limit the work done by God: the scope of India; all other equivalent changes or modifications that do not depart from the scope of the present invention, should be included in the following patent applications

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Claims (1)

466734 VI. Patent application scope L A type of static random access memory (SRAM), at least a. A shallow trench isolation area formed on the semiconductor ^ 1 2 a plurality of gate oxide layers polycrystalline silicon layer, surface, inner, surface ^ ^ ^ Sequence is formed on the semiconductor substrate and the upper cross-sectional area is not oxidized-a dielectric layer is formed on the surrounding layer of the gate; electrical layer: Ξ ΐ is formed on the side of the gate, and the- The dielectric gap wall around the gate is used to isolate the source and the pole and the structure formed by the gate and the gate, and is heavily doped with the row source; HeaVy doped ions are implanted and formed in the two In the conductor substrate between the gates, it is used as a static random access source a / drain; two lightly doped drains (nghtly doped drain) are formed between the bottom of the gap wall of the gate and the semiconductor substrate; A metal silicide is formed above the gate and the source / drain. The side wall of the gate where there is no gap is also covered with a layer of metal silicide for the contact metallization process; and the inner metal dielectric layer ( inter-metal dielectrics), formed in Over said substrate surface, a gate thereof to the source / drain region is etched between a common contact plug (Plug), a barrier metal layer for diffusion. 1 ′ The memory according to item 1 of the Shen Jing patent scope, wherein the gate oxide layer described above includes at least silicon dioxide. 466734 6. Scope of patent application 3. The memory as described in item 1 of the scope of patent application, wherein the above gate layer includes at least a polycrystalline silicon layer. 4. The memory according to item 1 of the scope of the patent application, wherein the above-mentioned dielectric layer contains at least one of the following: Shi Xi element, oxygen element. The description of the gate-The description of its body memory. The space between the 1st wall of the wall and the wall of the fan is beneficial only to the special wall. Please refer to Zhou 5 · Pole 6. The memory according to item 1 of the scope of patent application, wherein the above-mentioned wall contains at least nitride stone. 7. The memory according to item 1 of the scope of patent application, wherein the above-mentioned shallow trench isolation region includes at least polycrystalline silicon and silicon dioxide. 8. The memory according to item 1 of the scope of patent application, wherein the above-mentioned metal petrified compound contains at least titanium metal. 9. The memory according to item 8 of the scope of application for a patent, wherein the above-mentioned metal petroxide includes a metal. 10. The memory according to item 9 of the scope of the patent application, wherein the inter-metal dielectrics in at least one of the foregoing include at least SiO2. Page 15 4 6 673 4 6. Scope of patent application 11. The memory as described in the process item of the patent application No. 1 contact plug for forming multiple interconnects, wherein the common heavy metal interconnect mentioned above (multilevel 1 2. — a kind of static random access memory (SRAM) ), To a shallow trench isolation area, formed in the silicon substrate. Number: Closed layer and polycrystalline stone layer, sequentially formed ... Above the substrate surface / static random access memory (sram) s Metal gate. Section: formed around the intermetallic pole, on the metal free pole;: the area is not covered by a dielectric layer, and the side wall of the metal gate is not covered by two sides of the barrier wall, nor is it covered by a dielectric layer; the barrier wall is formed On the side wall of the metal gate, and the side wall of the closed electrode has a gap wall to isolate the source and the drain, and the gate and the structure of the gate (the structure formed by the gate electrode) is heavily doped with the row source; Heavy doped ion implantation, formed in a silicon substrate between two metal gates, as a source of static random access memory (SRA ... source / immortal; a lightly doped drain) doped drain), formed between the bottom of the gap wall of the gate sidewall and the semiconductor substrate, which has the same ionic charge as the heavily doped ion implantation; a metal silicide formed between the gate and Above the source / drain, where the side wall of the metal idler has no gaps, it is also covered with a layer of metal silicide for contact metallization process. Its low-resistance metal silicide can be silicide metal. 466734 6. Manufactured from a patent application layer (si 1 i cide); and an inter_metal dielectrics (formed above the surface of the wafer) with the gate between the gate and source / light diffusion region # 到'/, Shared contact plug' is used to isolate the metal layer. 13. As for the memory described in item 2 of the patent application scope, the gate oxidation system can be made by dry oxidation method. 14. The memory according to item 2 of the patent application scope, wherein the metal gate electrode can be made by a thermal diffusion method. 15. The memory according to item 2 of the scope of patent application, wherein the above-mentioned dielectric layer is made by a low-pressure chemical vapor deposition method. 16. The memory according to item 2 of the patent application scope, wherein the above-mentioned gate includes at least one of the following: polycrystalline silicon, phosphorus, arsenic, and tungsten silicide. 17. The memory according to item 12 of the scope of the patent application, in which the above-mentioned metal gate sidewalls have no gaps and are also covered with a layer of metal silicide. • ， 18. The memory according to item 17 of the scope of the patent application, in which the above-mentioned gold H 2 material should be a titanium film deposited in an aggressive manner, and its titanium film is as many as the above-mentioned gate i-pole two poles. Crystal cleavage reaction to form the iridium dream, and wet etching to remove the titanium that is not involved in the reaction or the reaction. Page 17