TW464986B - Method of manufacturing a semiconductor device - Google Patents

Abstract

A method of manufacturing semiconductor device capable of reducing the number of processing steps, comprises: forming a gate electrode on a semiconductor substrate; follow by covering the gate electrode with a first insulator layer; and forming a second insulator layer on the first insulator layer. Thereafter, simultaneously forming a first contact opening connected to the surface of the semiconductor substrate and a second contact opening connected to the upper surface of the gate electrode, in which the second contact hole has a diameter larger than that of the first contact hole. Subsequently, bury a conductive layer in the first contact hole and use this conductive layer to form a sidewall on the lateral walls of the second contact hole. Then, remove first insulator layer from the bottom of the second contact hole.

Description

464986 4〇22pir.doc / 〇〇8 Λ7 R? 5. Description of the invention (() The present invention relates to a method for manufacturing a -1 semiconductor device, and in particular to a method of using self-aligned contact windows. -contact) technology to manufacture semiconductor components, such as dynamic random access memory (DRAM), metal-oxide-semiconductor large-scale integrated circuit (MOS-type LSI), or similar devices. Manufacturing of contact windows for semiconductor components In the method, the self-aligning contact window technology is a method that can be used to reduce the alignment margin of the contact hole openings on the gate in the silicon substrate. ， -Η 消 于 合 竹 ^ Yinji (read the precautions before reading this page) This edge is provided to prevent the short circuit between the contact window opening and the gate. Figure 1 is a representative The self-aligned contact window technology. FIG. 1 is a schematic cross-sectional view of a part of a semiconductor device having a contact window opening formed by the self-aligned contact window technology. In a semiconductor substrate 10 (such as sand Base) A gate electrode 11 14 having a thin metal layer on a top surface is formed on the top surface. The top and side wall portions of the gate electrodes 12, 14 are covered with an f-silicon nitride layer 16, 18 as an insulating layer. An oxide layer 20¼ is formed on the gates 12, 14 as an insulating layer. Upper wirings 22, 24 'are formed on the oxide sand layer 20, and are connected to the gate 12 by polycrystalline silicon plugs 26A, 28A. The surface of the semiconductor substrate 1JQ is connected, and the polycrystalline sand plugs 26A, MA are embedded in the contact window openings 20, 28. The contact window openings 26, 28 are formed in the silicon oxide layer 20 and reach the semiconductor substrate 1. The numbers and 32 refer to the diffusion layer, while 34 refers to the field oxide layer. Because the contact window openings 26 and 28 are formed using self-aligned contact window technology, the upper conductor 24 and the gate electrode iTjf will short circuit. In other words In other words, the etching is performed under a highly selective etching condition, and the etching rates of the silicon nitride layer 16 and the silicon oxide layer 20 are quite different, that is, the contact window openings are formed. > A4 size (210X297mm) 46 4 986 4022pif'.d〇c / 0 0 8 A7 B7 V. Description of the invention (>) 26, 28 Insulation of the shouldered sand layer 2 (¾ etch rate, the etch rate of the silicon nitride layer I6 of the cover electrode i2 is much larger. Completed under this etching condition Etching 'even if the alignment edges of the contact window openings 26, 28 are green against the gates 12 and 4 first read: back side ..-of-note again fill in this e is very small, then the upper wires 22, 24 and the gate below it An electrical short at the pole 12 can be prevented. In spite of this, in the current large-scale integrated circuit, in addition to the contact window openings that connect the upper layer wires and the sand substrate, there are also upper layer wires and squares ^; the gates below them all contact the window openings. If the contact window opening is formed using the above-mentioned conventional self-aligned contact window technology, several contact window openings can be simultaneously formed in the same insulating layer after one lithography and etching. However, in the example shown in Figure 1, on the one hand, in order to form a contact window opening extending to the silicon substrate 10 by the conventional self-aligned contact window technology, the silicon wafer will not be etched. Selective etching is necessary. On the other hand, in order to form a contact window opening at its n pole, the gate electrode is covered (the gasified sand I must also be etched away at the same time. Next, the lithography and etching steps of the contact window openings applied to the silicon substrate, and the lithography and etching steps of forming the contact window openings extending to the gates below it must be performed separately. Therefore, This leads to the problem that the number of lithography steps must be increased. *? 浐 部 浐 save,.; | 1.; /) 贽 ^ '竹 ^ 印 来 Therefore, the object of the present invention is to provide a semiconductor device The manufacturing method of this method can form different types of contact window openings to extend to different types of material layers below it, thereby reducing the number of steps in the manufacturing process of semiconductor devices. In order to achieve the above object, a first object of the present invention is to provide a method for manufacturing a semiconductor device, which includes the following steps: firstly, a semiconductor paper standard is applied to the China Solid State Standard (CNS) A4 specification (2).厘} 4 浐 部 中 荣 h τ, ίίίϊέ :; 合:;: heart imprint 6 4 98 6 4 022pii'.d〇c / 00ii V. Description of the invention (々) A pole is formed on the substrate '+ -A first insulating layer covers the gate electrode, and a second insulating layer is formed on the first insulating layer. The second step is to form a first contact window opening 'in the second insulating layer for contacting the surface of the semiconductor substrate. And a second contact window opening is formed to connect with the upper surface of the gate electrode, and the diameter of the second contact window opening is larger than the diameter of the first contact window opening. The third step is the first contact window opening. A conductive layer is buried in the conductive layer, and a sidewall is formed on the side wall of the second contact window opening with the conductive layer. The fourth step is to remove the first insulating layer from the bottom of the second contact window opening. The fifth step is Form upper layer wires on the second insulation layer The upper conductive wire is connected to the surface of the semiconductor substrate and the upper surface of the gate electrode through the conductive layer in the first contact window opening and the second contact window opening. In the above-mentioned method for manufacturing a semiconductor device, In the second insulating layer constituting the interlayer insulator layer, a first contact window opening for connecting to the surface of the semiconductor substrate is simultaneously formed, and a second contact window opening for connecting to the surface of the gate is simultaneously formed. Where the diameter of the second contact window opening is larger than the diameter of the first contact window opening. A conductive layer is buried in the first contact window opening, and a side wall is formed on the side wall of the second contact window opening by the conductive layer. Removing the first insulating layer covering the gate electrode from the bottom of the second contact window opening. Forming an upper conductor on the second insulating layer, the upper conductor passing through the conductive layer in the first contact window opening or the second contact window opening, It is connected to the surface of the semiconductor substrate or to the upper surface of the gate. A second object of the present invention is to provide a method for manufacturing a semiconductor element. The method includes: a first step of forming a gate electrode on a semiconductor substrate, covering the gate electrode with a first insulating layer, and forming a 6 on the first insulating layer Read this page again}

This paper is in accordance with China National Standards (CNS) A4 specifications (2 丨 0X297 male) 4 6 4 9 8 6 A7 4 Ο 2 2 ρ ΐ fd 〇c / 〇〇 8 π 7 V. Description of the invention (G) Two insulating layers. The second step is to place a mask pattern 'with a first contact window opening and a second contact window opening' to form a first contact window opening to connect to the surface of the semiconductor substrate. 'This first contact window opening The diameter of the second contact window is smaller than the diameter of the second contact window opening, and a second contact window opening is formed to be connected to the upper surface of the gate electrode, and the first contact window opening and the second contact are simultaneously formed by performing highly selective etching. For window openings, the worm-etching rate of the second insulating layer is greater than the axial etch rates of the first insulating layer and the semiconductor substrate. The third step is to form a conductive layer on the second insulating layer so that its thickness completely fills the first contact window opening and partly fills the second contact window opening. The fourth step is to etch back the conductive layer 'to form a plug of the conductive layer in the first contact window opening, and form a side wall on the side wall of the second contact window opening. The fifth step is to perform low-selective etching to remove the first insulating layer at the bottom of the opening of the second contact window. The etching rate of the first insulating layer is greater than the axial etch rate of the second insulating layer. The sixth step is to form an upper layer conductor on the second insulating layer 'this upper layer conductor is connected to the surface of the semiconductor substrate via the conductive layer in the first and second contact window openings' and is connected to the upper surface of the gate electrode The surfaces are connected. In the method of manufacturing a semiconductor device having the above structure, the radius of the second contact window opening mask pattern formed to be connected to the upper surface of the gate electrode is larger than the radius of the first contact window opening mask pattern. The first contact window opening is used to connect with the surface of the semiconductor substrate. The first contact window opening and the second contact window opening are simultaneously formed by performing highly selective etching, wherein the etching rate of the second insulating layer (which forms the inner insulating layer) is higher than that of the semiconductor substrate and the first insulating layer (which Covered with gate), the etching rate is large. After that, a conductive layer 1 is formed on the second insulating layer so that its thickness is completed. The paper scale is suitable for Chuanzhong Family Standard Rate (CNS). A4 is now (2 丨 0X297).

(Count 1 Notes for reading the back song, then fill in Ben Lo 'J 464986 A7 40 22 pi Γ iioc / ΟΟίΐ B7 V. Description of the invention (t) Full of the first contact window opening' and the second contact window opening is not completely By the etching back of the conductive layer, a plug of the conductive layer is formed in the opening of the first contact window, and a side wall is formed on the side wall of the opening of the second contact window. Then, a low selectivity is performed. Etching to remove the first insulating layer at the bottom of the opening of the second contact window, wherein the etching rate of the first insulating layer is higher than the etching rate of the second insulating layer. Then, an upper conductor is formed on the second insulating layer, and the upper conductor passes through The conductive layer in the first contact window opening or the second contact window opening is connected to the surface of the semiconductor substrate or the upper surface of the gate electrode. A third object of the present invention is to provide a method for manufacturing a semiconductor element. The method includes the following steps: firstly forming a diffusion layer near the surface of the semiconductor substrate to become a source and a drain region; the second step is forming a first gate and a first electrode on the semiconductor substrate; The second gate. The third step is to cover a first insulating layer on the first gate and the second gate. The fourth step is to form a second insulating layer on the semiconductor substrate and the first insulating layer. Fifth The step is to simultaneously form a first contact window opening and a second contact window opening in the second insulating layer, wherein the first contact window opening exposes a source or drain region and the second contact window opening exposes a second The first insulating layer on the gate electrode, and the diameter of the second contact window opening is larger than the diameter of the first contact window opening. The sixth step is to embed a conductive substance in the first contact window opening, and use the conductive substance in the second A sidewall portion is formed at the contact window opening. The seventh step is to remove the first insulating layer from the bottom of the second contact window opening. The eighth step is to form a conductive layer on the second insulating layer to fill the second insulating layer. Contact window opening P ^ The fourth object of the present invention is to provide a semiconductor device manufacturing 8 (诮 Read the precautions on the back before filling in this bookΗ)

、 1T This paper size is suitable for Sichuan Chuanzhong Standard (CNS) Λ4 specification (210X297mm) 6 4 9 8 6 4 022pil'.d〇c / 〇〇S 8 7 _______________ B7 .---. M ___ Five ' SUMMARY OF THE INVENTION The method includes: a first step of forming a diffusion layer near a surface of a semiconductor substrate to become a source and a drain region. The second step is to form a field insulating layer on the semiconductor substrate. The third step is to form a first gate on the semiconductor substrate, and form a second gate on the field insulation layer. The fourth step is to cover the first gate electrode and the second gate electrode with a first insulating layer. The fifth step is to form a second insulating layer on the semiconductor substrate and the first insulating layer. The sixth step is to perform selective etching, and the etching rate of the second insulating layer is greater than the etching rates of the first insulating layer and the semiconductor substrate, and a second contact window opening mask is formed by using a mask pattern. The radius of the pattern is 'larger than the radius of the first contact window opening mask pattern formed', and a first contact window opening and a second contact window opening are simultaneously formed in the second insulating layer, wherein the first contact window opening is exposed The second contact window opening exposes the first insulation layer on the second gate electrode, and the diameter of the first contact window opening is larger than the diameter of the first contact window opening. The seventh step is to embed a conductive substance in the opening of the first contact window, and to form a side wall portion at the opening of the second contact window with the conductive substance. The eighth step is performed by selective etching, in which the etching rate of the first insulating layer is greater than the etching rate of the second insulating layer, and the first insulating layer is removed from the bottom of the opening of the second contact window. The ninth step is to form a conductive layer on the second insulating layer to fill the opening of the first-contact window. According to the first to fourth objects of the present invention, different types of contact window openings can be formed at the same time, and extend to the lower material layers of different types. Therefore, when manufacturing a semiconductor device having contact window openings of different forms and extending to the underlying material layer of different forms, the lithography process can be reduced once, thereby reducing the number of manufacturing steps. 9 This paper has been used for 1 month 丨 China Gujia Standard (CNS) A4 ^ (210X297 Gong Chu 1 " (铽 Read the notes on the back 1 & first 4 features) This page

* 1T / 价 A / 1 9 8 6 4022pil'.doc / 00H Λ __ ___ B7 V. Description of the invention (q) (4 Read the notes on the back first 4 Write this page) The fifth object of the present invention is to provide A method for manufacturing a semiconductor device of a first purpose or a second purpose, such a semiconductor device is a dynamic random access 5_β tl, a body (DRA M) «Among them, the first contact window opening is a bit contact window opening (bit contact hole), which is used to connect the silicon substrate of the semiconductor and the bit line, and the bit line is the upper wire of the memory cell area of the dynamic random access memory. The second contact window opening is used to connect the gate electrode and a bit line, and the bit line is an upper layer wire surrounding the peripheral circuit area of the memory cell area. The conductive layer formed in the first contact window opening and the conductive layer formed at the sidewall of the second contact window opening are polycrystalline silicon. The method for manufacturing a semiconductor substrate having the above structure has different forms of contact window openings, and extends to different layers of underlying material layers, that is, a bit contact window opening and another contact window opening can be formed at the same time, where the bit contacts The window opening is used to connect the semiconductor silicon substrate with a bit line, and this bit line is the upper wire of the memory cell area of the dynamic random access memory, and the other contact window opening is used to connect the gate and the bit. Element line, this bit line is the upper layer wire surrounding the peripheral circuit area of the memory cell area. Therefore, according to the fifth object of the present invention, when manufacturing a dynamic random access memory, the lithography process can be reduced once, and thus the number of manufacturing steps can be reduced. A sixth object of the present invention is to provide a method for manufacturing a semiconductor device of the first or second purpose, which semiconductor device is a large-size integrated circuit of a metal-oxide semiconductor type. The first contact window opening is a silicon substrate that can be used to connect the semiconductor to the first layer of metal wires. The first layer of metal wires is an upper wire of a metal oxide semiconductor large integrated circuit. The second contact window opening is a metal wire used to connect the gate electrode to the first layer. The first layer of this paper is sized to the Chinese National Standard (CNS) A4 size (210X297 mm> 4 6 4 9 8 6 402 2 pit'.doc / 0 08 A7 V. The metal wire of the description of the invention (?) Is the upper wire of a metal oxide semiconductor large integrated circuit. The conductive layer formed in the first contact window Π and the second The conductive layer formed at the side wall of the contact window opening is tungsten metal. The method for manufacturing a semiconductor substrate having the above structure has different types of contact window openings and extends to different layers of underlying material layers, that is, the first layer can be formed simultaneously Type contact window opening and second type contact window opening, wherein the first type contact window opening is used to connect the semiconductor silicon substrate and the first layer of metal wires, and the first layer of metal wires is a large-sized body of metal oxide semiconductor type The upper wire of the circuit, and the second type of contact window opening is a metal wire used to connect the alarm and the first layer, which is the upper wire of the large-scale integrated circuit of the metal-oxide semiconductor type. Therefore, According to the sixth object of the present invention, 1 can reduce the number of lithographic processes in manufacturing a metal-oxide-semiconductor-type large-scale integrated circuit, thereby reducing the number of manufacturing steps. In order to achieve the above and other objects, features, and The advantages are more obvious and easy to understand. The following is a detailed description of the two preferred embodiments and the accompanying drawings: Simple illustration of the drawings: Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs {Please read the back Please fill in this page again for attention.) Figure i is a cross-sectional structural diagram of a semiconductor device, which is used to explain the manufacturing method of a conventional semiconductor device; Figures 2A to 2j are drawings showing the first A preferred embodiment is a schematic sectional view of a manufacturing process of a semiconductor element; and FIGS. 3A to 31 are schematic sectional views showing a manufacturing process of a semiconductor element according to a second preferred embodiment of the present invention. . This paper size applies to China National Standard (CNS) A4 (2 丨 0 X 297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 6 4 9 8 6 4 Ο 2 2 p 1 f tl oc / 〇 0 SA 7 __B7 Five 'invention description (?) Symbol description of the drawing: 10 semiconductor substrate 12, 14, 60, 98 gate 16, 18, 50, 52, 94 silicon nitride layer 20, 56, 100 silicon oxide layer 22, 24 Conductor 16 '28 Contact window opening 26A '28A Polycrystalline sand plug 30, 32 Diffusion layer 34 Field layer 40, 80 Silicon substrate 42, 82 Isolation area 44' 88 Gate oxide layer 46 '66' 70 '90 Polycrystalline silicon layers 48, 72, 92 Tungsten silicide layers 54 Diffusion regions 58, 102 Photoresist patterns 61 MOS transistors 62, 64, 104, 106 Contact window openings 68 Polycrystalline silicon sidewalls 84 Diffusion layer (source) 86 Diffusion layer (drain) 96 Gold Oxygen Semiconducting Crystals 108, 122 Titanium Metal Layer 110 '120 Tungsten Metal Layer (Please read the precautions on the back before filling out this page) The size of the paper is applicable to China National Standards (CNS > Μ Specifications (2 丨 OX297 Public Finance) Ministry of Economic Affairs, Central Standard Labor and Consumer Cooperative, India Policy 464986 Ί〇22ρΠ 'doc / OΟΧ Α7 Β7--— — ______ " _Look — V. Description of the invention (β) 1 12 Side wall 124 Inscription copper alloy layer 126 Titanium nitride chewing embodiment. In the following, the embodiment of the present invention will be described with reference to the accompanying drawings FIG. 2A to FIG. 2 are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to a first preferred embodiment of the present invention. In the first embodiment, the semiconductor device is a hidden operation. Memory. In the memory cell area of the dynamic random access memory, a bit contact window opening connecting the silicon substrate and the bit line is provided. In the peripheral circuit area surrounding the memory cell area, such as a sense amp portion , Provide other contact windows, head and mouth, to connect imitation; f, line and smell pole. The dynamic random access memory with higher accumulation degree makes it impossible to ensure that the bit contact window of the memory cell area is opened and adjacent Aligned edges between the gates. In order to form this contact window opening α, self-aligned contact window technology is needed. However, as far as the traditional self-aligned contact window technology is concerned, it is necessary to form two different types at the same time. Form of Yu || , The delay does not serve to avoid the wind JF layer material layer is not possible. This issue can be overcome by the present invention.

Referring to FIG. 2A, first, an isolation region 42 is formed in a silicon substrate 40 (T · conductor substrate) by a LOCOS process. After that, an anodic oxide layer (.44 J with a thickness of about 4 nm) and a polycrystalline silicon layer 40 (with a thickness of about 150 nm) (with a thickness of about 100 nm) were sequentially formed by a low-pressure chemical vapor deposition method. (LP-CVD) depletion layer 50 (about 100 nm in thickness). _ 13 This paper size is in accordance with Chinese National Standard (CNS) 8-4 specification (210X297 mm) (Please read the precautions on the back before filling this page)-,? Τ pf Γ cl ο c / 0 Α7 Β7 V. Invention Explanation ((丨) Next, the polycrystalline silicon layer 46 and the tungsten silicide layer 48 are formed by a lithography and etching process *. The gate electrode 601 [see FIG. 2B]. After that, a silicon nitride layer 52 (thickness of about 100 to 200 nm) is formed with J; therefore, it is a layer. (See FIG. 2C). The silicon nitride is made ππ lighter than anisotropic etching, and the gate 60 is covered by the silicon nitride layer 52 to form a sidewall at the gate 60. Furthermore, by shaping and ion implantation, a diffusion region 54 (which will be 'formed as a source or a drain) and a MOS transistor 61 are formed in the memory cell region. After that, the shape of the ytterbium oxide layer 56 (thickness of about 400 ηπ〇 as the inner dielectric layer (refer to Figure 2D). After that, a photoresist pattern is formed by lithography. The resist pattern 58 is used to form one form of contact window opening (first contact window opening), which is used to connect the memory cell area with the silicon substrate; and another form of contact window opening (second contact window opening), In this case, the reading area is placed in the Tai_Tai area and 阃 殛 il JI. At this time, a main pattern is prepared in advance so that the diameter D1 of the opening of the contact window connected to the gate in the read amplification area is larger than that in the recording area. The diameter D2 of the contact window opening connected to the silicon substrate 40. For example, the diameter of the contact window opening extending to the gate is set to about 0.3 μm, and the diameter of the contact window opening extending to the silicon substrate 40 is set to about 0.2. The photoresist pattern 58 is used as a mask to perform highly selective etching, so that the etching rate of the silicon oxide layer 5_0 f second vine is greater than that of the silicon substrate 40 and covered with the alarm electrode 60 0 sand ^ 5 2 (First insulating layer) the speed of this highly selective etching, such as- Controlled etching machine-(_ magnetron-etcher) is performed under the following conditions: pressure: 4〇ηιοοτ, gas flow rate: Ar / CO / C4F8 = 400/300/1 6 (cc / min) 'power: 丨 300W, Base temperature 20 ° C, gas back pressure (back pressure): 14 (Please read the precautions on the back before filling out this page)% The Central Standards Bureau of the Ministry of Economic Affairs, Pei Yigong, Consumer Cooperative Seals The paper dimensions are applicable to Chinese national standards ( CNS) A4 size (210 X 297 mm) Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Industrial and Consumer Cooperatives 6 4 9 8 6 4 Ο 2 2 pi ί. Il c / f) () S A7 __B7 V. Description of the invention ( < >) Center / Edge = 3/45 Ton ~ So.- Come, the contact window opening 62 and the contact window opening 64 can be formed at the same time, wherein the contact window opening 62 exposes the surface of the silicon substrate 40 of the memory cell area, and The contact window opening 64 exposes the upper surface of the silicon nitride layer 52 on the gate 60 in the read amplification region. After that, the photoresist pattern 58 is removed (refer to FIG. 2F). Then, a low pressure chemical vapor deposition is performed. Method to form a polycrystalline silicon Jf 66 containing a high concentration of phosphorus atoms on the silicon oxide layer 56, in which The contact window openings 62, 64 have been formed in the silicon oxide layer 56. The thickness of the polycrystalline silicon layer 66 is set to about 100 nm at least so that the contact window openings 62 formed in the memory cell area are completely filled, and The contact window opening 64 is not completely filled (please refer to FIG. 2G). The polycrystalline silicon layer 66 formed on the silicon oxide layer 56 is etched back by reactive ion etching (RIE). The portion of the contact opening 62 has been completely filled with a polycrystalline silicon plug. Polysilicon sidewalls 6S, 68 are formed on the sidewalls of the portion where the contact window opening 64 has been formed in the read amplification region (see FIG. 2H). Then, a reactive selective etching method (eRIE) is used to perform low-selective etching, in which the etching rate of the silicon nitride layer 52 is determined by the etching rate of the silicon oxide layer 56 to remove the contact in the read amplification region. A silicon nitride layer 52 at the bottom of the window opening 64 (see FIG. 21). Low selective etching is performed, for example, by an electron cyclotron resonance; (ECF ^ contact engraving age is performed under the following conditions: pressure: 10 mTon, gas flow rate: He / CH2F2 = 100 / 丨5 (cc / min), microwave power: 300W, local frequency power: 100W, substrate temperature 30 ° C, helium back pressure: 8 Ton-. Then, chemical vapor deposition or sputtering was performed on the oxygen substrate. Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the notes on the back before filling in this tile) Order printed by the Central Standards Bureau of the Ministry of Economic Affairs and printed by the Bayer Consumer Cooperative 4 6 4 986 4〇22ρΜ ΐΙοί / ΠΟΚ Α7 ____ Β7 V. Description of the Invention (()) A polycrystalline silicon layer 70 (100 μηΊ) is formed on the siliconized layer 56 and a tungsten silicide layer 72 (100 μπ0) which will form a bit line. Thereafter, a lithographic process is performed on the polycrystalline silicon. A photoresist pattern (not shown) is formed on the layer 70 and the tungsten silicide layer 72. Using the photoresist pattern as a mask, unnecessary portions of the polycrystalline silicon layer 70 and the tungsten silicide layer 72 are etched to make bits Line, and thus complete the necessary steps (please (According to the figure) "According to the method for manufacturing a semiconductor device related to the first embodiment of the present invention, a bit contact window opening and a contact window opening can be formed simultaneously, wherein the bit contact window opening is connected to the dynamic random access memory. The silicon substrate (semiconductor substrate) and bit lines (upper conductors) in the memory cell area, while the contact window α is the bit line that connects the gate and the surrounding circuit area around the memory cell area (the upper conductors are therefore 1 in the manufacturing When the Dragon 1 machine accesses the memory, one lithography step can be reduced, so that the number of process steps can be reduced. Figures 3A to 3 are diagrams showing a semiconductor device according to a second preferred embodiment of the present invention. A schematic cross-sectional view of the manufacturing process. In the second embodiment, the semiconductor device is a large-sized integrated circuit of the metal-oxide semiconductor type. The large-sized integrated circuit of the metal-oxide semiconductor type has several contact windows, and some of the contact windows are connected to a silicon substrate. Some of the contact windows are connected to the first layer of metal wires and the gate electrode and the first layer of metal wires. The large-scale integrated circuit of the metal-oxide semiconductor type with a high accumulation degree cannot be guaranteed. The contact window opening connecting the bottom of the silicon wafer and the first layer of metal lines, and the aligned edge between the adjacent gates. In order to form this contact window opening, self-aligned contact window technology needs to be introduced. However, traditionally, In terms of self-aligning contact window technology, it is impossible to form two different types of contact window openings at the same time, and it is not possible to extend to different F-layer material layers. (Fill in this page again), π This paper size is applicable to China National Samples (CNS) Α4 (210X297 mm) 4 6 ^ -986 4ii22pi j · due / 00 8 A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Equipment V. Description of Invention (⑽) It shall be overcome. Please refer to 3Λ_ to form the isolation region (field insulation layer) S2, the diffusion layer (source electrode) on the silicon substrate 80 (semiconductor substrate) in the same steps (FIGS. 2A to 2D) in the first embodiment. ) 84, diffusion layer (drain) 86 and metal-oxide semi-conductive crystal%. The gold-oxygen semi-conductive crystal 96 has a gate electrode 'consisting of a polycrystalline sand layer 90 (having a thickness of about 50 nm) and a tungsten silicide layer 92 (having a thickness of about 100 nm) and is formed on the gate oxide layer 88. The gate electrode 96 of the gold-oxygen semi-conductive crystal 96 is covered by a silicon nitride layer 94 (having a thickness of about 100 nm) as an insulating layer. The gate 98 on the isolation region 82 is formed of a polycrystalline silicon layer 90 and a tungsten silicide layer 92, and is covered by a silicon nitride layer 94. A silicon oxide layer 100 is formed as an inner insulating layer on the silicon substrate 80 on which the metal-oxide semi-conductive crystal 96 and the gate 98 have been formed, and has a thickness of about 400 nm (refer to FIG. 3A). Thereafter, a photoresist pattern 102 is formed by lithography. The photoresist pattern 102 is used to form a contact window opening (first contact window opening), which is used to connect the silicon substrate 80 and the first layer of metal lines, and this first layer of metal lines is made of sand. The upper conductor of the metal oxide semiconductor type integrated circuit); and another contact window opening (second contact window opening) for connecting the gate electrode and the first layer of metal wire. When ΓΓ, a photoresist pattern is preliminarily prepared so that the diameter D3 of the contact window opening connected to the gate 98 is larger than the diameter D4 of the contact window opening connected to the silicon substrate 80. For example, the diameter of the contact window opening used to connect to the gate electrode 98 is set to about 0.4 Pm 'and the diameter of the contact window opening used to connect to the silicon substrate 80 is set to about 0.3 μm (see section (Picture 3B) · Secondly, the light-attached pattern 102 is used as a mask to carry out selective worming. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------- -Discard-. * (Please read the note on the back before filling in this page), τ Printed by the Shellfish Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 4. 6 a 9 8 6 4022pi l'.doc / 008 A7 _B7 V. Explanation of the invention (i) The etching rate of the oxide layer 100 (the second insulating layer) is greater than that of the sand substrate 80 and the silicon nitride layer 94 (the first insulating layer) covering the gate 98. 'In this way, the contact window opening U 104 and the contact window opening 106 can be formed at the same time, wherein the contact window opening 104 exposes the upper surface of the silicon substrate 80 forming the region of the metal-oxide semiconductor 96, and the contact window opening 106 is exposed. A nitrided sand layer 94 is formed in a region where the gate electrode 98 is formed and located on the intermediate electrode 98. After that, the photoresist pattern 102 is removed (refer to FIG. 3C). Then, a titanium metal layer 108 (a titanium nitride layer or a mixed material layer composed of titanium metal and titanium nitride) is formed by a sputtering method or a chemical vapor deposition method, and has a thickness of about 50 nm. Next, a tungsten metal layer 110 is formed by a low-pressure chemical vapor deposition method. At this time, the thickness of the tungsten metal layer 110 is set to 値, for example, about 100 ηη, so that at least the contact window opening 104 is completely filled, and the contact window opening 104 is formed in a region where the MOS transistor 96 is located. Moreover, the contact window opening 106 is not completely filled at most, and the contact window opening 106 is formed in the area where the gate electrode 98 is located (refer to FIG. 3D). Second, the reactive ion etching method is used to form the contact window opening 106. The tungsten metal layer I 1 0 and the hafnium metal layer 108 on the silicon oxide layer 100 are etched back (J. In this way, the contact window opening 104 used to connect to the silicon substrate 80 is plugged by tungsten. Fully filled 'and on the side wall of the contact window opening | 〇6 for connecting the gate 98, a side wall 1 Π is formed (refer to FIG. 3E). A reactive ion fusion method is performed in which the nitrided sand layer 94 is melted. The etching rate is greater than the etching rate of the silicon oxide layer 100, so that the contact window connected to the gate 98 is opened. The silicon nitride layer 94 at the bottom of the 106 is removed (see FIG. 3F). Method for forming tungsten gold on silicon oxide layer 100 National Standard (CNS) A4 Specification (210'X297 mm) — -II― ― · IIII 1 — ^ :. 11 n H ^ II! ~ -II Ϊ ~ I-Please read the precautions on the back before completing this Page} A7 B7 464986 V. Description of the invention The thickness of the metal layer 120 is about 100 nm, so that the contact window opening 106 on the gate electrode is completely filled (please refer to Figure 3 (3)). Then, the reaction is performed. Ion etching method is used to etch tungsten metal layer] 20. In this way, the contact window opening for connecting the silicon substrate 80 and the high opening for contacting the contact 9 8 Z and the contact opening are both plugged by cranes. Filled (| see Figure 3H). Secondly, a titanium metal layer I22 (thickness of about 50 nm) that will become the first metal wire is formed on the oxidized sand layer by chemical vapor deposition or sputtering. 1, Mingsha copper alloy layer 1 24 (thickness of about 500 nm) and nitride layer 126 (thickness of about 100 nm). Thereafter, a lithography process was used to define the titanium metal layer 122 and the aluminum-silicon-copper alloy. Layer P4 and titanium nitride layer 126 (not shown). Using the photoresist pattern as a mask, the titanium metal layer 122 and aluminum are etched. Unwanted parts of the copper alloy layer 124 and the titanium nitride layer 丨 26 to form the first-layer metal wire 1 and thus complete the necessary processes (see FIG. 31). According to the semiconductor related to the second embodiment of the present invention The device manufacturing method can form a first contact window opening and a second contact window opening at the same time, wherein the first contact window opening is a silicon substrate (semiconductor substrate) and a first layer of metal wire (metal oxide semiconductor large-scale integrated circuit). L·layer wire), and the second contact window opens the door to connect the gate electrode with the first layer of metal wire (the upper wire of the large-scale integrated circuit of the metal oxide semiconductor type). Therefore, in the production of a metal oxide semiconductor type λ: corpuscle circuit, the number of lithography steps can be reduced, so that the number of process steps can be reduced. According to the first and second objects of the present invention, different types of contact window openings are simultaneously formed, and extend to the lower material layers of different types. (Please read the note_item on the back before filling out this page). Participate · Order the printed paper size of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. The paper size is applicable to China National Standard (CNS) A4 (210 乂 29: / mm) A7 B7

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MJ22pir.tl tic / OOK V. Description of the Invention (η) Therefore, when manufacturing a semiconductor device having different types of contact window openings and extending to different layers of underlying material layers, the lithography process can be reduced once, thus making the manufacturing steps The number is reduced. According to the third aspect of the present invention, two different types of contact window openings 'can be formed at the same time and extend to different layers of underlying material layers, that is, the first contact window opening' is a memory connected to the dynamic random access memory The silicon substrate (semiconductor substrate) and bit lines in the cell area (upper wires in the memory cell area of the dynamic random access memory), and the second contact window opening connects the gate and the bit line (around the memory The upper wire of the peripheral circuit area of the cell area). Therefore, when manufacturing the dynamic random access memory, one lithography step can be reduced, so that the number of process steps can be reduced. According to the fourth g of the present invention, different forms of contact window openings can be formed at the same time and extend to different layers of lower material layers, that is, the first contact window openings, which connect the silicon substrate (semiconductor substrate) to the first layer. Metal wire (upper conductor of metal oxide semiconductor large integrated circuit), and the second contact window opening is to connect the gate electrode with the first layer of metal wire (upper conductor of metal oxide semiconductor large integrated circuit). Therefore, when manufacturing a metal oxide semiconductor type large-scale integrated circuit, π 丨 reduces one lithography step, so that the number of process steps can be reduced. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. 'Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. 2 0 (Please read the precautions on the back before filling out this page)% Order Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs This paper recognizes the wealth and the family (CNS (2 献 297 公 # >

Claims (1)

ABCD 〇4 9 8 6 4 02 2 ni 1 ′ 〇c / () 〇Η 6. Scope of patent application 1. A method for manufacturing a semiconductor device includes the following steps: forming a gate electrode on a semiconductor substrate, An insulating layer covers the gate electrode, and a second insulating layer is formed on the first insulating layer; a first contact window opening is formed in the second insulating layer, and is used to connect with a surface of the semiconductor substrate, and Forming a second contact window opening for connecting to an upper surface of the gate electrode, wherein the diameter of the second contact window opening is larger than that of the first contact window [a conductive layer is buried in the first contact window opening : Forming a side wall on the side of the second contact window opening with the conductive / electrical Jg; removing the first insulating layer from the bottom of the second contact window opening; and forming on the second insulating layer A plurality of upper-layer wires, which are connected to the surface of the semiconductor substrate and the upper surface of the gate electrode through the conductive layer in the first contact window opening and the second contact window opening; connection. 2. The method for manufacturing a semiconductor device according to item [Scope of the patent application], wherein the first insulating layer includes a silicon nitride layer, and the second insulating layer includes an oxide sand layer. 3. The method for manufacturing a semiconductor device according to item 1 of the scope of the patent application, wherein the first insulating layer exists only on the upper surface portion and the side surface portion of the gate electrode. 4. The method of manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the first contact window opening and the second contact window opening are formed with the stomach. 5. A method for manufacturing a semiconductor device, including the following steps: forming a gate electrode on a semiconductor substrate, and covering the paper size with a first-insulating layer; using the Chinese National Standard (CNS) A4 specification (210X297 mm) ( (Please read the notes on the back before filling out this page),-· Order the printed oxygen of the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs β d. 9 8 6 4 0 22 ptf, cit5c / 008 A8 B8 C8 D8 Staff of the Central Standards Bureau of the Ministry of Economic Affairs Consumer Cooperatives 6. The patent application scope of the gate electrode, and a second insulating layer is formed on the first insulating layer; a mask pattern having a first contact window opening and a second contact window opening is arranged to form the A first contact window opening for connecting to a surface of the semiconductor substrate 'the diameter of the first contact window opening is smaller than the diameter of the second contact window opening' and forming the second contact window opening for contacting the gate electrode An upper surface is connected to the first contact window opening and the second contact window opening by performing highly selective etching, wherein the etching rate of the second insulating layer is higher than that of the first insulating layer and The semiconductor substrate has a large etching rate; a conductive layer is formed on the second insulating layer, so that the thickness of the conductive layer completely fills the first contact window opening, and partially fills the second contact window opening; Layer to etch back to form a plug of the conductive layer in the first contact window opening, and to form a side wall on a side wall of the second contact window opening; perform low selective etching to remove the first The first insulation layer at the bottom of the two contact window openings, wherein the etch rate of the-•• insulation layer is greater than the etch rate of the second insulation layer; and a plurality of upper-layer wires are formed on the second insulation layer, these The upper-layer wire is connected to the surface of the semiconductor substrate through the conductive layer ′ in the first and second contact window openings, and is connected to the upper surface of the gate electrode. 6. The method for manufacturing a semiconductor device according to item 5 of the scope of the patent application, wherein the ... insulating layer includes a silicon nitride layer, and the second insulating layer includes a silicon oxide layer. This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page) Ordered by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, SA 9 8 6 A8 B8 4022 | > i Γ Joc / OOX C8 D8 6. Application for patent scope 7. The method for manufacturing a semiconductor device as described in item 5 of the scope of patent application, wherein the first insulating layer only exists on the upper surface portion of the gate electrode and Surface part of the side. The method for manufacturing a semiconductor device according to item 5 of the scope of patent application, wherein the first contact window opening and the second contact window opening are formed simultaneously. A method for manufacturing a semiconductor device, comprising the following steps: forming a diffusion layer near a surface of a semiconductor substrate to form a source and a drain region; and forming a first gate and a gate electrode on the semiconductor substrate A second gate electrode; covering the first gate electrode and the second alarm electrode with a first insulating layer; forming a second insulating layer on the semiconductor substrate and the first insulating layer; forming within the second insulating layer A first contact window opening and a second contact window opening, wherein the first contact window opening exposes the source electrode or the drain region and the second contact window opening exposes the first contact electrode on the second alarm electrode; -An insulating layer, and the diameter of the second contact window opening is larger than the diameter of the first contact window opening; a conductive substance is buried in the first contact window opening, and the conductive substance is used in the second contact window A sidewall portion is formed at the opening; the first insulating layer is removed from the bottom of the second contact window opening; and a conductive layer is formed on the second insulating frame to fill the second contact window opening Π. 1 〇. The method for manufacturing a semiconductor device according to item 9 of the scope of the patent application, wherein the first insulating layer includes a silicon nitride layer, and the second insulating layer package > h CNS) A4 size (210X297mm) (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 6 4 98 6 AS A8 Β8 4022pil.t | 〇c / 0 OS C8 D8 cavity, patent application scope includes silicon oxide layer. [1] The method for manufacturing a semiconductor device according to item 9 of the scope of the patent application ', wherein the first insulating layer exists only on the upper surface portion and the side surface portion of the gate electrode. 1 2. The method for manufacturing a semiconductor device according to item 9 of the scope of patent application, wherein the first contact window opening and the second contact window opening are formed simultaneously. 13_—A method for manufacturing a semiconductor device, including the following steps: forming a diffusion layer near a surface of a semiconductor substrate to become a source and a drain region; and forming a __- field insulating layer on the semiconductor substrate; A first gate electrode is formed on the semiconductor substrate, and a second gate electrode is formed on the field insulating layer; a first insulating layer is covered on the first gate electrode and the second gate electrode; A second insulating layer is formed on the substrate and the first insulating layer; the selective etching is performed, and the etching rate of the second insulating layer is greater than the etching rate of the first insulating layer and the semiconductor substrate; A first contact window opening and a second contact window opening are formed in the insulating layer, and the radius of the curtain line of the second contact window opening formed by using the mask pattern is larger than that of the first contact window formed. -The radius of the opening pattern of the contact window is large, and the first contact window U exposes the source or the drain region, and the first contact window opening exposes the first on the second gate electrode. Insulation, mesh. The second The diameter of the contact window opening is larger than the diameter of the first contact window opening U; This paper is scaled to the Chinese national kneading rate (CNS > A4 size (2i × 297mm)) ^-(Please read the note on the back first Please fill in this page again) Order Λ 6 4 986 40 ^ 2pi I'd 〇c / i) (), S AS BS C8 D8 Printed by the Industrial Standards and Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A conductive substance is buried in the opening of the contact window, and a sidewall portion is formed at the U of the second contact window with the conductive substance; by performing selective etching, the etching rate of the first insulating layer is greater than that of the second insulating layer. The etching rate of plutonium further removes the first insulating layer from the bottom of the second contact window opening; and a conductive layer is formed on the second insulating layer to fill the second contact window opening. 14. The method for manufacturing a semiconductor device according to item 13 of the patent application, wherein the first insulating layer includes a silicon nitride layer, and the second insulating layer includes a silicon oxide layer. 15. The method for manufacturing a semiconductor device according to item 13 of the scope of patent application, wherein the first insulating layer is present only on an upper surface portion and a side surface portion of the gate electrode. 16. The method for manufacturing a semiconductor device according to item Π of the application, wherein the first contact window opening and the second contact window opening are formed simultaneously. 17. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein: the semiconductor device is a dynamic random access memory; the first contact window U is a -bit contact window opening, To connect the sand substrate with a bit line, where the sand substrate is the semiconductor substrate, and the bit line is an upper wire in the memory cell area of the dynamic random access memory; the first The two contact window openings are a contact window opening for connecting the _ pole and a bit line, where the bit line is a week around the memory cell area (please read the precautions on the back before filling this page) ) Ken. This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 4 6 4 986 4 0 2 2 pit'.doc / 00S A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs An upper-layer wire in the side circuit area of the patent application; and the conductive layer 'in the first contact window U and the conductive layer forming the sidewall of the second contact window opening include polycrystalline silicon. 18. The method for manufacturing a semiconductor device according to item 5 of the scope of the patent application, wherein: the semiconductor device is a dynamic random access memory; the first contact window opening is a one-bit contact window opening for Connection--a silicon substrate and a bit line, wherein the silicon substrate is the semiconductor substrate, and the bit line is an upper wire in a memory cell region of the dynamic random access memory; the second contact The window opening U is a contact window opening for connecting the gate and a bit line, wherein the bit line is an upper layer wire in a peripheral circuit area surrounding the memory cell area; and in the first The conductive layer in the contact window opening and the conductive layer forming the sidewall of the second contact window opening include polycrystalline silicon. 19. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein: the semiconductor device is a metal oxide semiconductor type large-scale integrated circuit; the first contact window opening is a one-bit contact window opening. □ for connecting _-silicon substrate and --first metal wire, wherein the silicon substrate is the semiconductor substrate, and the first metal wire is an upper layer of one of the large-scale integrated circuits of the metal-oxide semiconductor type. The second contact window opening is a contact window opening 1 for connecting the gate electrode and the first layer of metal wire, wherein the first layer of metal wire is a metal oxide semiconductor type large-scale integrated circuit. _ · Upper lead; and (please read the precautions on the back before filling this page) 11¾ Order ^ '' This paper size applies to China's household rubbing rate (CNS) A4 size (210X297 mm) AB CD 464986 -I02 2 ni rJ 〇〇O () S 6. The conductive layer in the first contact window opening η, and the conductive layer forming the sidewall of the second contact window opening includes tungsten metal. 20. The method for manufacturing a semiconductor device according to item 5 of the scope of the patent application, wherein: the semiconductor device is a metal oxide semiconductor type large-scale integrated circuit; the first contact window opening is a one-bit contact window opening For connecting a silicon substrate and a first layer of metal wires, wherein the silicon substrate is the semiconductor substrate, and the first layer of metal wires is an upper wire of the metal oxide semiconductor type large-scale integrated circuit; the The second contact window opening is a contact window opening for connecting the gate electrode and the first layer of metal wires, wherein the first layer of metal wires is an upper wire of the metal oxide semiconductor type large-scale integrated circuit; And the conductive layer in the first contact window opening, and the conductive layer forming the side wall of the second contact window opening includes tungsten metal. (Please read the notes on the back before filling out this page) Printed by the staff of the Central Bureau of Standards of the Ministry of Economic Affairs and printed by the cooperatives The paper size applies to the Chinese National Standard (CNS) A4 (210X297 mm)