經濟部智慧財產局員工消費合作社印製 464964 6605twf.doc/006 A7 B7 五、發明說明（f ) 本發明是有關於一種半導體的製造方法與結構，且特 別有關於一種金氧半導體（Metal-Oxide-Semiconductor，MOS) 的製造方法與結構 隨著積體電路的積集度不斷的增加’半導體元件的面 積逐漸的縮小，金氧半導體夾著其耗電量非常小’並且適 合高密度的積集製造等諸多優點，實爲現今半導體製程 中，最重要而且應用最廣泛的一種基本的電子單元。 淡摻雜汲極（Lightly Doped Drain)的設計，被廣泛的應 用在解決N型M〇S(N-type MOS, NMOS)電晶體及互補式 M〇S(Complementary M〇S，CMOS)電晶體產生的短通道效應 (Short Channel Effects)。其做法就是在原來MOS源極及汲 極接近通道的地方，再增加一組摻雜程度較原來同型的源 極及汲極爲低的摻雜區。 習知金氧半導體的製造方法，係對已形成淺溝渠隔離 區、閘氧化層、閛極的基底進行離子植入步驟，以在閘極 兩側之基底中形成淡摻雜區。 接著，在閘極的側壁形成間隙壁。最後，以閘極與間 隙壁爲罩幕，進行離子植入步驟，以在間隙壁兩側之基底 中形成濃摻雜區，其中淡摻雜區和濃摻雜區共同組成源/汲 極區。 然而上述傳統製程有以下缺失： 依傳統製程所形成的金氧半導體，雖然形成了淡摻雜 的源/汲極，但是在閘極氧化層與汲極之間仍然會形成一高 場區。由於此高場區的存在導致閘極氧化層與汲極之間電 本紙張尺度適用中國國家標準（CNS)A4規樁（210 X 297公楚） -----------f 裝--------訂---------線7 ' (請先閱讀背面之注意事項再填寫本頁) 464964 6 605twf. doc/ 0 06 A7 _ B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（之） 子，電洞對（Electron-Hole Pairs)的增加，進而產生了熱電子 效應（Hot Electronic Effects)。 另外依傳統製程所形成的金氧半導體，其閘極的兩端 爲直接跨壓在源/汲極之上。於閘極結構的角落與汲極直接 接觸之處則容易產生閘極漏電流（Gate Leakage)的問題。 本發明提供一種改善金氧半導體可靠度的方法，以防 [1：熱電子效應的發生，並提高工作電壓及可靠度。 本發明提供一種改善金氧半導體可靠度的方法，減少 閘極的漏電流，以提高元件的可靠度。 本發明提出一種金氧半導體的製造方法，此方法係對 已形成閘極結構的基底進行淡離子植入步驟，以形成淡摻 雜區。接著，以氧離子或氮離子，進行一較淡離子植入步 驟，其離子植入的角度較大、植入能量較低而植入濃度相 等於淡摻雜源極/汲極區其離子植入的角度、植入能與植入 濃度，以於基底內淡摻雜區之中的表面形成離子摻雜區， 且此離子摻雜區延伸至閘極兩端下方。然後於閘極的側壁 形成間隙壁，再對基底進行一濃離子植入步驟，以形成濃 摻雜區。其後，進行一熱製程形成源/汲極區，並使得離子 摻雜區內的氮離子或氧離子與基底反應’而形成絕緣材質 的阻擋層。之後，於基底上形成介電層’並於介電層中形 成露出閘極以及源/汲極的接觸窗開口。最後’於接觸窗開 口內形成接觸窗。 依照本發明實施例所述，本發明的重要特徵爲以一大 角度傾斜離子植入少驟與…熱製程’形成延伸至閘極結構 4 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） (請先閲讀背面之达意事項再填寫本頁) · — .Ί--I I I 訂·---- 線7 -i# 經濟部智慧財產局員工消費合作社印製 4 S 4、G 4 6605twf.doc/006 A7 五、發明說明（>) 兩端下方的阻擋層，進而在閘極結構與汲極間形成一高阻 抗區，闻場區則發生在局阻ί几區的下方，防止電子-電洞 對的形成以避免熱電子效應。 而且此延伸至閘極結構兩端下方的阻擋層與閘極的間 隙壁對閘極結構兩端的邊角形成了包覆作用，使得閘極結 構的邊角不與源/汲極直接接觸，因此能減少閘極漏電流的 形成。 另外，此大角度傾斜的離子植入步驟於淡離子植入步 驟之後，以合適的植入角度、能量、劑量與離子，使用與 淺離子植入步驟相同的光罩進行。因此本發明不須使用額 外的設備而相容於原來的金氧半導體製程。 爲讓本發明之上述目的、特徵、優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1Α至1D圖是依照本發明一較佳實施例之金氧半導 體之製造流程的剖面示意圖。 標記之簡單說明 100 :半導體基底 102 :渠隔離區 104 :閘氧化層 106:閘極 10 8 :淡離子植入步驟 110 :淡摻雜區 -----------| ^ --------訂---！線 γ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 464964 6605twf.doc/006 A7 _ B7 五、發明說明) 112 :離子植入步驟 114 :離子摻雜區 116 :間隙壁 118 :濃離+植入步驟 120 :濃摻雜區 122 :源/汲極區 124 :阻擋層 126 :介電層 128 :接觸窗開口 130 :導體 實施例 首先，請參照第1A圖。提供一個已形成渠隔離區102、 閘氧化層104以及閘極106的基底100，此基底100之材 質例如爲矽。對基底100進行淡離子植入步驟108，用以 在閘極106兩側之基底100中形成一淡摻雜區110，植入 的劑量約爲l〇u〜l〇12/cm2之間。 接著，請參照第圖。於已形成淡摻雜區110的基 底100上，使用與淡離子植入步驟108相同的光罩（未顯 示），進行一大角度傾斜的離子植入步驟112,於基底100 內淡摻雜區110之中的基底100表面形成離子摻雜區114， 其中該離子植Λ步驟丨12包括以大於淡離子植入步驟108 的角度，並以小於淡離子植入步驟108的植入能量，且使 用與淡離子摻雜步驟108相同的離子劑量以做補償，將離 /-打於基底]〇〇的表面。離子植入步驟112的値入角度約 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） (請先閱讀背面之注意事項再填窝本頁) 經濟部智慧財產局員工消費合作社印製 -------—訂--I --------^§^7---L I ί J 1 I — _ -ί____ 4 6 4 9 6 4 6605twf.doc/006 A7 j_____B7 五、發明說明（y) 爲7〜45度，其植人的能量約爲30〜50仟電子伏特，較 {請先閱讀背面之注意事項再填寫本頁) 佳的植入的離_/·係可以是氮或者是氧，其植入的劑量約爲 1.011〜1012/cm2之間。由於離子摻雜區114是以一大角度傾 斜植入，所以離子摻雜區114會延伸至閘氧化層104兩端 的下方。 經濟部智慧財產局員工消費合作社印製 接著，請參照第1C圖。在閘極106側壁形成間隙壁 116。其形成的方法例如是在基底100上沉積一層共形之 絕緣層（未顯示），其中形成絕緣層之材質包括氧化政或 氮化矽，形成的方法包括化學氣相沈積法等。之後，再移 除部份之絕緣層，在閘極106側壁形成間隙壁116，並曝 露出閘極106及部份基底100。其中移除部份絕緣層之方 法包括非等向性蝕刻法。然後以閘極丨06與間隙壁U6爲 罩幕，進行濃離子植入步驟118，以在間隙壁H6兩側之 基底100中形成一濃摻雜區120。之後，進行一熱處理步 驟，而在此熱處理步驟中離子摻雜區H4之中的離子與基 底100的砂成分反應，而形成一阻擋層丨24。當離子摻雜 區114之中的離子爲氧或氮，則所形成的阻擋層124爲氧 化砍或氮化砂，並使淡慘雑區11 〇和濃慘雜區12 〇形成具 有淡摻雜結構的源/汲極區122。由於離子摻雜區1U之中 的離子延伸至部分的閘極氧化層104的下方’因此，所形 成之阻擋層124亦會延伸至閘氧化層104兩端的下方，且 阻擋11 124的材質爲氧化物或是氮化物等絕緣材質’所以 在閘氧化層104與汲極122間形成一尚阻抗區’尚場區發 生茌高阻抗區的下方’因此就不容易產生熱電效應"而 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 經濟部智慧財產局員工消費合作社印製 464964 66〇5twf.doc/〇〇6 A7 __B7_____ 五、發明說明（& ) 且此尚阻ί几區與間隙壁116對鬧極106與問氧化層104兩 端的邊角形成包覆作用，因此能減少閘極106的漏電流。 最後，請參照第1D圖。在基底1〇〇上形成介電層126， 其形成的方法例如是化學氣相沈積法，介電層126的材質 例如是氧化矽或是氮化矽。接著以微影與蝕刻製程去除部 分介電層126，以形成露出閘極106或源/汲極122的表面 的接觸窗開口 128，其中蝕刻去除部份的介電層126的方 法，例如是非等向性蝕刻法。當介電層126蝕刻之後，再 施以過度蝕刻，以蝕刻去除源/汲極122上方的阻擋層124。 此蝕刻步驟，可以蝕刻時間予以控制，以去除部份的阻擋 層124，露出源/汲極122的表面。最後於接觸窗開口 128 內塡入導體Π0，以形成接觸窗，導體130的材質例如爲 多晶矽，其形成的方法例如是化學氣相沈積法在介電層126 的表面上與接觸窗開口 128之中沉積多晶矽層之後，再以 回蝕刻或化學機械硏磨製程將介電層126表面上多餘的複 晶矽層去除，留下接觸窗開口 128之中的多晶矽層。 由上述本發明較佳實施例可知，本發明的特徵是以大 角度傾斜離子植入步驟以及回火製程，形成延伸至閘極結 構兩端下方的阻擋層。此阻擋層在閘極結構與汲極間形成 一高阻抗區，使得載子電流沿著汲極與基底的接觸面傳 導，高場區則發生在高阳.抗區的下方，防止電子-電洞對 的形成以避免熱電子效應。 而且此延伸至閘極結構兩端_F方的阻擋層與閘極的間 隙壁對閘極結構兩端的邊角形成了包Μ作用，使得閘極結 8 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公爱） ,kl,---------{ 裝-------1 訂 ίι!----線-·* (請先閱讀背面之注f項再填寫本頁) 4 6 4 9 664〇 5 twf. do c/0 0 6 A7 B7 五、發明說明（q ) . 構的邊角+與源/汲極直接接觸，因此能減少閘極漏電流的 形成。 . 另外，此大角度傾斜的離子植入步驟於淺離子植入步 驟後，以合適的植入角度、能量、，劑量與離子，使用與淺 離子植入步驟相同的光罩進行。因此本發明不須使用額外 的設備而相容於原來的金氧半寧體製程。~ 雖然本發明已以一較佳實施例掲露如上，然其並非用 以限定本發朋，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 464964 6605twf.doc / 006 A7 B7 V. Description of the Invention (f) The present invention relates to a method and structure for manufacturing a semiconductor, and more particularly to a metal-oxide semiconductor (Metal-Oxide -Semiconductor (MOS) manufacturing method and structure With the accumulation of integrated circuits, the area of semiconductor devices is gradually reduced, and the power consumption of metal oxide semiconductors is very small, and it is suitable for high-density accumulation. Many advantages, such as manufacturing, are the most important and most widely used basic electronic unit in today's semiconductor manufacturing processes. The design of Lightly Doped Drain is widely used to solve N-type MOS (N-type MOS) transistors and complementary MOS (Complementary MOS, CMOS) transistors The resulting short channel effects. The method is to add a set of doped regions with lower levels of source and drain than the original source and drain where the original MOS source and drain are close to the channel. A conventional method for manufacturing a metal oxide semiconductor is to perform an ion implantation step on a substrate having a shallow trench isolation region, a gate oxide layer, and a hafnium electrode formed to form a lightly doped region in the substrate on both sides of the gate. Next, a spacer is formed on the side wall of the gate. Finally, the gate and the gap wall are used as a mask to perform an ion implantation step to form a heavily doped region in the substrate on both sides of the gap wall. The lightly doped region and the heavily doped region together form a source / drain region. . However, the above traditional process has the following defects: Although the gold-oxygen semiconductor formed by the traditional process has formed a lightly doped source / drain, a high field region will still be formed between the gate oxide and the drain. Due to the existence of this high field region, the electrical paper size between the gate oxide layer and the drain electrode is applicable to the Chinese National Standard (CNS) A4 gauge pile (210 X 297 cm) ----------- f Install -------- Order --------- Line 7 '(Please read the precautions on the back before filling this page) 464964 6 605twf. Doc / 0 06 A7 _ B7 Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives. 5. Description of the invention. The increase in Electron-Hole Pairs has created Hot Electronic Effects. In addition, the metal-oxide semiconductor formed by the traditional process has two ends of the gate directly across the source / drain. At the corner of the gate structure where it is in direct contact with the drain, the Gate Leakage problem is prone to occur. The present invention provides a method for improving the reliability of a metal-oxide semiconductor to prevent [1: the occurrence of a thermal electron effect, and improve the working voltage and reliability. The invention provides a method for improving the reliability of a metal-oxide semiconductor, reduces the leakage current of a gate electrode, and improves the reliability of a component. The invention proposes a method for manufacturing a gold-oxide semiconductor. This method involves performing a light ion implantation step on a substrate on which a gate structure has been formed to form a lightly doped region. Next, a lighter ion implantation step is performed with oxygen ions or nitrogen ions. The ion implantation angle is larger, the implantation energy is lower, and the implantation concentration is equal to that of lightly doped source / drain regions. The implantation angle, implantation energy, and implantation concentration form an ion-doped region on the surface of the lightly-doped region in the substrate, and the ion-doped region extends below both ends of the gate. A spacer is then formed on the side wall of the gate electrode, and then a concentrated ion implantation step is performed on the substrate to form a heavily doped region. After that, a thermal process is performed to form the source / drain region, and the nitrogen or oxygen ions in the ion doped region react with the substrate 'to form a barrier layer of insulating material. Thereafter, a dielectric layer 'is formed on the substrate, and a contact window opening is formed in the dielectric layer to expose the gate electrode and the source / drain electrode. Finally, a contact window is formed in the opening of the contact window. According to the embodiment of the present invention, the important feature of the present invention is that the ion implantation at a large angle is inclined and the thermal process is formed to extend to the gate structure. 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x 297 mm) (Please read the notice on the back before filling out this page) · — .Ί--III Order · ---- Line 7 -i # Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 4 S 4, G 4 6605twf.doc / 006 A7 V. Description of the invention (>) The barrier layer below the two ends forms a high-impedance region between the gate structure and the drain, and the smell field region occurs below the partially blocked regions. To prevent the formation of electron-hole pairs to avoid thermionic effect. In addition, the barrier layer extending below the gate structure and the gap between the gate structure form a covering effect on the corners of the gate structure, so that the corners of the gate structure do not directly contact the source / drain. Can reduce the formation of gate leakage current. In addition, the ion implantation step at a large angle is performed after the light ion implantation step with a suitable implantation angle, energy, dose, and ions using the same mask as the shallow ion implantation step. Therefore, the present invention is compatible with the original metal oxide semiconductor process without using additional equipment. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Figures 1A to 1D are A schematic cross-sectional view of a manufacturing process of a metal-oxide semiconductor according to a preferred embodiment of the present invention. Simple description of the mark 100: semiconductor substrate 102: trench isolation region 104: gate oxide layer 106: gate electrode 10 8: light ion implantation step 110: lightly doped region ----------- | ^- ------- Order ---! Line γ (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 464964 6605twf.doc / 006 A7 _ B7 V. Description of the invention 112: Ion implantation step 114: ion doped region 116: spacer 118: dense ionization + implantation step 120: heavily doped region 122: source / drain region 124: barrier layer 126: dielectric layer 128: contact window opening 130 : Conductor Example First, please refer to FIG. 1A. A substrate 100 having a trench isolation region 102, a gate oxide layer 104, and a gate electrode 106 is provided. The material of the substrate 100 is, for example, silicon. A light ion implantation step 108 is performed on the substrate 100 to form a lightly doped region 110 in the substrate 100 on both sides of the gate 106, and the implanted dose is about 10u to 1012 / cm2. Next, please refer to the figure. On the substrate 100 on which the lightly doped region 110 has been formed, the same photomask (not shown) as the light ion implantation step 108 is used to perform a large-angle tilted ion implantation step 112 to lightly doped the region in the substrate 100. An ion doped region 114 is formed on the surface of the substrate 100 in 110, wherein the ion implantation step 12 includes an angle greater than the light ion implantation step 108 and a smaller implantation energy than the light ion implantation step 108, and uses To compensate, the same ion dose as in the light ion doping step 108 is applied to the surface of the substrate. The penetration angle of the ion implantation step 112 is about the paper size. The Chinese national standard (CNS) A4 specification (210 x 297 mm) is applicable. Printed by the cooperative --------- Order--I -------- ^ § ^ 7 --- LI ί J 1 I — _ -ί ____ 4 6 4 9 6 4 6605twf.doc / 006 A7 j_____B7 V. Description of the invention (y) is 7 ~ 45 degrees, and its energy for planting is about 30 ~ 50 仟 electron volts, which is better than {Please read the precautions on the back before filling this page) _ / · Department can be nitrogen or oxygen, and the implanted dose is about 1.011 ~ 1012 / cm2. Since the ion-doped region 114 is implanted obliquely at a large angle, the ion-doped region 114 extends below both ends of the gate oxide layer 104. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy Next, please refer to Figure 1C. A spacer 116 is formed on the side wall of the gate electrode 106. The formation method is, for example, depositing a conformal insulating layer (not shown) on the substrate 100, wherein the material for forming the insulating layer includes an oxide or silicon nitride, and the forming method includes a chemical vapor deposition method. After that, a part of the insulating layer is removed to form a spacer 116 on the side wall of the gate electrode 106, and the gate electrode 106 and a part of the substrate 100 are exposed. A method in which a part of the insulating layer is removed includes an anisotropic etching method. Then, using the gate electrode 06 and the spacer U6 as a mask, a concentrated ion implantation step 118 is performed to form a heavily doped region 120 in the substrate 100 on both sides of the spacer H6. Thereafter, a heat treatment step is performed, and in this heat treatment step, the ions in the ion doped region H4 react with the sand component of the substrate 100 to form a barrier layer 24. When the ions in the ion-doped region 114 are oxygen or nitrogen, the barrier layer 124 formed is oxidized or nitrided sand, and the lightly doped region 11 o and the heavily doped region 12 o are formed with light doping. The source / drain region 122 of the structure. Because the ions in the ion-doped region 1U extend below a portion of the gate oxide layer 104, the barrier layer 124 formed also extends below both ends of the gate oxide layer 104, and the material of the barrier 11 124 is oxidized Insulation materials such as metals or nitrides', so a high-impedance region is formed between the gate oxide layer 104 and the drain electrode 122, and the high-impedance region occurs in the high-field region, so it is not easy to generate a thermoelectric effect. Standards apply to China National Standard (CNS) A4 specifications (210 X 297 public love) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 464964 66〇5twf.doc / 〇〇6 A7 __B7_____ 5. Description of the invention (&) The resistance regions and the partition wall 116 form a covering effect on the corners of the both ends of the anode 106 and the oxide layer 104, so that the leakage current of the gate 106 can be reduced. Finally, please refer to Figure 1D. A dielectric layer 126 is formed on the substrate 100, for example, by a chemical vapor deposition method, and the material of the dielectric layer 126 is, for example, silicon oxide or silicon nitride. Then, a portion of the dielectric layer 126 is removed by a lithography and etching process to form a contact window opening 128 that exposes the surface of the gate electrode 106 or the source / drain electrode 122. The method of etching and removing a portion of the dielectric layer 126 is, for example, non-equivalent Anisotropic etching. After the dielectric layer 126 is etched, over-etching is performed to remove the barrier layer 124 over the source / drain 122 by etching. In this etching step, the etching time can be controlled to remove part of the blocking layer 124 and expose the surface of the source / drain electrode 122. Finally, a conductor Π0 is inserted into the contact window opening 128 to form a contact window. The material of the conductor 130 is, for example, polycrystalline silicon. The formation method is, for example, chemical vapor deposition on the surface of the dielectric layer 126 and the contact window opening 128. After the polycrystalline silicon layer is deposited in the middle, the excess polycrystalline silicon layer on the surface of the dielectric layer 126 is removed by an etch-back or chemical mechanical honing process, leaving the polycrystalline silicon layer in the contact window opening 128. As can be seen from the above-mentioned preferred embodiments of the present invention, the present invention is characterized in that the barrier layer is formed to extend below the two ends of the gate structure by a step of ion implantation at a large angle and a tempering process. This barrier layer forms a high-impedance region between the gate structure and the drain, so that the carrier current is conducted along the contact surface between the drain and the substrate, and the high-field region occurs below the high-yang. Anti-region, preventing electron-holes Formation of pairs to avoid thermionic effects. And the barrier layer that extends to both ends of the gate structure _F side and the gap between the gate structure form a M effect on the corners of both ends of the gate structure, so that the gate junction 8 paper size applies to Chinese national standards (CNS > A4 specification (210 X 297 public love), kl, --------- {装 ------- 1 order ίι! ---- line- · * (Please read the note f on the back first Please fill in this page again) 4 6 4 9 664〇5 twf. Do c / 0 0 6 A7 B7 V. Description of the invention (q). The corners of the structure + directly contact the source / drain, which can reduce the gate leakage The formation of electric current. In addition, after the large-angle inclined ion implantation step, after the shallow ion implantation step, the same implantation angle, energy, dose and ion are used, using the same mask as the shallow ion implantation step. Therefore, the present invention does not require additional equipment and is compatible with the original metal oxybanning process. ~ Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present friend, any familiarity Those skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be attached as follows. Please refer to the definition of the patent scope. (Please read the notes on the back before filling out this page.) Printed on the paper by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm )