4 6 3 3 5 9 Α7 Β7 五、發明説明（1 ) 本發明係有關於靜電放電保護技術，特別有關於 種用於靜電放電保護電路（dynamic substrate-coupled electrostatic discharge protection circuit)之多重指狀結 構（multi-finger structure)。 在積體電路（ICs)的應用上，導體、半導體及絕緣 層等材料已被廣泛使用，而薄膜沈積（Thiri Film Deposition)、微影製程（photolithography)、及姓刻程序 (etching)則為主要之半導體技術。 其中薄膜沈積，即是將上述各材料分層沈積於待 製晶圓（wafer)表面’而微影製程則是複製（replicate)所 欲形成之元件或電路圖案，並透過蝕刻步驟，將該些 圖案轉移至待製晶圓表面各層以形成内部半導體元件 如電晶體或電容等。此外為避免水氣、鹼金屬離子的 侵入或機械性刮傷，必須另沈積一護層（passivati〇n layer)以保護前述積體電路結構，且尚須定義出作為輪 出/入（input/output)用之金屬鲜墊（metal pad)區之範圍， 並以姓刻步驟挖開護層，露出金屬鮮整表面，方能進 行最後之構裝（packaging)工作。 經确部中次榡率局貝J'消费合作社印^ 然而在前述所完成之半導體裝置中，靜電放電 (ESD : electrostatic discharge)經常在乾燥環境下因碰 觸帶靜電體而自晶片之輸出/入墊（I/O pad)侵入，造成 積體電路損傷。 尤其在進入極大型積體電路（ULSI)世代以後，例如 使用0.25μπι以下之深次微米製程所形成的半導體震 本纸张尺度適用中國國家標嗥（CNS ) A4規格（210X297公釐） 463359 經潢部中央標準局員τ_消资合作社印裝 A7 __________B7_五、發明説明（2) 置如CMOS ICs ’其薄閘極氧化層（thin gate oxide)、 短通道（short channel iength)、和淺接面（shall〇w junction)等結構特徵，或者是淡摻雜（LDD)和金屬矽化 物擴散（salicided diffusion)技術的運用，均嚴重衰減了 電晶體之抗ESD能力’且影響其對靜電放電之可靠度 問題，例如’前述製作之電晶體元件因具有容易破裂 (rupture)之薄閘極氧化層（化丨n gate oxide)，因此對高電 壓放電（high voltage discharges)極為敏感。 般靜電放電引起電子元件失效者可分為電壓型 扣傷和電流型損傷，而依據人體模型，高靜電電壓可 能源自於人體碰觸到積體電路接腳，其可能產生超過 2000V之電荷並以較長期間之高電流脈衝型態出現；另 依據機器模型’尚靜電電壓亦可能來自積體電路接腳 與不良接地導體，如測試機台之接觸，其則能以較短 期間之高電壓脈衝型態出現。若依人體模型設計靜電放電保護結構時’其ESD值需高達4000V，而若依機 器模型設計靜電放電保護結構時，其ESE)值則約 500V。 目則有關靜電放電保護結構’大抵係利用保護電 路之電晶體導通（turn on)機制和電晶體崩潰_跳回機制 兩種’其中電晶體導通（turn on)機制係以厚氧化型電晶 體閘極連接輸出/入墊，因此以導通通道臨限電壓值為 其特徵，而電晶體朋潰-跳回機制係以薄氧化型電晶體 汲極連接輸出/入墊’閘極則與源極連接，因此以電晶 本紙張尺度適用中國國家標準（CNS > Α4規格（2)0X 297公釐> (請先閱讀背面之注意事項再填寫本頁) 訂 邊！ m· It 經潢部中央標準局員工消费合作社印繁 4 6335 9 Α7 __________B~7 五、發明説明（3) ^ 體崩潰電壓值為其特徵。 以目前較被廣泛使用之崩潰_跳回機制為例，如第 1圖所示’半導體裝置一般具有内部電路元件區30及 一與之電性連接之輸出/入墊（I/〇 pad)1〇，其中，可於 兩者之間加入一靜電放電保護結構2〇如一 NMOS電晶 體’其主要功能係依據第3圖所示，NMOS電晶體之 沒極電壓對汲極電流之特性曲線，一般包括線性區 (linear region)、飽和區（saturation region)、累增區 (avalanche region)和跳回區（snapback region)等四個階 段’當發生靜電放電時，自輸出/入墊1〇侵入之靜電電 壓即促使NMOS電晶體20崩潰（breakdown)而直接進入 跳回區（snapback)以對此靜電放電進行限電位和過渡， 避免内部電峰元件區30發生ESD損傷。 另為進一步詳細說明其跳回機制，請參閱第2 圖，靜電放電保護結構20通常包括一金氧半（]^08)電 晶體’如NMOS、PMOS、或CMOS電晶體，而依據 第2圖所示’在P型基底接地之NMOS電晶體的場合 中，具薄閘極氧化層之閘極21和源極22同為接地，因 此，在正常運作時NMOS電晶體25並不導通，而在發 生靜電放電時，則利用内建NPN雙載子電晶體 26(build-in parastic npn bipolar transistor)之導引 (bypass)，來保護内部電路元件區3〇，其中，源極N+ 型捧雜區22形成射極Ε，ί及極N+型捧雜區23形成年 極C，而Ρ型矽基底24則形成基極Β，由於射基極 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210Χ297公釐） ,衣------II------^ 1 (請先閱讀背面之注意事項再填寫本頁) 經漪部中央標準局負工消资合作社印裝 4 633 5 9 A7 __ -__B7 五、發明説明（4) ~~~~ E、B接地’當靜電放電如一對地為正之eSd電壓脈 衝，自輸出/入金屬墊10經汲極N+型摻雜區23侵入 時，ESD電壓將觸發(trigger)寄生雙載子電晶體26， 形成正回饋（positive feedback)，故而使NMOS電晶體 25 因崩潰（breakdown)而進入跳回區（snapback regi〇n)， 並藉此傳導大量的ESD電流至接地電位節點，其令 NMOS電晶镡25之崩潰電壓（breakdown voltage)出現在 節點Q ’即用以作為靜電放電之箝制電壓（ciamp voltage) 〇 其中為使NMOS電晶體能容納大量之靜電放電電 流’但又能避免閘極結構之縱寬方向過長，因此一般 係採用如第4圖之傳統多重指狀結構（multi_finger structure)之佈局方式，依據該圖，其係在一 p型基底 或P型井區100中形成一主動區2〇〇，在主動區200中 則包括有多_並聯MOS元件，如210 、230和250 等’其等效電路示意圖則如第5圖所示，而每一 MOS 元件則均由以下結構組成，如源極區S ，形成於主動 區之既疋位置，及極區D，形成於主動區之相對各源 極區S之位置；以及閘極結構G，分別形成於各源極 區S和汲極區D間之主動區表面。其中，各M〇S元件 之汲·極區D係彼此相鄰而電性連接在一起，源極區s 亦然’此外閘極結構G和前述源極s另透過圍繞p型 井區100之P+接觸區150接至一偏壓源，例如一接地 節點Vss，以構成第5圖之多個並聯M〇s元件，接觸 本紙張尺度適用中國國家椋孪（CNS) Λ4規格（21〇χ29»釐 (請先閲讀背面之注意事項再填寫本頁) ,1Τ 吹Ί· A7 463359 五、發明説明（5) " 窗27〇則用以進行各區域或節點之電性連接，因此，依 據前述第2蘭之原理說明，傳統多重指狀結構係利用並 聯之多個MOS元件及其内部寄生之雙載子電晶體來形 成崩潰-跳回機制之靜電保護模式。 然而’在實際運用上，由於在同一指狀闡極結構 G之長度設計上同為γ丨值，其並未隨著前述閘極結構 之縱寬方向X改變，因此，就沿閘極結構之縱寬方向 X形成之多個寄生雙載子電晶體而言，其基極（base)B 長度均為相同（可局部參照第2圖之閘極結構與基極長 度之關係），而此亦導致相同之電流增益係數p值 (current gain)。至於各寄生雙載子電晶體之基極電流， 則由於各雙載子電晶體與P+接觸區150之距離差異， 導致等效基極阻值於兩端位置（L，_L)處最小，因此相對 基極電流最大，於汲極區D產生之集極電流亦因此而 自中〇(0)向兩端之位置（L，-L)而變大，如此當靜電放電 自輸出/入墊10侵入汲極D時，便經常發生靜電電流不 均勻分佈之問題，如接近閘極結構縱寬方向之中心處 幾無靜電電流流通，但卻有大量靜電電流集中於兩端 (L，-L)而生毀損之情形。 有鑑於此，本發明之一目的為當靜電放電侵入 時，於靜電放電保護電路中，選擇一種多重指狀結 構，其内部之閘極結構長度係沿縱寬方向而變化，其 中’基極等效電阻較高者，其閘極結構長度較短，而 基極等效電阻較低者，其閘極結構長度較長，其用以 本紙張尺糾财關家鮮(CNS)A^ (2107297-^¾ ) — II____ _ I / _ _____ _ τ II _ I---发 1 -1-5么 . I (請先閱讀背面之注意事項再填寫本頁} 經淨部中决標枣局貝J消资含作社印製 經满部中次標準局員工消费合作社印製 4 6335 9 A7 _— B7 五、發明説明（6) 使各寄生雙載子電晶體以不同之基極電流搭配不同之 電流增益β值，而形成差不多之集極電流，以增加靜電 電流經汲極擴散時之均勻度。 為達成±述目的，本發明提供一種多重指狀靜電 保護結構，適用於-基底，其包括：複數源極區，形 成於該基底之既定位置；複數汲極區，形成於該基底 之相對該些源極區之位置；以及複數閘極結構，分別 形成於該些源極區和汲極區間之基底表面，以構成複 數個並聯之MOS元件，其中，閘極結構之長度係沿前 述各閘極結構之縱窗‘方向而變化。亦即當基極等效電 阻較高者如接近閘極結構縱寬方向之中心處，其閘極 結構長度較知，而當基極等效電阻較低者如接近閘極 結構縱寬方向之兩端處，其閘極蛙椹長度較長。 為讓本發明之上述和其他目的、特徵、和優點能 更明顯易懂，下文特舉-較佳實施例，並配合所附圖 式，作詳細說明如下： 圖式之簡單說明： 第1圖係顯不傳統形成靜電放電保護結構之内部 電路元件示意圖。 第2圖係顯示利用崩潰_跳回機制之傳統靜電放電 保護結構之半導體剖面圖。 第3圖係顯示靜電放電保護結構内之電晶體的特 性曲線。 第4圖係顯示傳統多重指狀靜電保護結構的半導 本紙張尺度刺彳1翻丨縣（CNS ) Α4^ ( 210X297^7 ‘％----^----,1Τ------^ I (請先閱瘦背面之注意事項再填寫本頁〕 4 6335 9 A7 一 ·™— -------- B7 「 五、發明説明（7) — ~^ 體佈局圖。 第5圖係顯示第4圖之傳統等效電路示意圖。 (#先閱讀背面之注意事項再填疴本頁) 第6圖係顯示第4圖之傳統半導體佈局和第5圖之 傳統等效電路中，各雙載子電晶體之電性連接關係。 第7圖係本發明之一實施例中，多重指狀靜電保 護結構的半導體佈局圖。 ^第8圖係顯示第7圖之多重指狀靜電保護結構的 半導體佈局圖中，各雙載子電晶體之電性連接關係。 蔚號說明 10〜輸出/入墊；20〜靜電放電保護結構2丨〜閘極結 構；22〜源極；23〜汲極；24〜基底；25〜NM〇s電晶 體；26〜寄生雙載子電晶體；3〇〜内部電路元件區； 1〇〇〜P型井區；150〜P+接觸區；2〇〇〜主動區；210、 230、250〜MOS 元件；210’、23〇，、25〇，〜M〇S 元 件；Rl、R2〜等效電阻；R〜基極電阻；Ic，Ic，〜集極 電流；lb〜基極電流；β，β，〜電流增益；τ〜寄生雙載子 電晶體；270〜接觸窗。 實施例 經淤部中央標準局員工消費合竹社印來 為方便比較起見’在說明本實施例前，先行敘述 第6圖之機制’以顯示本發明實施例與傳統多重指狀結 構之區別與改善之效果。 請參閱第6圖，其代表第4圖之傳統半導體佈局 和第5圖之傳統等效電路中，各雙載子電晶體之電性連 接關係。首先依據第4圖，以MOS元件210為例，如 本紙張尺度適用中國國家標學-(CNS ) Λ4規格Uioxw7公釐） 463359 經"部中央桴率扃Μ工消費合作·社印繁 A7 五、發明説明（8) ' 在p尘基底之NMOS電晶體，N型基底之PMOS電晶 體，或者在雙井結構之CM〇s電晶體。以NM〇s為 ^其扣狀閘極結構G係沿縱寬方向（x，-x)配置在主動 區200上’靠近中心處為（〇)，而於接近P+接觸區1 50 處之兩鳊則為（L，_l) ’至於長度則為γι值，因此就沿 閘極結構之縱寬方向χ形成之多個寄生雙載子電晶體 而言，其基極（base)B長度均為相同，而此亦導致相同 之電流增益係數β值（current gain)。 其中’依該指狀閘極結構G之沿縱寬方向（χ，_χ)剖 面線I - I ’，其閘極結構G下方之主動區隨位置之改變 而形成多個寄生雙載子電晶體，如第6圖所示，在集極 c方面’當靜電放電電流IESD自輸出/入墊1〇侵入 NMOS元件210之汲極區D時，會分別流入各寄生雙 載子電晶體T(-L)…T(0)，…丁 (χ), T(x+dx)...T(L)中之集極 C ’在射極E方面’各雙載子電晶體均電性連接至 MOS元件之源極接地節點vss，而p型丼區或基底亦 透過P+接觸區接地。 此時’在各雙載子電晶體T(-L)....T(0)，....T(X)， T(x+dx)….T(L)之基極B經基底至接地節點Vss之路徑 上’則各自形成有基極電阻R(-L)...,R(0)，…T(x), R(x+dx)…R(L)，其各由等效電阻Ri和串聯數目不等之 等效電阻R2形成’以寄生雙載子電晶體 T(x)，…T(x+dx)...，T(L)為例，由於各雙載子電晶體與接 地P+接觸區150之距離越大，其各自串聯電阻R2之數 本紙张尺度適用中國國家標準（CNS ) Λ4規格（210X29：；公釐） ---------笨-------訂------^ 1 (請先閱讀背面之注^^^項再填寫本頁) 4 633 5 9 好碘部中决標率局ί消贽合作社印繁 A7 B7 五、發明説明（9) 量越多，因此可知由基極B看出之基極電阻值R(x)於 接近中心位置（X)處最大，相對基極電流化彳幻則最小； 反之，隨著遠離中心處之位置，如在（X+(JX)處之電晶體 T(x+dx) ’其由基極B看出之串聯等效基極電阻值 R(x+dx)逐漸減小’相對基極電流ib(x+dx)則逐漸增 加；直到兩端位置（L，-L)處’可得最小串聯等效基極電 阻R(-L)、R(L)，故相對基極電流ib(L)最大。 由於在各寄生雙載子電晶體T(_Ly τ(〇), τ(χ)， T(x+dx)….T(L)中’；;及極區d產生之集極電流，係等於 基極電流與電流增益係數β之乘積（Ic=p x Ib),因此所 得到之集極電流 Ic(-L)...Ic(0)”..Ic(x), Ic(x+dx)…Ic(L)， 係自約中心（0)處向兩端之位置（L，-L)而變大，如表一所 示。 表一 基極電阻 R(-L)〈，…< R(〇)>_> R(x)> R(x+dxy > 基極電流lb Ib(-L)>〜> Ib(〇)< — < Ib(x)< Ib(x+dx)?；..< IbfL) 電流增益β P(-L)—…=β(〇)=.,,：=β(χ)= p(x+dx)…=β(χ、 集極電流Ic Ic(-L)>...> le(〇)<...< ic⑻< ic(x+dx) < Ic(X) 由表一 可知’傳統結構係由於各MOS電晶體閘極 結構之長度相同’因此就沿閘極結構之縱寬方向X形 成之多個寄生雙載子電晶體而言，其基極（base)B長度 亦為相同’故依此能得到相同之電流增益係數β值 (current gain) ’加以各雙載子電晶體與ρ+接觸區15〇之 距離差異’導致等效基極阻值於兩端位置（L，_L)處最 10 本紙張尺度邮料（CNS) Λ4^ (公廣)- — ---------衣-----„--訂------气| {請先閲讀背面之注意事項再填寫本頁) 4b 33 5 9 A7 ^________ B7 五、發明説明（w) 小，因此相對基極電流最大，於汲極區D產生之集極 電流亦因此而自中心（〇)向兩端之位置（L,_L)而變大，如 此當靜電放電自輸出/入墊10侵入汲極〇時，便經常發 生靜電電流不均勻分佈之問題。 據此，請參閱第7圖，其顯示本發明之一實施例 中，多重指狀靜電保護結構的半導體佈局圖。首先本 圖以並聯之MOS元件210’、230,和250,為例，其中指 狀閘極結構G’係沿縱寬方向（χ,·χ)配置在主動區2〇〇 上’靠近中心處為（0) ’而於接近ρ+接觸區15〇處之兩 端則為（L，-L) ’而依該指狀閘極結構G’之沿縱寬方向 (X，-X)剖面Π-Π ’ ’其閘極結構G’下方之主動區200隨 位置之改變而形成多個寄生雙載子電晶體，至於長度 則分別有較窄之Y1值和逐漸加寬之Y2值，此即為與 傳統結構最大不同之處’因此就沿閘極結構之縱寬方 向X形成之多個寄生雙載子電晶體而言，其基極 (base)B長度也隨之改變，而此亦導致其各具有不同之 電流增益係數β’值（current gain)，故該β，值係於接近中 心位置（X)處之β’（χ)最大，反之，隨著遠離中心處之位 置，如在（x+dx)處之電晶體T(x+dx)，其電流增益 β’（χ+<1χ)值逐漸減小，直到兩端位置（L，-L)處，可得最 小之電流增益β’（·Ι〇、β’(ί)。 此外，請參閱第8圖，當靜電放電電流Iesd自輸 出/入塾10侵入汲_極區D時，會分別流入各雙載子電晶 體丁(-1^..1'(0)，...1'(乂)，1'(\+£1\1..丁(1^中之集極（：，在射 讀先間讀背面之注意事項再填寫本頁) 訂 經漪部中央標準局員工消贽合作社印製 (CNS ) ( 21 OX 297-^¾ ) A7 4 6 33 5 9 —___ B7_ 五、發明説明（11) ~~ ~ 極E方面.，各雙載子電晶體t(-L)...T⑼，,.ίΤ(认 T(x+dx)".，T(L)均電性連接至MOS元件之源極接地節點 Vss ’而P型井區或基底亦透過P+接觸區接地。 因此’在各雙載子電晶體T(_L)...T⑼，τ(χ)5 T(x+dx)…T(L)之基極Β經基底至接地節點yss之路徑 上’各自形成有基極電阻R(_L)...,R⑼ R(x+dx)…R(L) ’其於接近中心位置⑻處最大，相對基 極電流Ib(x)則最小；反之，隨著遠離中心處之位置， 其串聯等效基極電阻值R(x+dx)逐漸減小，相對基極電 流Ib(x+dx)則逐漸增加；直到兩端位置（L，_L)處，可得 最小串聯等效基極電阻r(_l)、r(l)，故相對基極電流 Ib(L)最大。 同理’由於在各寄生雙載子電晶體T(-L)…Τ(0)，.·.Τ(χ)，T(x+dx)...T(L)中，汲極區 D 產生之集 極電流’係等於基極電流與電流增益係數β’之乘積 (Ic’=p’x lb) ’因此藉由上述電流增益係數β之調整， 所得之集極電流 Ic’(-L)...lc’(0),...lc’(x), Ic’（x+dx)."，Ic’（L)，其與閘極結構之縱寬方向距離關係 即如表二所示。 表二 基極電阻 R(-L)<...< R(〇)>...> R(x)> R(x+dx)...> R(L) 基極電流lb Ib(-L)>...> lb(0)<...< Ib(x)< Ib(x+dx)...< Ib(L) 電流增益p’ β’(-ί) < ..· < β，(〇) < …< p，(x)< p，(x+dxy“ < p’(L) 集極電流Ic’ . .=10^0)=.. .Hc^xHc^x+dx).. .=101 (L) 12 本紙張尺度適用中國國家標皁（CNS } Λ4说格（210X29?公釐〉 -----------h I I ^.丁 - - n n n -令、 1 ^ 、V6 A (諳先閱讀背面之注意事項再填寫本頁〕 經"部t央標準局負工消资合作社印製 ^消部中*標^-局負工消費合"社印％ A7 Β7 五、發明説明（12) '—— ----- 由表二可知’當靜電放電侵入時，於靜電放電保 護電路中，選擇-種多重指狀結構，其内部之閉極社 構長度係沿縱寬方向而變化，其中，當基極等效電、; 較商者如接近間極結構縱寬方向之中心處，其間極結 構長度較短，而當基極等效電阻較低者如接近閉極结 構縱寬方向之兩端處’其閘極結構長度較長。如此； 使各寄生雙載子電晶體以不同之基極電流搭配不同之 電流增益β [而形成相同之集極電流’亦即增加靜電 電流在各MOS元件之汲極擴散之均勻度，使多重指狀 靜電保護結構内之寄生雙载子電晶體均勻導通，而不 致因集中於兩端而生毁損之情形。 本發明中所應用之物質材料’並不限於實施例所 弓丨述者，其能由各種具恰當特性之物質和形成方法所 置換，且本發明之結構空間亦不限於實施例引用之尺 寸大小。 雖然本發明已以一較佳實施例揭露如下，然其並 非用以限定本發明，任何熟習此技藝者，在不脫離本 發明之精神和範園内，當可做些許之更動與潤飾，因 此本發明之保護範圍當視後附之申請專利範圍所界定 者為準。 1 3 1：、紙張尺度適则(CNS)鐵格（21Qx 297公廣） (請先閱讀背面之注意事項再填寫本頁)4 6 3 3 5 9 Α7 Β7 V. Description of the invention (1) The present invention relates to electrostatic discharge protection technology, and in particular to a multi-finger structure for a dynamic substrate-coupled electrostatic discharge protection circuit (Multi-finger structure). In the application of integrated circuits (ICs), materials such as conductors, semiconductors and insulation layers have been widely used, while thin film deposition (Thiri Film Deposition), photolithography, and etching are the main Semiconductor technology. The thin film deposition is to deposit the above materials on the wafer surface in layers, and the lithography process is to replicate the element or circuit pattern that is to be formed. The pattern is transferred to each layer on the surface of the wafer to be formed to form internal semiconductor elements such as transistors or capacitors. In addition, in order to avoid the invasion of water vapor, alkali metal ions, or mechanical scratches, a separate passivating layer must be deposited to protect the aforementioned integrated circuit structure, and it must be defined as input / output (input / The area of the metal pad area used for output), and the protective layer is excavated by the last name engraving step to expose the fresh metal surface before the final packaging work can be performed. It has been confirmed that it is printed by J 'Consumer Cooperative Co., Ltd. ^ However, in the semiconductor devices completed previously, electrostatic discharge (ESD: electrostatic discharge) is often output from the wafer due to contact with electrostatic objects in a dry environment. The intrusion of the I / O pad causes damage to the integrated circuit. Especially after entering the ultra large integrated circuit (ULSI) generation, for example, the semiconductor paper formed by using deep submicron processes below 0.25 μm is suitable for the Chinese paper standard (CNS) A4 (210X297 mm) 463359 Member of the Ministry of Central Standards Bureau __ Consumer Cooperatives printed A7 __________B7_ V. Description of the invention (2) The CMOS ICs' its thin gate oxide, short channel iength, and shallow junction (Shall ow junction) and other structural features, or the application of lightly doped (LDD) and metal silicide diffusion (salicided diffusion) technologies, have seriously weakened the ESD resistance of the transistor 'and affected its reliability against electrostatic discharge. For example, the transistor device described above is extremely sensitive to high voltage discharges because it has a thin gate oxide layer that is easily ruptured. The general electrostatic discharge causes the failure of electronic components can be divided into voltage-type buckle and current-type damage. According to the human body model, high electrostatic voltage may originate from the human body touching the pins of the integrated circuit, which may generate a charge of more than 2000V and It appears in the form of high current pulses for a long period of time; according to the machine model, the static electricity voltage may also come from the integrated circuit pins and poor ground conductors. If the test machine is in contact, it can use a high voltage for a short period of time. A pulse pattern appears. If the electrostatic discharge protection structure is designed according to the human body model, its ESD value needs to be as high as 4000V, and if the electrostatic discharge protection structure is designed according to the machine model, its ESE value is about 500V. The electrostatic discharge protection structure 'is probably based on two types of transistor turn-on mechanism and transistor breakdown_jumpback mechanism'. The transistor turn-on mechanism is based on a thick oxide transistor. The electrode is connected to the output / input pad, so it is characterized by the threshold voltage value of the conduction channel, and the transistor break-back mechanism is connected to the output / input pad with a thin oxide transistor drain. The gate is connected to the source. Therefore, the national standard of CNS > Α4 size (2) 0X 297mm > (Please read the precautions on the back before filling this page) is used for the paper size of the transistor. Standards Bureau Consumer Cooperatives Co., Ltd. 4 6335 9 Α7 __________ B ~ 7 V. Description of the invention (3) ^ The body breakdown voltage value is its characteristic. Take the currently widely used crash_jumpback mechanism as an example, as shown in Figure 1. It is shown that a semiconductor device generally has an internal circuit element area 30 and an output / input pad (I / 〇pad) 10 electrically connected thereto. Among them, an electrostatic discharge protection structure 20 such as an NMOS can be added between the two. Transistor's main function Based on Figure 3, the characteristic curve of the non-polar voltage versus the drain current of an NMOS transistor generally includes a linear region, a saturation region, an avalanche region, and a jump-back region. (Snapback region) and other four stages. When an electrostatic discharge occurs, the electrostatic voltage invaded from the output / input pad 10 will cause the NMOS transistor 20 to break down and directly enter the snapback region to discharge the static electricity. Carry out potential limiting and transition to avoid ESD damage in the internal electrical peak element area 30. In order to further explain its jump-back mechanism, please refer to Figure 2, the electrostatic discharge protection structure 20 usually includes a metal-oxygen half (] ^ 08) power The crystal 'is an NMOS, PMOS, or CMOS transistor, and according to Figure 2', in the case of a P-type grounded NMOS transistor, the gate 21 and source 22 with thin gate oxide layers are both grounded. Therefore, during normal operation, the NMOS transistor 25 is not conductive, and when an electrostatic discharge occurs, the built-in NPN bipolar transistor 26 (bypass) is used to bypass Protect the inside The device element area 30, in which the source N + doped region 22 forms an emitter Ε, and the pole N + doped region 23 forms an annual pole C, and the P-type silicon substrate 24 forms a base B. Since the emitter base The size of the ultra-thin paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210 × 297 mm), clothing -------- II ------ ^ 1 (Please read the precautions on the back before filling this page) Jing Yi Printed by the Central Standards Bureau of the Ministry of Work, Consumers and Consumers Cooperatives 4 633 5 9 A7 __ -__ B7 V. Description of the invention (4) ~~~~ E, B grounded 'When the electrostatic discharge is positive, such as a pair of grounds, the eSd voltage pulse is self-output / When the metal pad 10 penetrates through the drain N + doped region 23, the ESD voltage will trigger the parasitic bipolar transistor 26 to form positive feedback, so the NMOS transistor 25 will break down. Then, it enters the snapback region, and thus conducts a large amount of ESD current to the ground potential node, which causes the breakdown voltage of the NMOS transistor 25 to appear at the node Q ', which is used as an electrostatic discharge. The clamping voltage (ciamp voltage) 〇 In order to make the NMOS transistor can accommodate a large amount of electrostatic discharge current 'But it can avoid the gate structure's longitudinal direction being too long, so the traditional multi-finger structure layout as shown in Figure 4 is generally used. According to the figure, it is a p-type substrate or P An active area 200 is formed in the well area 100, and a multi-parallel MOS device such as 210, 230, and 250 is included in the active area 200. The equivalent circuit diagram is shown in FIG. 5, and each A MOS device is composed of the following structures, such as a source region S formed at a predetermined position of an active region, and a pole region D formed at a position of each active region S relative to the active region; and a gate structure G, They are formed on the surfaces of the active regions between the source regions S and the drain regions D, respectively. Among them, the drain and electrode regions D of each MOS device are adjacent to each other and are electrically connected together, so is the source region s. In addition, the gate structure G and the aforementioned source electrode s pass through the p-type well region 100. The P + contact region 150 is connected to a bias source, such as a ground node Vss, to form a plurality of parallel Mos elements in FIG. 5. The contact with this paper is applicable to the Chinese National Twin (CNS) Λ4 specification (21〇χ29 » (Please read the precautions on the back before filling this page), 1T blow · A7 463359 V. Description of the invention (5) " Window 27〇 is used for the electrical connection of each area or node, so according to the foregoing The principle of the second blue shows that the traditional multi-finger structure uses a plurality of MOS devices connected in parallel and the parasitic double-battery transistor to form the electrostatic protection mode of the collapse-jumpback mechanism. However, in practical applications, because The same design of the length of the same finger electrode structure G has the same value of γ 丨, which does not change with the longitudinal width direction X of the foregoing gate structure. Therefore, a plurality of formed along the longitudinal width direction X of the gate structure For a parasitic bipolar transistor, the length of the base B is uniform. The same (can refer to the relationship between the gate structure and the base length in Figure 2), and this also results in the same current gain coefficient p. As for the base current of each parasitic bipolar transistor, then Due to the difference in distance between each bipolar transistor and the P + contact region 150, the equivalent base resistance value is the smallest at both ends (L, _L), so the relative base current is the largest, and the set generated in the drain region D As a result, the electrode current also increases from the middle 0 (0) to the position (L, -L) at both ends. In this way, when the electrostatic discharge invades the drain D from the output / input pad 10, an uneven distribution of electrostatic current often occurs The problem is, for example, that there is almost no static current flowing near the center of the gate structure in the longitudinal direction, but a large amount of static current is concentrated at both ends (L, -L) and is damaged. In view of this, one of the present inventions The purpose is to select a multi-finger structure in the electrostatic discharge protection circuit when the electrostatic discharge invades. The length of the internal gate structure changes along the width direction. The length of the pole structure is short, while the base is equivalent to Those with lower resistance have a longer gate structure, which is used for paper correction (CNS) A ^ (2107297- ^ ¾) — II____ _ I / _ _____ _ τ II _ I --- Is it 1 -1-5? I (Please read the precautions on the back before filling out this page} Printed by the Ministry of Economic Affairs and the Jujube Bureau J Consumer Information Co., Ltd. Printed by the Ministry of Standards Bureau Consumer Consumption Cooperatives System 4 6335 9 A7 _ — B7 V. Description of the invention (6) Make each parasitic bipolar transistor with different base currents and different current gain β values to form almost a collector current to increase the static current. Uniformity when the drain is diffused. In order to achieve the stated purpose, the present invention provides a multi-finger electrostatic protection structure suitable for a substrate, which includes: a plurality of source regions formed at a predetermined position on the substrate; and a plurality of drain regions formed on the substrate opposite to the substrate. The positions of the source regions; and a plurality of gate structures respectively formed on the substrate surfaces of the source and drain regions to form a plurality of parallel MOS devices, wherein the length of the gate structure is along the gates The polar structure's vertical window 'direction changes. That is, when the base equivalent resistance is higher near the center of the gate structure in the widthwise direction, the gate structure length is better known, and when the base equivalent resistance is lower, it is near the gate structure in the widthwise direction. At both ends, its gate frog pupa is longer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a detailed description is given below in conjunction with the preferred embodiments and the accompanying drawings as follows: Brief description of the drawings: FIG. 1 It is a schematic diagram of internal circuit components that do not traditionally form an electrostatic discharge protection structure. Fig. 2 is a cross-sectional view of a semiconductor showing a conventional electrostatic discharge protection structure using a crash-bounce mechanism. Figure 3 shows the characteristic curve of the transistor in the electrostatic discharge protection structure. Figure 4 shows a conventional multi-finger electrostatic protection structure of a semi-conductive paper with a scale of 1 丨 Count (CNS) Α4 ^ (210X297 ^ 7 '% ---- ^ ----, 1T ---- -^ I (Please read the precautions on the thin back first and then fill out this page) 4 6335 9 A7 A · ™ —— -------- B7 "V. Description of the invention (7) — ~ ^ Body layout. Figure 5 is a schematic diagram of the conventional equivalent circuit of Figure 4. (#Read the precautions on the back before filling this page) Figure 6 is the traditional semiconductor layout of Figure 4 and the traditional equivalent circuit of Figure 5 The electrical connection relationship of each bipolar transistor is shown in Fig. 7. Fig. 7 is a semiconductor layout diagram of a multi-finger electrostatic protection structure according to an embodiment of the present invention. ^ Fig. 8 shows the multi-finger pattern of Fig. 7 In the semiconductor layout of the electrostatic protection structure, the electrical connection relationship of each bipolar transistor is shown in the following figure: 10 ~ output / input pad; 20 ~ electrostatic discharge protection structure 2 丨 ~ gate structure; 22 ~ source; 23 ~ Drain; 24 ~ Substrate; 25 ~ NMOS transistor; 26 ~ Parasitic bipolar transistor; 30 ~ Internal circuit element area; 100 ~ P-type well area; 150 ~ P + Contact area; 200 ~ active area; 210, 230, 250 ~ MOS device; 210 ', 23, 25, 250 ~~ MOS device; R1, R2 ~ equivalent resistance; R ~ base resistance; Ic , Ic, ~ collector current; lb ~ base current; β, β, ~ current gain; τ ~ parasitic bipolar transistor; 270 ~ contact window. To facilitate comparison, 'the mechanism of FIG. 6 will be described before explaining this embodiment' to show the difference and improvement of the embodiment of the present invention and the traditional multi-finger structure. Please refer to FIG. 6, which represents the first In the conventional semiconductor layout of Fig. 4 and the conventional equivalent circuit of Fig. 5, the electrical connection relationship of each bipolar transistor is first. According to Fig. 4, the MOS device 210 is taken as an example. Science- (CNS) Λ4 specification Uioxw7 mm) 463359 Ministry of Economy and Trade Cooperative Industry Cooperative and Printing Co., Ltd. A7 V. Description of the invention (8) 'NMOS transistor on p-type substrate, N-type substrate PMOS transistor, or CMOS transistor in double-well structure. Take NMOS as its buckle The gate structure G is arranged on the active area 200 along the longitudinal width direction (x, -x). '(0) near the center, and (L, _l)' near the P + contact area 1 50 As for the length, it is γι value, so for a plurality of parasitic bipolar transistors formed along the longitudinal width direction of the gate structure, the base B lengths are the same, and this also results in the same current Gain coefficient β (current gain). Among them, 'According to the finger gate structure G along the longitudinal width (χ, _χ) section line I-I', the active area below the gate structure G changes with the position A plurality of parasitic bipolar transistors are formed. As shown in FIG. 6, in the collector c ', when the electrostatic discharge current IESD enters the drain region D of the NMOS element 210 from the input / input pad 10, it flows into each The parasitic bipolar transistor T (-L) ... T (0), ... D (χ), T (x + dx) ... T (L), the collector C 'in the emitter E' The carrier transistor is electrically connected to the source ground node vss of the MOS device, and the p-type 丼 region or substrate is also grounded through the P + contact region. At this time, at the base B of each bipolar transistor T (-L) ...... T (0), ... T (X), T (x + dx) ... T (L) On the path from the substrate to the ground node Vss, base resistances R (-L) ..., R (0), ... T (x), R (x + dx) ... R (L) are formed respectively. Formed by the equivalent resistance Ri and the equivalent resistance R2 of different numbers in series. Take parasitic bipolar transistors T (x), ... T (x + dx) ..., T (L) as examples. The larger the distance between the carrier transistor and the ground P + contact area 150, the number of its respective series resistance R2. The paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X29 :; mm) --------- Stupid ------- Order ------ ^ 1 (please read the note ^^^ on the back before filling this page) 4 633 5 9繁 A7 B7 V. Description of the invention (9) The more the quantity is, it can be seen that the base resistance value R (x) seen from the base B is the largest near the center position (X), and the illusion of the base current is the smallest. Conversely, with the position far away from the center, such as the transistor T (x + dx) at (X + (JX) ', its series equivalent base resistance R (x + dx) seen from the base B Gradually decrease 'relative base current ib (x + dx) gradually increases until the minimum series equivalent base resistance R (-L), R (L) is obtained at the two ends (L, -L), so the relative base current ib (L ) Max. Because in each parasitic bipolar transistor T (_Ly τ (〇), τ (χ), T (x + dx) .... T (L) '; and the collector current generated by the polar region d Is equal to the product of the base current and the current gain coefficient β (Ic = px Ib), so the obtained collector current Ic (-L) ... Ic (0) ”.. Ic (x), Ic (x + dx) ... Ic (L), which increases from about the center (0) to the positions (L, -L) at both ends, as shown in Table 1. Table 1 Base resistance R (-L) <, ... < R (〇) > _ > R (x) > R (x + dxy > Base current lb Ib (-L) > ~ > Ib (〇) < — < Ib (x ) < Ib (x + dx)?; .. < IbfL) Current gain β P (-L) —... = β (〇) =. ,,: = β (χ) = p (x + dx)… = β (χ, collector current Ic Ic (-L) > ... > le (〇) < ... < ic⑻ < ic (x + dx) < Ic (X) 'Traditional structure is because the gate structure of each MOS transistor has the same length', so for a plurality of parasitic bipolar transistors formed along the longitudinal width direction X of the gate structure, its The length of the base B is also the same 'so that the same current gain coefficient β value (current gain) can be obtained' and the difference between the distance between each bipolar transistor and the ρ + contact area 15 ° results in an equivalent base The resistance value is at the end of the two positions (L, _L) at the most 10 paper-scale postal materials (CNS) Λ4 ^ (public wide)----------- 衣 --------- Order- ----- 气 | {Please read the notes on the back before filling in this page) 4b 33 5 9 A7 ^ ________ B7 V. Description of the invention (w) is small, so the relative base current is the largest, which is generated in the drain region D As a result, the collector current also increases from the center (0) to the positions (L, _L) at both ends, so that when the electrostatic discharge invades the drain electrode 0 from the output / input pad 10, uneven static current distribution often occurs. Problem. Accordingly, please refer to FIG. 7, which shows a semiconductor layout of a multi-finger electrostatic protection structure according to an embodiment of the present invention. First, this figure uses MOS elements 210 ', 230, and 250 connected in parallel as an example. The finger gate structure G' is arranged on the active area 200 'near the center in the longitudinal width direction (χ, · χ). Is (0) 'and (L, -L)' near the two ends near ρ + contact area 150, and according to the finger gate structure G 'in the longitudinal width direction (X, -X) section Π -Π '' The active region 200 below its gate structure G 'forms a plurality of parasitic bipolar transistor with the change of position. As for the length, it has a narrower Y1 value and a gradually wider Y2 value. It is the biggest difference from the traditional structure '. Therefore, for a plurality of parasitic bipolar transistors formed along the longitudinal width direction X of the gate structure, the length of the base B also changes, which also results in Each of them has a different current gain coefficient β '(current gain), so the value of β is the largest β' (χ) near the center position (X), and conversely, as the position farther from the center, as in The transistor T (x + dx) at (x + dx), its current gain β '(χ + < 1χ) value gradually decreases, until the two ends (L, -L), can get the smallest Current gain β ′ (· Ι〇, β ′ (ί). In addition, please refer to FIG. 8, when the electrostatic discharge current Iesd enters the drain region D from the output / input 10, it will flow into each bipolar transistor separately. Ding (-1 ^ .. 1 '(0), ... 1' (乂), 1 '(\ + £ 1 \ 1 .. Ding (1 ^ in the collector (:, read in radio read first) Note on the back, please fill in this page again) Printed by the Central Bureau of Standards of the Ministry of Commerce and Industry (CNS) (21 OX 297- ^ ¾) A7 4 6 33 5 9 —___ B7_ V. Description of the Invention (11) ~ In the aspect of the pole E, each of the bipolar transistors t (-L) ... T⑼ ,, .ίΤ (T (x + dx) "., T (L) is electrically connected to the MOS device The source ground node Vss 'and the P-type well area or substrate is also grounded through the P + contact area. Therefore,' at each bipolar transistor T (_L) ... T⑼, τ (χ) 5 T (x + dx) ... The base B of T (L) passes through the substrate to the ground node yss. 'Base resistors R (_L) ..., R⑼ R (x + dx) ... R (L)' are formed near the center.最大 is the largest, and the relative base current Ib (x) is the smallest. Conversely, as it moves away from the center, its series equivalent base resistance R (x + dx) gradually decreases, and the relative base current Ib (x) x + dx) gradually increase; until the two ends (L, _L), the minimum series equivalent base resistance r (_l), r (l) can be obtained, so the relative base current Ib (L) is the largest. The reason is that in each parasitic bipolar transistor T (-L) ... T (0), ..T (χ), T (x + dx) ... T (L), the drain region D is generated The collector current 'is equal to the product of the base current and the current gain coefficient β' (Ic '= p'x lb)'. Therefore, by adjusting the current gain coefficient β described above, the obtained collector current Ic '(-L) ... lc '(0), ... lc' (x), Ic '(x + dx). ", Ic' (L), the distance relationship with the gate structure in the widthwise direction is shown in Table 2 As shown. Table 2 Base resistance R (-L) < ... < R (〇) > ... > R (x) > R (x + dx) ... > R (L) base Pole current lb Ib (-L) > ... > lb (0) < ... < Ib (x) < Ib (x + dx) ... < Ib (L) current gain p 'β' (-ί) < .. · < β, (〇) <… < p, (x) < p, (x + dxy “< p '(L) collector current Ic' .. = 10 ^ 0) = .. .Hc ^ xHc ^ x + dx) ... = 101 (L) 12 This paper size is applicable to China National Standard Soap (CNS) Λ4 grid (210X29? Mm)- --------- h II ^. 丁--nnn -Order, 1 ^, V6 A (谙 Please read the precautions on the back before filling in this page) Printed by the cooperative ^ Consumer Ministry * Standard ^-Bureau of Work and Consumer Consumption & Co., Ltd.% A7 Β7 V. Description of the invention (12) '—— ----- From Table 2, we can see' When electrostatic discharge invades, In the electrostatic discharge protection circuit, a multi-finger structure is selected. The internal closed-electrode structure length of the electrostatic discharge protection circuit changes along the width direction. When the base electrode is equivalent to electricity, if the business person is close to the width of the electrode structure, In the center of the direction, the length of the pole structure is shorter, and when the equivalent resistance of the base is lower, The gate structure length is longer at both ends in the widthwise direction of the closed-pole structure. In this way, each parasitic bipolar transistor has different base currents and different current gains β [to form the same collector current ' That is, the uniformity of the electrostatic current diffusion in the drain electrodes of the MOS devices is increased, so that the parasitic bipolar transistor in the multi-finger electrostatic protection structure is uniformly conducted without causing damage due to the concentration at the two ends. The material materials used in the invention are not limited to those described in the embodiments, they can be replaced by various materials and forming methods with appropriate characteristics, and the structural space of the present invention is not limited to the dimensions cited in the embodiments. The present invention has been disclosed in a preferred embodiment as follows, but it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. 1 3 1: The paper size is appropriate (CNS) Tiege (21Qx 297). (Please read the notes on the back first (Please fill this page again)