TW463323B - Manufacturing method for self-aligned node contact - Google Patents

Abstract

The present invention provides a manufacturing method for self-aligned node contact on a semiconductor chip in which the semiconductor chip comprises a substrate, a dielectric and a first and a second bit lines. The first side of the first bit line is adjacent to the second side of the second bit line and the first side a first section and two neighbored second sections. The distance between the two second sections and the second side is smaller than the predetermined value. The inventive manufacturing method includes the following steps: first, forming a second insulation layer on the dielectric and the two bit lines and the second insulation will form a slot in the gap between the first section and the second side; then, conducting a first anisotropic etching process so as to make the bottom of the slot between the first section and the second side passing down to the surface of the dielectric in which the remaining second insulation layer on the perimeter of the slot will form a spacer and the remaining second insulation layer in the gap between the two second sections and the second side will still completely cover the surface of the two gaps; finally, conducting a second anisotropic etching process to vertically remove the dielectric at the bottom of the slot until the substrate surface so as to form the node contact.

Description

463323 V. Description of the invention (1) On-chip point contact hole (η 〇 d e) is a method for making a hole in a stacked dynamic access memory (MAM). A memory cell contains a capacitor on a crystal. Stacked DRAM is set to control a bit line. To read the lower electrode, the electrode needs to be formed on a conductive object as an electrical connection line to design the electrical pattern. Because the contact hole will have two bit lines The gap is narrowed, and it is easy to cause short data loss with the bit lines around it. How to make a capacitor and make the conductive object in the contact hole have a relationship with its periphery is a method in the semiconductor manufacturing process that recreates the invention as a semiconductor crystal contact, especially the electrical connection of the electrodes under the state memory (dynamicrand 0m capacitor) The memory of a stacked DRAM transistor and *-a stack of electricity. The ten principle is to use the transistor as the data stored in the capacitor. And the crystal in the node contact is electrically connected. In the semiconductor The chip crosses the gap between the two bit lines. As the conductive material in the contact hole becomes more capacity, which leads to the contact hole for the electrical connection of the I electrode stored in the capacitor, the bit line has a problem of good insulation. See May 1st, 5th, and 2nd. The sound diagram of the isi production method: 2 ;: to FIG. 6 are top views of the conventional point contact holes 48, and FIG .: The same is the semiconductor wafer of the known production method 10 cross-section diagram = is the semiconductor wafer shown in Figure 1 along the tangent line aa is the semiconductor wafer shown in Figure 1 along the tangent line W Figure 4 stem: Main 1 Figure 4 is a conventional point contact hole 48 Top view, Fig. 5 is a schematic cross-sectional view of the + conductor chip 10 along the tangent line c ~ c, Fig. 6

4633 2 3

V. Description of the invention (2) A schematic cross-sectional view of the semiconductor wafer 10 along the tangent line d-d shown in FIG. 4. The manufacturing method of the conventional point contact hole 48 is performed on a semiconductor wafer. As shown in FIGS. 1 to 3, the semiconductor wafer 10 includes a substrate 12, a dielectric layer 14, a first bit line 6 and a second bit line 18. The crossing surfaces of the first and second bit lines 16 and 18 are approximately square, and the two sides are two approximately vertical sides. The first side of the first bit line 16 includes a first section 5 and two second sections 7 adjacent to the first section 15, and is respectively connected to the second bit line 1 8 The second side edges 19 are adjacent. The distance d1 between the first section 5 and the second side 9 is larger than a predetermined value, and the distance d2 between the second section 7 and the second side 8 is smaller than a predetermined value. The conventional method for making the point contact holes 48 is to form a second dielectric layer (not shown) on the vertical sidewalls of the first and second bit lines 16 and 18, and surround the first in a circular manner. And the vertical side walls of the second bit line 6 and 18 are used as a side wall 30. Since the distance d 1 between the first segment 15 of the first bit line 16 and the second side 19 of the second bit line 18 is larger, the first segment 16 of the first bit line 16 1 7 The distance d 2 between the second bit 19 of the first bit line 18 and the second bit 19 is small. Therefore, there will be a gap between the first section 15 and the second side 19 2 side wall 30. A groove 32 ′ having a relatively large opening, and a groove 34 having a larger aspect ratio will be formed between the second section 17 and the second side wall 19 30. As shown in Figures 4 to 6, a third dielectric layer 40 'is then formed on the semiconductor wafer so that the groove 32 is filled with the third dielectric layer 40. Then a yellow light process is performed to form a photoresist layer (not shown), and a hole is formed in the photoresist layer

463323 V. Description of the invention (3) Hole 'can be used to define the point where the point touches the hole. Then, an anisotropic dry-relief process is performed to vertically remove the third dielectric layer 40 and the first dielectric layer 14 to the substrate 12 under the hole of the photoresist layer under the condition that the sidewall member 30 is almost not removed. Surface 'to form a little contact hole 48. Finally, the photoresist layer is removed, and the entire point contact hole 48 is completed. When the third dielectric layer 40 is formed, because the aspect ratio of the trench 34 is too large, the third dielectric layer 40 cannot be completely filled therein. Therefore, in the second section 17 and the second side 19, An empty pipe 42 will be formed between the two side walls 30. Please refer to FIGS. 7 to 9, which are schematic diagrams of a polycrystalline silicon layer 50 formed in a conventional point contact hole 48. FIG. 7 is a top view of a polycrystalline silicon layer 50 formed in the point contact hole 48 of FIG. 9. FIG. 8 is a schematic cross-sectional view of the semiconductor wafer 10 shown in FIG. 7 along a tangent line ee. A schematic cross-sectional view of the semiconductor wafer 10 is taken along the tangent line ff. After the point contact hole 48 is fabricated, a polycrystalline silicon layer 50 can be formed in the point contact hole 48, which can be used as an electrical connection line to electrically connect the transistor of the semiconductor wafer 10 and the capacitor lower electrode to be manufactured later. When a polycrystalline silicon layer 50 is formed in the point contact hole 48, since the point contact hole 48 is connected to the empty tube 42 under the third dielectric layer 40, a polycrystalline silicon layer 50 is also easily formed in the empty tube 42. The polycrystalline silicon layer 50 formed therein will cause a leakage path between the capacitors to be electrically connected in the future. As shown in Fig. 7, arrow 52 indicates the direction of the leakage path. The manufacturing method of the point contact hole 4 8 will be generated by the empty tube 4 2, and the point

4 633 2 3 -7ΰ m bu_ Wj_ V. Description of the Invention (4) When a polycrystalline silicon layer 50 is formed in the contact hole 48, the polycrystalline silicon layer 50 is also easily formed in the empty tube 42. Although the point contact hole 48 is surrounded by a dielectric layer 14 so that the polycrystalline stone layer 50 can have a good insulation relationship with the first and second bit lines 16 and 18, the empty tube 4 2 The internal polycrystalline silicon layer 50 will cause leakage paths between the capacitors, which will cause the amount of charge stored in the capacitor to change and lose the stored data. Therefore, the main object of the present invention is to provide a method for making self-aligning point contact holes, so that the polycrystalline silicon layer formed in the point contact holes can have a good insulation relationship with the first and second bit lines to avoid capacitance. Leakage paths are created between each other. Brief description of the diagrams Figures 1 to 6 are schematic diagrams of a method for manufacturing a conventional point contact hole. Figures 7 to 9 are schematic diagrams of a polycrystalline silicon layer formed in a conventional point contact hole. Fig. 10 is a top view of a semiconductor wafer used in the method for manufacturing a point contact hole according to the present invention. Fig. 11 is a schematic cross-sectional view of the semiconductor wafer shown in Fig. 10 along a tangent line g-g. Fig. 12 is a schematic cross-sectional view of the semiconductor wafer shown in Fig. 10 along a tangent line h-h. Figures 13 to 16 are schematic diagrams showing the manufacturing process of the method for manufacturing a point contact hole according to the present invention.

463323 V. Description of the invention (5) FIG. 17 is a schematic diagram of a point contact hole of a semiconductor wafer of the present invention. FIG. 18 is a schematic cross-sectional view of the semiconductor wafer shown in FIG. 17 along a tangent line i-i. FIG. 19 is a top view of a polycrystalline stone layer formed in the point contact hole shown in FIG. Fig. 20 is a schematic cross-sectional view of the semiconductor wafer shown in Fig. 19 along a tangent line k-k. FIG. 21 is a schematic cross-sectional view of the semiconductor wafer shown in FIG. 19 along a tangent line m-m. 62 Substrate 6 6 First bit line 7 0 Polycrystalline silicon layer 7 4 Symbol description of the first insulating layer illustration 60 Semiconductor chip 64 Dielectric layer 6 8 Second bit line 7 2 Tungsten silicide layer 7 8 Second bit The second side of the line 80 the first section 82 the second section 8 4 the second insulating layer 8 6 the groove 8 8 the side wall 9 0 point contact holes, please refer to FIG. 10 to FIG. A top view of a semiconductor wafer 60 that invents a method for manufacturing a contact hole. FIG. 11 is a schematic cross-sectional view of the semiconductor wafer 60 shown in FIG. 10 along a tangent line g-g, and FIG. Schematic sectional view along the tangent line h -h. The present invention

463323 V. Description of the invention (6) Fabrication of the positive point contact hole 90 The semiconductor wafer 60 includes a layer 64 provided on the substrate 62 and a dielectric layer 64 provided. A first electrical layer 73 is provided on the dielectric layer 64. A layer 74 is provided on the conductive layer 73. On the dielectric layer 64, a side which is approximately perpendicular to the second bit line 66, 68 is located on the second layer which includes a first segment 80 and a second bit line 68. A segment 8 0 and a first distance dl are greater than a predetermined value, and a value of segment 8 2 and a second bit line 68 of 0 are both sides of oxygen. One of the first side edges 66 of the first bit line 66 and two adjacent second sides 78 are adjacent. The method between the second bit line 6 8 and the second bit line 7 6 of the first bit line 6 6 is to conduct the base 6 2 with the first bit line 6 6 and the second bit line 6 6, and A nitride conductive layer 73 containing a tungsten carbide layer 72 is provided on the wafer 60 with a plurality of lateral load-bearing surfaces. The dielectric formed by the fossil evening and a second bit line 6 8, 68 each include a first insulation made of conductive silicon. A polycrystalline silicon layer 70 is disposed on the crystalline silicon layer 70. The first square includes two sections 8 2 and the distance d2 between the second side of the first side and the second side 78 of the one-bit line 66 is smaller than the predetermined value. Please refer to FIG. 10 Second rm point contact hole production square diagram: three to sixteen for the present invention! 'Before the dielectric layer' and the first and second bit lines 66, 68 of ee Yudi-#lice 彳 ΪSi The second insulating layer 84 constituted by the first bit line =: two due to the second insulating layer 84 of the first section 80 and the second side 78! I]; 82; the distance d2 'and dl> d2 'So the gap is so full: the second section 82 is between the second side and the second side, and the first section is between 80 and the second side.

4 6 33 2 3 V. Description of the invention (7) ---- The gap is formed—the groove 8 6 ′ is shown in FIG. 13. f-The first anisotropic etching process is performed to completely remove the second insulating layer 84 above the first and first bit lines 66 and 68 and pass the bottom side of the groove 8β down to the dielectric layer 64. surface. The second insulating layer 84 remaining on the periphery of the groove 86 will form a side wall (s pace ^ 88, which is used to cover and isolate the conductive layers in the first and second bit lines 66 and 68 located on the periphery of the groove 86. 73 'as shown in Figure 15. The second insulating layer 34 remaining in the gap between the second section 82 and the second side edge 78 will still completely cover the surface of the two gaps, as shown in Figure 16. _ Then define an array area (not shown) on the surface of the semiconductor wafer 60 to make a plurality of DRAM memory cells (memry ceU). The first and second bit lines 6 6 and 6 8 and the gap between them are located in the array area. Then a yellow light process is performed to form a photoresist layer (not shown) on a predetermined area outside the array area on the surface of the semiconductor wafer 60 to protect the semiconductor in the predetermined area. The surface of the wafer 60 to avoid damage by subsequent etching processes. Refer to FIG. 17 and FIG. 18 'FIG. 17 is a schematic diagram of a point contact hole 90 of the semiconductor wafer 60 of the present invention' ® 18 is a semiconductor wafer of FIG. 17 6 〇 A schematic cross-sectional view taken along the tangent line 1-:. The directional etching process uses the first insulating layer 74 and the remaining second insulating layer M as a hard mask (Chard mask), and vertically removes the dielectric layer located on the bottom side of the groove 86 "to the surface of the substrate 62 to form a point Contact hole 90. Finally, a removal of light

4 633 2 3 5 'Explanation of the invention (8) ^ Resistive layer process' will complete the self-aligning point contact hole 9 of the present invention. When anisotropic etching is used to form the point contact hole 90, the position of the point contact hole 90 will be aligned with the first segment 8 0 and the second bit of the first side of the first bit line 66. The middle position of the gap of the second side edge 78 of the line 68 is formed on the bottom side of the groove 86, so the point contact hole 9o will not be too close to the peripheral bit line. As for the gap between the second section 82 of the first side and the second side 78 of the second bit line 68, the second insulating layer 84 is used as a hard mask and is not affected by the etching. The cross-sectional view of the wafer 60 along the tangent line j_] · is still shown in circle 16. Please refer to Figure 19 to Figure 21. FIG. 19 is a top view of the polycrystalline silicon layer 92 formed in the point contact hole 90 shown in FIG. 17, and FIG. 20 is a schematic diagram of the facet of the semiconductor wafer 6 shown in FIG. 19 along the tangent line k-k. FIG. 21 is a schematic cross-sectional view of the semiconductor wafer 60 shown in FIG. 19 along a tangent line mm. After the point contact hole 90 is fabricated, a polycrystalline silicon layer 92 can be formed in the point contact hole g q as an electrical connection line for electrically connecting the transistor of the semiconductor wafer 60 and the capacitor lower electrode to be produced later. In the method for manufacturing the point contact hole 90 of the present invention, since the position of the point contact hole 90 is aligned on its own, there is no need for a very precise photoresist layer to define 'that is, the tolerance of the misalignment of the photoresist layer can be tolerated. (mis-alignment tolerance) is larger, so the entire process will be smoother, which will improve the yield of semiconductor products. In addition, since the second insulating layer 84 completely fills the gap between the second section 82 and the second side 78,

笫 Page 12 4 633 2 3 V. Description of the invention (9) The polycrystalline silicon layer 92 cannot be formed therein, so the polycrystalline silicon layer 5 is formed. It can be related to the first and second bit lines 66, 6 =: as many as 90. The capacitors do not generate leakage paths between each other. They have good insulation and a stable amount of charge to maintain the stored data.彳 Compared with the conventional point contact hole 90, the second insulating layer 8 4 is formed in the capacitor. The two insulating layers 84 of the line 6 6 and the second bit line 6 8 are used as a hard mask. The position of 90 can align the segment 80 and the second bit line 68 by itself. The electrical connection of the bit lines 66 and 68 of the capacitor's lower electrode in the point contact hole 90 of the present invention has a good leakage path and electrical memory. data of. The method of making the hole 48 is to make the second insulation gap, and then use the first insulation method. The first and second edge layers 84 are completely formed to form a multi-line, poly-crystal formed on the second side of the first position. The memory point contact hole in the insulation capacitor is the gap between the 80th side of the element line 66 and the 7th side. The crystalline silicon layer 50 can be connected to the silicon layer 50. Therefore, the self-aligned bit lines 66 and 68 invented by the amount of electrical charge fill the first The one-bit margin layer 74 and the first middle position of the 'point contact point-side'. Making the memory unit and the first volume are not stable with each other to keep them. So the above is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application of the present invention shall belong to the patent of the present invention. , Letter cover range. '

4 6 33 2 3 _ ^ year ^ sundial correction / correction / replenishment simple illustration of the diagram simple illustration of the diagram Figures 1 to 6 are schematic diagrams of the method for making a conventional point contact hole. Figures 7 to 9 are schematic views of a polycrystalline silicon layer formed in a conventional point contact hole. Fig. 10 is a top view of a semiconductor wafer used in the method of manufacturing a contact hole of the present invention. FIG. 11 is a schematic cross-sectional view of the semiconductor wafer shown in FIG. 10 taken along the tangent line g-g. Fig. 12 is a schematic cross-sectional view of the semiconductor wafer shown in Fig. 10 taken along a tangent line h-h. 13 to 16 are schematic diagrams showing the manufacturing process of the method for manufacturing a point contact hole according to the present invention. FIG. 17 is a schematic diagram of a point contact hole of a semiconductor wafer according to the present invention. FIG. 18 is a schematic cross-sectional view of the semiconductor wafer shown in FIG. 17 along a tangent line i-i. ^ Figure 19 is a top view of a polycrystalline silicon layer formed in the point contact hole shown in Figure 17. FIG. 20 is a schematic cross-sectional view of the semiconductor wafer shown in FIG. 19 along a tangent line k-k. FIG. 21 is a schematic cross-sectional view of the semiconductor wafer shown in FIG. 19 along a tangent line m-m. Symbol description

Page 14 463323 Simple explanation of 60-type semiconductor chip 6 2 substrate 64 dielectric layer 66 bit line 68 second bit line 70 polycrystalline silicon layer 72 tungsten silicide layer 74 first insulating layer 78 second side of second bit line Edge 80 First section 82 Second section 84 First --- Insulating layer 86 Groove 88 Side wall 90 point contact hole

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Claims (1)

463323 fa July 7th repair / soldier / transfer 6. Application scope 1. A method for making a node contact on a semiconductor wafer, the semiconductor wafer includes: a substrate; a dielectric layer On the substrate; and first and second bit lines on the dielectric layer, each bit line includes two approximately vertical sides on both sides, and each bit line The cross section is approximately square, and contains a conductive layer disposed on the dielectric layer and a first insulating layer disposed on the conductive layer, wherein a first side of one of the first bit lines is connected to the One of the second bit lines has a second side edge adjacent to each other. The first side edge includes a first section and two adjacent second sections. The distance between the first section and the second side edge. Is greater than a predetermined value, and the distance between the two second sections and the second side is less than the predetermined value; the manufacturing method includes: forming a second insulating layer on the dielectric layer and the two bits Above the element line, the second insulating layer will completely fill the gap between the two second sections and the second side. A gap, and forming a groove in the gap between the first section and the second side; performing a first anisotropic etching process to completely remove the second insulating layer above the bit line And let the bottom side of the groove between the first section and the second side pass down to the surface of the dielectric layer, wherein the second insulating layer remaining around the groove will form a side wall (spacer) is used to cover and 'isolate the conductive layer inside the two-bit line around the groove, and remains in the two second sections and the second side Page 16 463323 6. The second insulating layer in the gap between the scope of the patent application will still completely cover the surfaces of the two gaps; and a second anisotropic etching process is performed to vertically remove the bottom side of the κ groove The dielectric layer reaches the surface of the substrate to form the point contact hole. 2. The method according to item 1 of the patent application scope, wherein the semiconductor chip includes an array area for making a plurality of dynamic memory (DRAM) memory cells (mem ryce 1 1), and the two bits The lines and the gaps between them are located in the array area. 3. The method according to item 2 of the scope of patent application, wherein before the second anisotropic last name engraving process is performed, the method further includes a yellow light process for a predetermined area on the surface of the semiconductor wafer outside the array area A photoresist layer is formed thereon to prevent the second anisotropic etching process from invading the surface of the semiconductor wafer in the predetermined area. 4. The method of claim 1 in which the dielectric layer is formed by oxidation. 5. The method of claim 1, wherein the conductive layer includes a polycrystalline silicon layer disposed on the dielectric layer, and a tungsten silicide layer is disposed on the polycrystalline silicon layer. 6. The method described in the first paragraph of ^^ _ item_1 ^, wherein the first insulating layer and the Page 463323 Page 18