461046 A7 ___.6Q02twfifinr/fin8--— 五、發明說明（ί ) (請先閱讀背面之注意事項再填寫本頁) 本發明是有關於一種感測器之結構與其製造方法，且特 別是有關於一種主動式光二極體互補式金氧半影像感測器 (Photodiode CMOS Image Sensor)之結構與其製造方法。 光二極體影像感測器是目前常見的一種影像感測元 件。典型的光二極體影像感測器，至少包括一個重置電晶 體(Reset Transistor)以及一個二極體所形成的光感測區。以 η型摻雜區、p型基體(n+/p)所形成之’二極體作爲感光區域 爲例，光二極體影像感測器在操作時係在重置電晶體的閘 極施加一電壓，使重置電晶體開啓後，對n+/p二極體接面 電容充電。當充電到一高電位之後，關掉重置電晶體，使 n+/p二極體產生逆偏而形成空乏區。當光照射在此n+/p二 極體感光區時，產生的電子電洞對會被空乏區的電場分 開，使電子往η型摻雜區移動，而使η型摻雜區的電位降 低，至於電洞則會往Ρ型基體流走。若此時以一個電晶體 把η型摻雜區的電子傳到輸出端(Bus Line)，使照光所產生 的電荷直接傳到輸出端進行讀取，而沒有經由任何的放大 元件，此種光感測器則是所謂的被動式光二極體影像感測 器(Passive Pixel Photodiode)。若η型慘雜區接到一個傳送 經濟部智慧財產局員工消費合作社印製 電晶體(Transfer Transistor)所形成的源極隨鍋器(Source461046 A7 ___. 6Q02twfifinr / fin8 --- 5. Description of the invention (ί) (Please read the notes on the back before filling out this page) The present invention relates to the structure of a sensor and its manufacturing method, and in particular to A structure of an active photodiode complementary metal-oxide-semiconductor image sensor (Photodiode CMOS Image Sensor) and a manufacturing method thereof. Photodiode image sensor is a common image sensing element. A typical photodiode image sensor includes at least one Reset Transistor and a photodiode formed by a diode. Taking the 'diode' formed by the n-type doped region and the p-type substrate (n + / p) as an example of the photosensitive region, the photodiode image sensor is operated to apply a voltage to the gate of the reset transistor during operation. After the reset transistor is turned on, the n + / p diode junction capacitor is charged. When charged to a high potential, the reset transistor is turned off, so that the n + / p diodes are reverse biased and empty regions are formed. When light is irradiated to the n + / p diode photosensitive region, the generated electron hole pair will be separated by the electric field in the empty region, causing the electrons to move to the n-type doped region, and the potential of the n-type doped region is reduced. As for the hole, it will flow away to the P-type substrate. If at this time an electron is used to pass the electrons of the n-type doped region to the output terminal (Bus Line), the charge generated by the light is directly transmitted to the output terminal for reading without passing through any amplification element. The sensor is a so-called passive pixel photodiode. If the η-type miscellaneous area receives a transmission, a source transistor formed by a printed transistor (Transfer Transistor) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs.
Follower)，則可以利用源極隨耦器所提供的大電流，快速 地對輸出端充放電，使輸出端的電壓穩定，雜訊較小’此 種光感測器則爲所泛稱的主動式光二極體感測器(Active Pixel Photodiode)。 近年來在許多低價位影像感測器的應用上，主動式光 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 61 〇46 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（π) 二極體互補式金氧半影像感測器已成爲電荷耦合元件 (Chaise Coupled Device，CCD)的替代品。由於主動式光二 極體互補式金氧影像感測器具有高量子率（Quantum Efficiency)、低 g買出雜訊.(Read Noise)、高動態範圍（Dynamic Range)以及隨機存取（Random Access)等特性，而且與互補 式金氧半導體（CMOS)元件的製程具有百分之百的相容 性’因此可以很容易地將其與其他的控制電路、類比轉數 位電路(A/D Converter)以及數位訊號處理電路整合在同一 片晶片之上，達到所謂的系統單一晶片（System On a Chip， soc)。執是之故，主動式光二極體互補式金氧半影像感測 器是未來發展影像感測器的一種趨勢。 請參照第1圖，習知一種主動式光二極體互補式金氧 半感測器的製造方法係在基體100中形成隔離區102，之 後，在基體100上沉積一層氧化層與複晶矽層，然後，經 由微影與蝕刻技術，定義氧化層與複晶矽層，以形成重置胃 電晶體120的閘極氧化層104以及複晶矽閘極106。接著， 以隔離區102以及複晶矽閘極106作爲植入罩幕，利用離 子植入與熱驅入製程，在基體1〇〇中形成源極/汲極區108 及二極體感光區110的摻雜區112。其後，再於複晶矽閘極 106以及閘極氧化層104的側壁形成間隙壁114。 典型的互補式金氧半電晶體標準製程中，尙包括一道 自動對準金屬化製程（Self-Aligned Silicide，Salicide)，以在 複晶矽閘極106以及源極/汲極108上形成金屬矽化物，用 以降低元件的阻値。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ill----------- 裝----！— 訂---------/T .( 、：'L {請先閱讀背面之注意事項再填寫本頁) S 4 1 04 6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（々） 但是，當上所述之典型的互補式金氧半電晶體標準製 程應用於主動式光二極體互補式金氧半影像感測器的製作 時，二極體感光區110在施行自動對準金屬化製程之後亦 會如同複晶矽閘極124以及源極/汲極106 —樣形成金屬矽 化物。覆蓋金屬矽化物的二極體感光區110，將造成入射光 大量反射，而使得光電轉移效率大幅降低，影響整個‘感測 器的靈敏度。 此外，二極體感光區110表面的界面態（Interface State) 存在著許多的缺陷，因此，當光照射在此n+/p二極體感光 區110時，所產生的電子電洞對被空乏區的電場分開的過 程中，將因爲界面態的缺陷而導致表面漏電流。 因此，本發明之目的就是在提供一種主動式光二極體 互補式金氧半影像感測器之結構，以避免元件的漏電流現 象。 本發明之目的就是在提供一種主動式光二極體互補式 金氧半影像感測器之結構，可以增加光電轉移效率，提舁 整個感測器的靈敏度。 本發明提出一種主動式光二極體互補式金氧半影像感 測器’包括一二極體感光區、一電晶體與一覆蓋層，其中’ 二極體感光區係位於基體之中，電晶體係配置於基體上’ 且電晶體的源極區與部分的二極體感光區連接，覆蓋餍係 以形成閘極介電層的方式所形成者，其配置於二極體感光 區之上。 本發明提出一種製作上述之主動式光二極體互補式金 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------、 f--------訂---------線、 ( /, (請先閲讀背面之注意事項再填寫本頁) 4 6 104 6 經濟部智慧財產局員工消費合作社印製 Α7. Β7 五、發明說明（$ ) 氧半影像感測器的製造方法，其方法係在基體上形成一層 閘極介電層、一層閘極導體層與一層頂蓋層，之後，以微 影與蝕刻技術定義之，以形成一閘極結構。然後，先進行 離子植入步驟，再施行熱驅入與熱氧化製程，以在基體中 形成源極/汲極區以及二極體感光區的摻雜區，並在所裸露 的基體表面上形成一層覆蓋層。其後，去除部分的覆蓋層， 以留下二極體感光區所覆蓋之覆蓋層。之後，去除頂蓋層， 再於閘極結構的側壁形成間隙壁。最後，進行自動對準金 屬矽化物製程，以在閘極導體層以及源極/汲極區上形成金 屬矽化物。 本發明在二極體感光區上覆蓋一層覆蓋層，可以避免 金氧半電晶體標準製程，因爲自動對準矽化物步驟在感光 .區上形成金屬矽化物，而造成大量的光反射效應。 本發明在二極體感光區上覆蓋一層以製備閘極介電層 方式所形成的覆蓋層。由於閘極介電層是半導體製程中用 以製作品質最好之氧化介電層的一種方式，其與基體之間 具有良好的界面態，且少缺陷，因此，本發明之感光元件 可以降低感光區表面的漏電流，以使感測器之暗電流降到 最小。 由於覆蓋層係在形成源極/汲極區之熱驅入步驟的同時 形成者，其整個製程與傳統的互補式金氧半導體元件的標 準製程相較，僅需多加一道光罩，即可達到改善因爲自動 對準金屬化製程所造成入射光大量反射的不良效應。 本發明之二極體感光區，其摻雜濃度較習知者低，因 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------- 裝--------訂---------線 C ... 厂 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1 04 6 A7 _A〇〇9twf Hnr/nnx__ 五、發明說明（6 ) 此，元件在施加電壓之後，其所形成之空乏區的寬度較寬， 光電轉換效率較高。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖係繪示習知一種主動式光二極體互補式金氧半 影像感測器的剖面圖。 第2A圖至第2F圖係繪示依照本發明實施例之一種主 動式光二極體互補式金氧半影像感測器之製造流程的剖面 圖。 圖式標記說明： 100、200 :基體 102、202 ··隔離區 104.:閘極氧化層 106 :閘極導體層 110、240 ;二極體感光區 114 :間隙壁 120、230 :電晶體 204 :介電層 204a :閘極導體層 206 :導體層 ' 206a:閘極導體層 208、208a :頂蓋層 7 本紙張尺度適用中ΐ國ϋ準（CNS)A4規格（210 X 297公釐) ^ ------:------ --------訂---------線 T ,( - . C (請先閱讀背面之注音？事項再填寫本頁) Α7 五、發明說明（4) 210 :離子植入 212、 214 ： 216a 220 ： 222、 46^ 〇4 6 213 :源極/汲極區 摻雜區 覆蓋層 金屬層 224、226 :金屬矽化物 复施例 請參照第2F圖，本發明之主動式光二極體互補式金氧 半影像感測器，包括一電晶體230、一二極體感光區240 與〜覆蓋層216a。 上述之電晶體230例如是一重置電晶體或是一傳送電 晶體，其結構包括一閘極介電層204a、閘極導體層206a、 源極/汲極區212與213。閘極介電層204a與閘極導體層 2G6a係配置於基體200上；而源極區213與二極體感光區 240的部分摻雜區214相連接，且其摻雜型態與摻雜區214 之摻雜型態相同。 閘極介電層204a之材質例如爲氧化矽，其形成的方法 例如爲熱氧化法。閘極導體層206a其材質例如爲複晶矽、 或複晶矽與金屬矽化物所組成的複晶矽化金屬(Polycide)、 或爲金屬材料。其形成的方法例如爲化學氣相沉積法或濺 鍍法。當閘極導體層206a爲複晶矽，較佳的電晶體230其 閘極導體層206a上更包括一金屬矽化物222，源極/汲極區 212、213更包括金屬矽化物224與226，以降低其片電阻。 金屬矽化物222、224與226之材質包括耐熱金屬所形成之 ------------裝--------訂---------線 r /1, ,/1、 (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 參紙張尺度適用中國家標準（CNS)A4規格（210 X 297公髮 46 1 04 6 A7 B7 五、發明說明（q ) 矽化物，例如爲矽化鈦或矽化鈷，其形成的方法例如爲自 動對準金屬矽化物（Salicide)製程。 二極體感光區240係位於基體200中隔離區202與電 晶體230之間。二極體感光區240係由摻雜區2.14與基體 200所組成者。摻雜區214之摻雜型態與源極/汲極區212、 213相同、但與基體200相異。當基體200之摻雜型態爲p 型，摻雜區214之摻雜型態則爲η型；若基體200之摻雜 型態爲η型，摻雜區214之摻雜型態則爲ρ型。依照互補 式金氧半導體元件的製程，二極體感光區240亦可以由摻 雜區214與介於摻雜區214與基體200之間的一摻雜井（未 繪示)所組成者，故，摻雜區214的摻雜型態亦包括與基體 200之摻雜型態相同者。 覆蓋層216a係以形成閘極介電層204a的方式所形成 者，其係配置於二極體感光區240之基體200上。覆蓋層 216a之材質例如爲氧化矽，其形成的方法例如是熱氧化 法。 上述之主動式光二極體互補式金氧半影像感測器的製 造方法如第2A圖至第2F圖所示。 請參照第2A圖，以局部區域氧化法或淺溝渠隔離法在 基體200中形成隔離區202,以在基體200界定出主動區。 然後，在基體200上形成介電層204、導體層206與頂蓋層 208。介電層204係作爲閘極介電層之用，其材質例如爲氧^ 化矽，形成方法例如爲熱氧化法。導體層206之材質例如 爲複晶矽，複晶矽與金屬矽化物所組成之複晶矽化金屬或 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) :裝---------訂---------線... 經濟部智慧財產局員工消費合作社印製 A7 B7 4々〇46 i、發明說明（$ ) 金屬，其形成的方法例如爲化學氣相沉積法。頂蓋層208 之材質例如爲氮化矽，形成的方法例如爲化學氣相沉積 法。 接著’請參照第2B圖，以微影與蝕刻技術定義頂蓋層 208、導體層206與介電層204，留下頂蓋層208a、導體層 206a與介電層204a，以作爲電晶體的閘極結構。其中，導 體層206a係作爲電晶體230之閘極導體層；介電層204a 則作爲電晶體230之閘極介電層；覆蓋於導體層206a上的 頂蓋層208a，則可以避免導體層206a在後續的過程中發生 氧化。然後，再以隔離區202 '頂蓋層208a爲罩幕，進行 離子植入步驟210，以將雜質植入於基體200之中。離子植 入步驟210所植入之雜質例如爲n型的磷或砷、或爲p型 的硼。 接著，請參照第2C圖，進行一熱驅入(Drive-in)製程， 並且在此進行熱驅入製程的同時進行熱氧化製程，以將上· 述植入於基體200之中的雜質驅入於基體200中形成源極/ 汲極區212、213以及與源極/汲極區213連接之二極體感光 區240的摻雜區214,並使所裸露的基體200表面形成一層 氧化矽覆蓋層216。 此熱氧化製程係以形成閘極氧化層的溫度施行，其氧 化的溫度約爲攝氏900度至1〇〇〇度，施行的時間約爲45 分鐘。此二極體感光區240所形成的摻雜區214 ’其濃度較-低於習知者，且其所形成之空乏區的寬度較寬，具有較高 的光電轉換效率。 10 本紙張尺二適用中國國家標準（CNS)A4規格（21〇 X 297公髮） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂—------線一 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製Follower), you can use the large current provided by the source follower to quickly charge and discharge the output terminal, so that the voltage at the output terminal is stable, and the noise is small. This type of optical sensor is generally called the active optical two. Polar body sensor (Active Pixel Photodiode). In recent years, in the application of many low-priced image sensors, the active light 3 paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 4 61 〇46 Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed A7 V. Description of the Invention (π) Diode complementary metal-oxide-semiconductor image sensor has become a substitute for Charge Coupled Device (CCD). Because the active photodiode complementary metal-oxide image sensor has high quantum efficiency (Quantum Efficiency), low g buy noise (Read Noise), high dynamic range (Dynamic Range) and random access (Random Access) And other characteristics, and has 100% compatibility with the process of complementary metal-oxide-semiconductor (CMOS) devices, so it can be easily compared with other control circuits, analog to digital converters (A / D Converter), and digital signal processing. The circuits are integrated on the same chip to achieve the so-called System On a Chip (SOC). For this reason, the active photodiode complementary metal-oxide half-image sensor is a trend for the development of image sensors in the future. Please refer to FIG. 1, and a conventional method for manufacturing an active photodiode complementary metal-oxide-semiconductor sensor is to form an isolation region 102 in a substrate 100, and then deposit an oxide layer and a polycrystalline silicon layer on the substrate 100. Then, through lithography and etching technology, an oxide layer and a polycrystalline silicon layer are defined to form a gate oxide layer 104 and a polycrystalline silicon gate 106 for resetting the gastric electrocrystal 120. Next, the isolation region 102 and the polysilicon gate 106 are used as implantation masks. A source / drain region 108 and a diode photoreceptor region 110 are formed in the substrate 100 by using ion implantation and thermal drive-in processes. 'S doped region 112. Thereafter, a spacer 114 is formed on the sidewalls of the polycrystalline silicon gate 106 and the gate oxide layer 104. In a typical complementary metal-oxide-semiconductor (CMOS) standard manufacturing process, 尙 includes a self-aligned silicide (Salicide) process to form metal silicide on the complex silicon gate 106 and source / drain 108. Materials to reduce the resistance of the component. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ill ----------------------- — Order --------- / T. (,: 'L {Please read the notes on the back before filling this page) S 4 1 04 6 A7 B7 2. Description of the Invention (々) However, when the above-mentioned standard complementary metal-oxide-semiconductor standard manufacturing process is applied to the production of active photodiode complementary metal-oxide-semiconductor image sensors, the photodiode area 110 After the auto-alignment metallization process is performed, metal silicide is formed like the complex silicon gate 124 and the source / drain 106. The diode photosensitive region 110 covering the metal silicide will cause a large amount of reflection of the incident light, which will greatly reduce the photoelectric transfer efficiency and affect the sensitivity of the entire 'sensor. In addition, there are many defects in the interface state on the surface of the diode photoreceptor region 110. Therefore, when light is irradiated on the n + / p diode photoreceptor region 110, the electron holes generated by the n + / p diode photoreceptor region 110 are empty. In the process of separating the electric field, the surface leakage current will be caused by the defect of the interface state. Therefore, the object of the present invention is to provide a structure of an active photodiode complementary metal-oxide half-image sensor to avoid the leakage current of the device. The purpose of the present invention is to provide a structure of an active photodiode complementary metal-oxide half-image sensor, which can increase the photoelectric transfer efficiency and improve the sensitivity of the entire sensor. The present invention proposes an active photodiode complementary metal-oxide-semiconductor image sensor, which includes a photodiode photodiode, a transistor, and a cover layer. The photodiode photodiode is located in the substrate and the photodiode The system is disposed on the substrate, and the source region of the transistor is connected to a part of the photodiode photosensitive region, covering the system formed by forming a gate dielectric layer, which is disposed on the photodiode photosensitive region. The present invention proposes a method for producing the above-mentioned active photodiode complementary gold paper with a standard applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) -------------, f- ------- Order --------- line, (/, (Please read the notes on the back before filling out this page) 4 6 104 6 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives Α7 Β7 V. Description of the Invention ($) A method for manufacturing an oxygen half image sensor, the method is to form a gate dielectric layer, a gate conductor layer and a cap layer on the substrate, and then use lithography and Etching technology defines it to form a gate structure. Then, an ion implantation step is performed first, and then a thermal drive-in and thermal oxidation process is performed to form a source / drain region and a doped photosensitive region in the substrate. And forming a cover layer on the surface of the exposed substrate. After that, a part of the cover layer is removed to leave a cover layer covered by the light-sensitive area of the diode. After that, the top cover layer is removed, and then the gate electrode is removed. The sidewall of the structure forms a gap wall. Finally, an automatic metal silicide process is performed to And forming a metal silicide on the source / drain region. The present invention covers a photosensitive layer of the diode, which can avoid the standard process of metal oxide semiconductors, because the auto-alignment silicide step is formed on the photosensitive region. The metal silicide causes a large amount of light reflection effect. The present invention covers the diode photosensitive layer with a cover layer formed by preparing a gate dielectric layer. Since the gate dielectric layer is used in the semiconductor manufacturing process to make One method of oxidizing the dielectric layer with the best quality has a good interface state with the substrate and few defects. Therefore, the photosensitive element of the present invention can reduce the leakage current on the surface of the photosensitive region to make the sensor dark. The current is reduced to a minimum. Since the cover layer is formed at the same time as the heat-driving step of the source / drain region, the entire process is compared with the standard process of the traditional complementary metal-oxide semiconductor device, and only one additional light is required. The mask can achieve the improvement of the adverse effect of the large amount of incident light reflection caused by the automatic alignment metallization process. The doped concentration of the diode photosensitive region of the present invention is relatively known Low, because 6 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) -------------- Loading -------- Order --- ------ Line C ... Factory (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 04 6 A7 _A〇〇9twf Hnr / nnx__ V. Description of the Invention (6) Therefore, after the voltage is applied, the width of the empty area formed by the device is wider, and the photoelectric conversion efficiency is higher. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following special A preferred embodiment will be described in detail with the accompanying drawings as follows: A brief description of the drawings: FIG. 1 shows a cross section of a conventional active photodiode complementary metal-oxide half-image sensor Illustration. Figures 2A to 2F are cross-sectional views showing the manufacturing process of a active photodiode complementary metal-oxide half-image sensor according to an embodiment of the present invention. Description of graphical symbols: 100, 200: substrates 102, 202 ·· Isolation area 104 .: Gate oxide layer 106: Gate conductor layer 110, 240; Diode photoreceptor area 114: Spacer wall 120, 230: Transistor 204 : Dielectric layer 204a: Gate conductor layer 206: Conductor layer '206a: Gate conductor layer 208, 208a: Top cover layer 7 This paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) ^ ------: ------ -------- Order --------- line T, (-. C (Please read the phonetic on the back? Matters before filling in This page) A7 V. Description of the invention (4) 210: ion implantation 212, 214: 216a 220: 222, 46 ^ 〇4 6 213: source / drain region doped region cover layer metal layer 224, 226: metal Please refer to FIG. 2F for an example of silicide restoration. The active photodiode complementary metal-oxide half-image sensor of the present invention includes a transistor 230, a diode photosensitive area 240, and a cover layer 216a. The transistor 230 is, for example, a reset transistor or a transmission transistor, and its structure includes a gate dielectric layer 204a, a gate conductor layer 206a, and source / drain regions 212 and 213. The gate dielectric layer 204a 2G6a series with gate conductor layer The source region 213 is connected to a part of the doped region 214 of the diode photosensitive region 240, and the doped pattern is the same as that of the doped region 214. Gate dielectric layer The material of 204a is, for example, silicon oxide, and a method for forming the same is, for example, a thermal oxidation method. The material of the gate conductor layer 206a is, for example, polycrystalline silicon, or polycide composed of polycrystalline silicon and metal silicide, Or it is a metal material. The method for forming it is, for example, chemical vapor deposition or sputtering. When the gate conductor layer 206a is polycrystalline silicon, the preferred transistor 230 includes a metal silicide on the gate conductor layer 206a. The material 222, the source / drain regions 212, 213 further include metal silicides 224 and 226 to reduce the sheet resistance. The materials of the metal silicides 222, 224, and 226 include heat-resistant metals. ----- Equipment -------- Order --------- Line r / 1,, / 1, (Please read the phonetic on the back? Matters before filling out this page) Ministry of Economy Wisdom Applicable National Standards (CNS) A4 Specifications (210 X 297 Public Issue 46 1 04 6 A7 B7) for Printing Paper Standards for Employees' Cooperatives of the Property Bureau V. Invention Description (q) The silicide is, for example, titanium silicide or cobalt silicide, and the method of forming the silicide is, for example, an auto-aligned metal silicide (Salicide) process. The photodiode region 240 is located between the isolation region 202 and the transistor 230 in the substrate 200. The diode photosensitive region 240 is composed of a doped region 2.14 and a substrate 200. The doped region 214 has the same doping pattern as the source / drain regions 212 and 213 but is different from the base 200. When the doping pattern of the substrate 200 is p-type, the doping pattern of the doped region 214 is η-type; if the doping pattern of the substrate 200 is η-type, the doping pattern of the doped region 214 is ρ type. According to the manufacturing process of the complementary metal-oxide semiconductor device, the diode photosensitive region 240 may also be composed of a doped region 214 and a doped well (not shown) between the doped region 214 and the substrate 200. Therefore, The doping pattern of the doped region 214 also includes the same doping pattern as that of the substrate 200. The cover layer 216a is formed in such a manner as to form the gate dielectric layer 204a, and is disposed on the substrate 200 of the diode photosensitive region 240. The material of the cover layer 216a is, for example, silicon oxide, and a method of forming the cover layer 216a is, for example, a thermal oxidation method. The manufacturing method of the above-mentioned active photodiode complementary metal-oxide half-image sensor is shown in Figs. 2A to 2F. Referring to FIG. 2A, an isolation region 202 is formed in the substrate 200 by a local area oxidation method or a shallow trench isolation method to define an active region in the substrate 200. Then, a dielectric layer 204, a conductor layer 206, and a cap layer 208 are formed on the substrate 200. The dielectric layer 204 is used as a gate dielectric layer. The material of the dielectric layer 204 is, for example, silicon oxide, and the formation method is, for example, a thermal oxidation method. The material of the conductive layer 206 is, for example, polycrystalline silicon, polycrystalline silicon silicide composed of polycrystalline silicon and metal silicide, or 9 paper sizes applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read first Note on the back, please fill out this page again): Install --------- Order --------- Line ... Printed by A7 B7 4々〇46, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs i. Description of the invention ($) The method of forming the metal is, for example, chemical vapor deposition. The material of the cap layer 208 is, for example, silicon nitride, and a method of forming the cap layer 208 is, for example, a chemical vapor deposition method. Next, please refer to FIG. 2B, define the cap layer 208, the conductor layer 206, and the dielectric layer 204 by lithography and etching techniques, leaving the cap layer 208a, the conductor layer 206a, and the dielectric layer 204a as the crystal Gate structure. Among them, the conductor layer 206a serves as the gate conductor layer of the transistor 230; the dielectric layer 204a serves as the gate dielectric layer of the transistor 230; and the cap layer 208a covering the conductor layer 206a can avoid the conductor layer 206a Oxidation occurs in subsequent processes. Then, using the isolation region 202 'and the cap layer 208a as a mask, an ion implantation step 210 is performed to implant impurities into the substrate 200. The impurity implanted in the ion implantation step 210 is, for example, n-type phosphorus or arsenic, or p-type boron. Next, referring to FIG. 2C, a drive-in process is performed, and a thermal oxidation process is performed at the same time as the heat-drive process, so as to drive the impurity drive implanted into the substrate 200 as described above. The doped regions 214 of the source / drain regions 212, 213 and the diode photosensitive region 240 connected to the source / drain regions 213 are formed in the substrate 200, and a layer of silicon oxide is formed on the surface of the exposed substrate 200. Cover layer 216. This thermal oxidation process is performed at the temperature at which the gate oxide layer is formed. The oxidation temperature is about 900 ° C to 1000 ° C, and the execution time is about 45 minutes. The concentration of the doped region 214 ′ formed by the photodiode photosensitive region 240 is lower than that of the conventional one, and the width of the empty region formed by the doped region 214 ′ is relatively wide, and has high photoelectric conversion efficiency. 10 This paper ruler 2 is applicable to China National Standard (CNS) A4 specification (21〇X 297) (Please read the precautions on the back before filling this page) --Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
^^正 j ,年月日^ ......-Ηί 全 J A7 Π7 τι^ΙΕΗαΒ j j/J,, 6 1046 6()02twfl.doc/002 _ > r,.^ ? τ ,,π ,τη I ^ ^ ___ 五、發明說明（^) 「 在上述過程中，由於頂蓋層208a可以保護閘極導體層 206a ’避免其上表面發生氧化，因此，氧化矽覆蓋層216 僅會形成於基體200所裸露的表面以及閘極導體層206a之 側壁。 其後，請參照第2D圖，以微影與蝕刻技術去除部分的 氧化矽覆蓋層216，以裸露出源極/汲極區212、213的基體 200表面，僅留下覆蓋於感光區240之氧化矽覆蓋層216a。 接著，去除頂蓋層206a，以裸露出閘極導體層206a的表面》 去除頂蓋層206a的方法包括等向性鈾刻法，例如是以熱磷 酸進行濕式蝕刻製程以去除之。 之後，請參照第2E圖，在閘極導體層206a以及閘極 介電層204a的側壁形成間隙壁218。間隙壁218之材質例 如爲氮化矽或爲氧介，矽，其形成的方法例如是以化學氣相 沉積法，先在基體200上覆蓋一層氮化矽層，再以非等向 性回蝕刻的方式形成間隙壁218。其後，進行自動準金屬矽 化物製程，其步驟係先在基體200上形成一層金屬層220。 金屬層220之材質包括耐熱金屬，例如爲鈦、鎢、鈷或鉑， 其形成的方法例如爲濺鍍法。 其後，請參照第2F圖，進行熱回火製程，使金屬層220 與其所接觸的閘極導體層206a、源極/汲極212 V 213的矽 成分產生反應，而分別形成金屬矽化物222、224與226， 然後，再以濕式蝕刻法將未參與反應的金屬層220去除。 在去除未參與反應的金屬層220之後，可再進行另一道回 火製程，以降低金屬矽化物222、224與226的阻値。 !! ^ — — — — ---II---- /t„, (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 461046 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（（G) 由於感光區240上覆蓋著一層覆蓋層216a，而並未與 金屬層220直接接觸，金屬層220並不會與感光區240的 基體200表面產生反應，因此，感光區240並不會形成金 屬矽化物，當未參與反應的金屬層220去除之後，感光區 240將裸露出覆蓋層216a。 本發明在二極體感光區上覆蓋一層覆蓋層，可以避免 金氧半電晶體標準製程，因爲自動對準矽化物步驟在感光 區上形成金屬矽化物，而造成大量的光反射效應。 本發明在二極體感光區上覆蓋一層以製備閘極介電層 方式所形成的覆蓋層。由於閘極介電層是半導體製程中用 以製作品質最好之介電層的一種方式，其與基體之間具有 良好的界面態，且少缺陷，因此，本發明之感光元件可以 降低感光區表面的漏電流，以使感測器之暗電流降到最 小。 由於覆蓋層係在形成源極/汲極區之熱驅入步驟的同時 形成者’其整個製程與傳統的互補式金氧半導體元件的標 準製程相較，僅需多加一道光罩，即可達到改善因爲自動 對準金屬化製程所造成入射光大量反射的不良效應。 本發明之二極體感光區，其摻雜濃度較習知者低，因 此’元件在施加電壓之後，其所形成之空乏區的寬度較寬’ 光電轉換效率較高。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內’當可作各種之更動與潤飾，因此本發明之保護 12 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線一 A7 B7 461046 6002twf.doc/008 五、發明說明（（I ) 範圍當視後附之申請專利範圍所界定者爲準 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）^^ 正 j, year, month, day ^ ...- Ηί All J A7 Π7 τι ^ ΙΕΗαΒ jj / J ,, 6 1046 6 () 02twfl.doc / 002 _ > r,. ^? Τ ,, π, τη I ^ ^ ___ V. Description of the invention (^) "In the above process, since the cap layer 208a can protect the gate conductor layer 206a 'from being oxidized on its upper surface, the silicon oxide cover layer 216 will only form On the exposed surface of the substrate 200 and the sidewall of the gate conductor layer 206a. Thereafter, referring to FIG. 2D, a portion of the silicon oxide cover layer 216 is removed by lithography and etching techniques to expose the source / drain regions 212. The surface of the substrate 200 of 213, only the silicon oxide covering layer 216a covering the photosensitive area 240 is left. Next, the top cap layer 206a is removed to expose the surface of the gate conductor layer 206a. Methods for removing the top cap layer 206a include, etc. Anisotropic uranium etching, for example, is performed by wet etching with hot phosphoric acid to remove it. After that, referring to FIG. 2E, a spacer 218 is formed on the sidewalls of the gate conductor layer 206a and the gate dielectric layer 204a. The spacer The material of 218 is, for example, silicon nitride or oxygen medium, and silicon, and the formation method thereof is, for example, chemical vapor deposition. Product method, a silicon nitride layer is first covered on the substrate 200, and then the spacer 218 is formed by anisotropic etchback. Thereafter, an automatic quasi-metal silicide process is performed, and the steps are formed on the substrate 200 first. A metal layer 220. The material of the metal layer 220 includes a heat-resistant metal, such as titanium, tungsten, cobalt, or platinum, and a method of forming the metal layer 220 is, for example, sputtering. Thereafter, refer to FIG. 2F and perform a thermal tempering process so that The metal layer 220 reacts with the silicon components of the gate conductor layer 206a and the source / drain 212 V 213 that it contacts to form metal silicides 222, 224, and 226, respectively. Then, the wet etching method will not participate The reaction metal layer 220 is removed. After the metal layer 220 not participating in the reaction is removed, another tempering process may be performed to reduce the resistance of the metal silicides 222, 224, and 226. !! ^ — — — —- -II ---- / t „, (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Cooperative printed A7 B7 V. Invention ((G) Since the photosensitive region 240 is covered with a cover layer 216a without directly contacting the metal layer 220, the metal layer 220 does not react with the surface of the substrate 200 of the photosensitive region 240. Therefore, the photosensitive region 240 does not A metal silicide will be formed. After the metal layer 220 not participating in the reaction is removed, the photosensitive region 240 will expose the cover layer 216a. In the present invention, a cover layer is coated on the photosensitive area of the diode, which can avoid the standard manufacturing process of the metal-oxide semiconductor, because a metal silicide is formed on the photosensitive area by the step of automatically aligning the silicide, which causes a large number of light reflection effects. The present invention covers a photodiode with a cover layer formed by preparing a gate dielectric layer. Since the gate dielectric layer is a method for making the best quality dielectric layer in a semiconductor process, it has a good interface state with the substrate and few defects. Therefore, the photosensitive element of the present invention can reduce the photosensitive area. Surface leakage current to minimize the dark current of the sensor. Because the cover layer is formed at the same time as the heat-driving step of the source / drain region, the entire process is compared with the standard process of the conventional complementary metal-oxide semiconductor device, and only one additional mask is needed to achieve Improves the adverse effect of a large amount of incident light reflection caused by the automatic alignment metallization process. The doped concentration of the diode photosensitive region of the present invention is lower than that of a conventional one. Therefore, after the element is applied with a voltage, the width of the empty region formed by the element is wider. The photoelectric conversion efficiency is higher. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention Protection 12 This paper size is applicable to China National Standard (CNS) A4 specification (21〇χ 297 mm) (Please read the precautions on the back before filling this page) ----- Line 1 A7 B7 461046 6002twf.doc / 008 V. Description of the invention ((I) The scope shall be determined by the scope of the attached patent application (please read the precautions on the back before filling this page) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)