460983460983
五、發明說明（1 發明領域 本發明是關於鈍化半導时置及其㈣方法，該方 :-謂階段製程，更明確地說是關於—較簡單，較便 立和更環保之晶圓階段製程製作 枉以裂邗许多適用於各種電壓 之鈍化半導體裝置。 發明背景 -半導體裝置(例如一整流器)之製程可概分為四個階 段’亦即接合面之形成、接合面之曝露、接合面之趣化以 及接點之形成。 接合面形成階段的已知製程包含：利用擴散的方法對晶 圓摻雜以提供合適的Ρ _ η層給所需的應用。 接合面曝露階段的已知製程包含：切割許多凹槽以形成 許多晶片。切割製程可以由圓形鋸來執行，其刀口適合部 份地切割過晶圓的厚度。之後，@圓係沿著切線被裂鱗 獨的晶片。此外，切割製程也可以用噴沙製程，在該製程 中不銹鋼的阻隔元件被黏到晶圓表面上所要的晶片之位 置。然掾，施以喷沙，使得沿著阻隔元件的邊緣形成凹槽 穿透過整個晶圓，以切割晶圓成所要的晶片。 由於在後續的製程中，個別晶片的處理係繁雜且高成本 的，因此有數種晶圓階段之製成方法乃被提出。美國專利 第4,904,610號提供一製程，此製程包含利用黏結性的中間 層將晶圓鑲配於基材上，並且於被鑲配的晶圓上切割許多 凹槽以形成許多晶片，在該製程中，凹槽的深度係延伸穿 過整個晶圓的厚度以及部份穿過黏結層但沒有延伸到基 —4 — 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝· I —一 I J— I 訂1—！1 ί 繞 經濟部智慧財產局員工消費合作社印製 3 •6V. Description of the Invention (1 Field of the Invention The present invention relates to the passivation of semiconducting timing and its method, which is: a stage process, more specifically about-a simpler, more convenient and more environmentally friendly wafer stage The manufacturing process is to crack many passivated semiconductor devices that are suitable for various voltages. BACKGROUND OF THE INVENTION- The manufacturing process of a semiconductor device (such as a rectifier) can be roughly divided into four stages, that is, the formation of the joint surface, the exposure of the joint surface, and the joint surface. Interesting and contact formation. Known processes in the joint formation stage include: doping the wafer using a diffusion method to provide the appropriate P_η layer for the required application. Known processes in the exposure stage of the joint Including: cutting many grooves to form many wafers. The cutting process can be performed by a circular saw with a knife edge suitable for partially cutting the thickness of the wafer. Afterwards, @ 圆 系 is split along the tangent line to separate the wafer. In addition, The cutting process can also use a sandblasting process, in which the barrier elements of stainless steel are adhered to the desired wafer position on the wafer surface. However, sandblasting is applied so that the The groove formed on the edge of the component penetrates the entire wafer to cut the wafer into the desired wafer. Because the processing of individual wafers is complicated and costly in subsequent processes, there are several wafer stage manufacturing methods. US Patent No. 4,904,610 provides a process that includes mounting a wafer on a substrate by using an adhesive interlayer, and cutting a plurality of grooves on the mounted wafer to form a plurality of wafers. In the process, the depth of the groove extends through the thickness of the entire wafer and partially through the adhesive layer but does not extend to the base—4 — This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) Equipment · I — 一 IJ— I order 1—! 1 ί Printed around the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 • 6
發明說明（ °98 經濟部智慧財產局員工消費合作社印製 材。美國專利第4,9〇4,61〇號的製程要求一 P使用溶劑（有毒性及對環境有害）以去除該黏結層。此 卜，分立的晶片藉由黏結層黏結到一基材上之方式、、 疋能提供像在—真正晶圓中未分割之各晶 = 的連結。 丨赝牛固 被廣泛採用之接合面曝露階段的晶圓階段製程，包人* 影步驟以蝕刻出在晶圓中的凹槽來曝露p-η層的p_n: 2 面，其中，凹槽為部份地穿過晶圓並有足夠深度來曝 η接合面。然而，微影的步驟係繁多且複雜，因而4= 到可靠度。 日办鲁 舜在接合面鈍化階段，美國專利第4,904,610號的製程包含塗 覆矽膠樹脂於開過凹槽的晶圓上以填滿凹槽。該矽膠=沪 不僅覆蓋該凹槽，更覆蓋晶片的表面，如此一來，在樹= 硬化後，需要有一額外的步騾來清除覆蓋晶片表面的2 脂。另一個傳統製程，係使用微影以塗覆玻璃到凹槽内以 鈍化該接合面。然而，如上面討論過的，微影的步騾繁 且複雜。 、 被廣泛採用於接點形成階段的製程，包含微影蝕刻接 點，這種方法繁瑣且複雜。美國專利第4,904,610號的製程 在整個製程開始時，利用三階段電鍍製程來形成接點（電 極），三階段電鍍製程後，整個表面被鍍上一層金膜。在 美國專利第4,904,610號的後續製程中，凹槽上的鍍金部份 在開凹槽後，將被去除而形成浪費。 另申請人於87年12月22曰所申請而仍在審查中之「製作 -5 - }紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚）: T !、— ！ .* 裝！--*!訂·！--- 竣 (讀先閱讀背面之注意事項再填寫本頁) 460983 五、發明說明（ 敛化半導體裝置之方法」（中請號：8712 〜 題提出一套有效之解決方案。然該案所形，、則述問 力線内縮之情形’以致磁場較高及/或電場：：槽會有： 易崩潰之情形。因此，該申社I 义间時會有容 用於較高之電塵。此外，該申請案所製作之半導 不適用於高溫之環境下。 心裝置亦 因此…晶圓階段製心製造適用於各 魏化半導體裝置且該製程是較簡單、較便宜、更 避免先前技術的缺點，仍為業界所企求者。 衣 可 發明插要 訂 半目的ΓΓ—晶圓階段製程，以製作_化 士導肢裝置，這個製程能免除部份或全部的微影步驟。 ，竣 發明的另-個目的是提供一個晶圓階段 國專利第讽610號之製程更簡單，更便宜，.且更環f呆美 本發月（另-目的在於提供一種挑化半導體裝置，其成 低，製程簡單且能適用於高電壓及高溫之環境。 根據本發明所揭示之方法，其包含了下列步驟：提供一 =少形成-個p-η接合面的半導體晶圓；接合一具有薄全 2二基板於該晶圓下方；形成許多凹槽在該晶圓上以曝 :。该至少一個p-n接合面，其中每—個該凹槽延伸穿過 H曰圓厚度的一部份’且有足夠的深度以曝露出該至少一個 接合面；鈍化該凹槽並硬化該鈍化材料；以及金屬化 ::圓。凹槽之形成可以利用有刀口的圓形鋸，或利用噴 VI%並控制製程時間，或利用微影化學蝕刻製程。鈍化 460983 經濟部智慧財產局員工消費合作社印製 17 A7 五、發明說明（ 層材料是藉由網印，塗佈或是藉由針梢分給方六、 dispensing)施加到凹槽中。切割製程可接著進亡、0万式（Ρώ- 切成個別的晶片並繼績製作成完整的半導體元丁件以將晶圓 圖式簡單說明 虹兀 。 圖1是根據本發明乏___且音# ω 截面圖。 一實施例的晶圓結構的部份橫 圖圖2是圖1之晶圓結構形成。_η接合面後之部份橫截面 圖3所示為圖2之結構在接合_具有铭板之基板後 橫截面圖。 ” 圖4所示為圖3之結構在形成凹槽之後之部扮橫截面圖。 圖5為圖4之結構於凹槽填充純化物f時的部份橫截面 圖。 圖6為圖5之結構於金屬化處理過後的部份橫截面圖。 圖7為圖6之結構在切割處理後之部份橫截面圖。 圖式元件符號説明 10 晶圓 π N型接面 12 P型接面 13 鋁層 14 P型基板 15 凹槽 16 鈍化材料 金屬層 表紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公楚） -i — ！JL裝·--111 訂·! !.線 {請先閱讀背面之注意事項再填寫本頁) Α7DESCRIPTION OF THE INVENTION (98) The printed materials of the cooperative of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. The process of U.S. Patent No. 4,904,610 requires a solvent (toxic and harmful to the environment) to remove the adhesive layer. This Bu, the way that discrete wafers are bonded to a substrate by an adhesive layer, can provide a connection like the undivided individual crystals in a real wafer. 丨 Yaku solid is widely used in the joint surface exposure stage In the wafer-level process, the encapsulation step is to etch out the grooves in the wafer to expose the p_n: 2 side of the p-η layer, where the grooves partially pass through the wafer and have sufficient depth to Exposure to the bonding surface. However, the lithography steps are numerous and complicated, so 4 = to reliability. In the passivation phase of the Japanese office Lu Shun, the process of U.S. Patent No. 4,904,610 includes applying a silicone resin to the grooves. To fill the groove on the wafer. The silicone = not only covers the groove, but also covers the surface of the wafer. As a result, after the tree = hardened, an additional step is required to remove the 2 grease covering the surface of the wafer. . Another traditional process, using micro Glass is coated into the groove to passivate the joint surface. However, as discussed above, the lithography steps are complicated and complicated. The process is widely used in the contact formation stage, including lithography etching contacts, This method is cumbersome and complicated. At the beginning of the entire process of US Patent No. 4,904,610, a three-stage electroplating process is used to form contacts (electrodes). After the three-stage electroplating process, the entire surface is plated with a gold film. In the United States In the subsequent process of Patent No. 4,904,610, the gold-plated part on the groove will be removed after the groove is formed, and waste will be formed. Another application, which was filed on December 22, 1987 and is still under review, "Making- 5-} The paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 Gongchu): T!,-!. * Packing!-*! Ordering! --- End (Read the precautions on the back before reading) (Fill in this page again) 460983 V. Explanation of the invention (Method for Converging Semiconductor Devices "(Centre No .: 8712 ~ Proposed a set of effective solutions. However, as the case is, the situation where the line of force shrinks 'As a result of the high magnetic field and / or electric field: The tank will have the following situations: It is easy to collapse. Therefore, the Shenshe I will sometimes be used for higher electric dust. In addition, the semiconductor produced in this application is not suitable for high temperature environments. The heart device is also Therefore ... wafer-level core manufacturing is applicable to various semiconductor devices, and the process is simpler, cheaper, and avoids the shortcomings of the previous technology, which is still sought by the industry. Yi Ke can invent a half-order ΓΓ-crystal The round stage process is used to make the _Hua Shi guide limb device. This process can eliminate some or all of the lithography steps. Another purpose of the completed invention is to provide a wafer stage national patent No. 610. The process is simpler , Cheaper, and more beautiful. This month (another purpose is to provide a picky semiconductor device, which has a low cost, a simple process, and can be applied to high voltage and high temperature environments. According to the method disclosed in the present invention, the method includes the following steps: providing a semiconductor wafer with less formation of a p-η junction surface; joining a thin substrate with a thin substrate, and forming a plurality of grooves on the wafer; The wafer is exposed to :. The at least one pn joint surface, wherein each of the grooves extends through a portion of the H-circle thickness and has a sufficient depth to expose the at least one joint surface; passivate the groove and harden the passivation material; Well metallized :: round. The groove can be formed by using a circular saw with a knife edge, or by spraying VI% and controlling the process time, or by using a lithography chemical etching process. Passivation 460983 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 17 A7 V. Description of the invention (The layer material is applied to the groove by screen printing, coating or dispensing to the square 6 by needle tips). The dicing process can then go on and off, 100,000-style (PFG-cut into individual wafers and then make a complete semiconductor element to briefly explain the wafer pattern. Figure 1 is lacking according to the present invention ___ And tone # ω cross-sectional view. Partial cross-sectional view of the wafer structure of an embodiment FIG. 2 is the formation of the wafer structure of FIG. 1. Partial cross-section behind the joint surface FIG. 3 shows the structure of FIG. 2 during bonding _A cross-sectional view of a substrate with a nameplate. "Fig. 4 is a cross-sectional view of the structure of Fig. 3 after the groove is formed. Fig. 5 is a portion of the structure of Fig. 4 when the groove is filled with the purified product f Fig. 6 is a partial cross-sectional view of the structure of Fig. 5 after the metallization process. Fig. 7 is a partial cross-sectional view of the structure of Fig. 6 after the cutting process. π N-type interface 12 P-type interface 13 Aluminum layer 14 P-type substrate 15 Groove 16 Passive material metal layer Surface paper size Applicable to China National Standard (CNS) A4 specification (21〇X 297) Chu -i —! JL Outfitting --- 111 Orders!!. Line {Please read the precautions on the back before filling out this page) Α7
4^〇98^ 五、發明說明（5 ) 較佳具體實施例的詳細說明 ^ 本發明所揭示之製造純化半導體之方法流程係如下所 示： 圖i所示為用於本發明具體化的製程中之—晶圓結構 10，该晶圓1 0可為一矽晶圓或其他類似者。如圖2所示， 該晶圓10是經由同時擴散硼及廣來摻雜以提供—卩4層， 其中p層I2為P接面，11層11為歐姆接觸層。圖式中之 層係為了方便表示’在本發明中p層與n層的相對位置是可 任意對調的（亦即，亦可11層在上而p層在下）。 本發明之具體化之製程之下一步騾如圖3所示，本發明 將:較厚且具有金屬板13(如銘板）之基板"（如p型基板） 在咼溫下接合至圖2所示之部份完成之半導體裝置下方。 夕本發明具體化之製程的下一步驟如圖4所示，係形成許 夕的凹槽15，丨中凹槽15係為v形凹槽並部份地穿過晶圓 二的厚度部份，且凹槽15每一個均具有一足夠的深度以曝 露P-η層的接合面。凹槽15可以利用有刀口的圓形鋸或是 噴：製程或是傳統的微影化學蝕刻方式形&。根據本發明 之-實施例，凹槽15是利用噴沙製程形成，其中藉由控制 噴沙時間使得凹槽15部份地延伸穿過晶圓【〇的厚度方向且 深度足以曝露P - η接合面。 本發明具體化的下一步驟如圖5所示，為鈍化凹槽Μ。 根據本發明的—具體實施例，鈍化材料Μ為可網印的材料 且被網印到凹槽15中。用於本發明具體化製程的可網印純 化材料1 6可為―種¥舊胺或破璃:>艮據本發明另—實施 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 Μ.---I.-->----------線 ----------------------------4 ^ 9898 ^ V. Detailed description of the invention (5) Detailed description of the preferred embodiments ^ The process flow of the method for manufacturing purified semiconductors disclosed in the present invention is as follows: Figure i shows the process used for the embodiment of the present invention. Among them—wafer structure 10, the wafer 10 may be a silicon wafer or the like. As shown in FIG. 2, the wafer 10 is doped through simultaneous diffusion of boron and silicon to provide four layers of ytterbium, where p layer I2 is a P junction, and 11 layers 11 are ohmic contact layers. The layers in the figure are for the convenience of representation. In the present invention, the relative positions of the p-layer and the n-layer can be arbitrarily reversed (that is, 11 layers can be on the top and p-layer can be on the bottom). The next step in the process of the embodiment of the present invention is shown in FIG. 3. The present invention will: a thicker substrate with a metal plate 13 (such as a name plate) (such as a p-type substrate) is bonded to FIG. 2 at a high temperature. The partially shown semiconductor device is completed below. The next step of the process of the embodiment of the present invention is shown in FIG. 4, which is to form a groove 15 of Xu Xi. The middle groove 15 is a v-shaped groove and partially passes through the thickness of the second wafer. Each of the grooves 15 has a sufficient depth to expose the joint surface of the P-η layer. The groove 15 can be formed by using a circular saw with a knife edge or spraying: a process or a conventional lithography chemical etching method. According to an embodiment of the present invention, the groove 15 is formed by a sandblasting process, wherein the groove 15 is partially extended through the thickness of the wafer [0] and the depth is sufficient to expose the P-η junction by controlling the sandblasting time. surface. The next step embodying the present invention is shown in FIG. 5, which is a passivation groove M. According to a specific embodiment of the present invention, the passivation material M is a screen-printable material and is screen-printed into the groove 15. The screen-printable purification material 16 used in the embodiment of the present invention may be a kind of ¥ old amine or broken glass: > According to the present invention, another implementation (please read the precautions on the back before filling this page) Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperatives M .--- I .-- > ---------- line -------------------- --------
297公釐） 4 6 098 3 A7 B7 五、發明說明（ 例，鈍化材料丨6 σ 1 、 中。使用在本發明疋實施針例梢；;給的且被針梢分給到凹槽b 種聚蝴2Γ::Γ梢分給之材料可以是〜 是可直接塗JV 發明之另—實施例，純化材料 玻璃。在二:槽16中’而其材料可為論胺或 施加鈍化材料i 6至凹槽 材料16之步驟。 至凹槽15後’實施硬化該鈍化 本發明具體化之_ ^ θ Π1Λ 4程的下-步驟如圖6所示，為金屬化 邊卵回10，亦即在該晶圓丨〇之上、 層17 Γ如水a、、 下—侧各電鍍一金屬 、* m以形成接點。鈍化材料1 6的表面是血法電 ::無法電鍵金，因此在電錄製程中不需二屏 或去除的步驟。 匕日7汫 具體化的晶圓階段製程後，可藉—切剖製程切 二 =所示)成為個別之已魏化保護接合面之晶 成。程可藉由使用雷射光或是有刀口的圓形銀來完 體2 ’ St該等晶片經過封裝之製程，以形成崎導 虹衣置。藉由本發明所揭示之. 々製程飼““ 所製成之半導體裝置 Sr，且能適用於高溫及高電壓之環 因此，顯已符合准予發明專利之要件。 以上說明’揭示了本發明τ η、θ 、 个叙明不间又具體化製程。秣而仍 以發：範圍之：，做許多的修改和替代。所以， 圍。、§ ;僅疋為了揭71"本發明，而並不限制本發明的範 閲 鍍蔽 訂 不境 可 9 - 本紙張尺度勒中國國家標準（CNS>A4規格（210] 297公釐〉297 mm) 4 6 098 3 A7 B7 V. Description of the invention (for example, passivation material 丨 6 σ 1). Used in the present invention to implement the needle tip; given and divided by the needle tip into the groove b Poly butterfly 2 Γ :: Γ tip can be divided into materials that can be directly coated with JV. Another embodiment of the invention, the purified material glass. In the two: tank 16 'and its material can be amine or passivation material i 6 Step to the groove material 16. After the groove 15, the hardening and passivation of the present invention is implemented. ^ Θ Π1Λ The next 4 steps of the process are shown in FIG. Above the wafer, the layer 17 Γ is plated with a metal and * m on the lower side, respectively, to form a contact. The surface of the passivation material 16 is hematological electricity :: gold cannot be bonded, so There is no need for two screens or removal steps in the manufacturing process. After the wafer stage process is realized in 7 days, it can be cut through the cutting process (see 2) (see below) to become an individual crystal that has been protected. The process can use laser light or round silver with a knife edge to complete the 2 ′ St wafers through a packaging process to form a rugged iris. According to the disclosure of the present invention, the semiconductor device Sr manufactured by the "々 process process" can be applied to high-temperature and high-voltage loops. Therefore, it has clearly met the requirements for granting an invention patent. The above description 'discloses the invention τ η, θ and the detailed and specific process. Instead, I still send it: Scope of it: make many modifications and replacements. So, Wai. , Only for the purpose of revealing 71 " the present invention, and does not limit the scope of the present invention. Plating, ordering, etc. 9-This paper is a Chinese national standard (CNS > A4 specification (210) 297 mm>