TW460944B - Laterally diffused metal oxide semiconductor with gradient doped source/drain and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a method for forming a laterally diffused metal oxide semiconductor device. The method comprises the following steps. First, a conductive semiconductor layer is provided and then a field insulating layer is formed therein. Next, a gate dielectric area is formed over a portion of the field insulating layer and a first conductive drain region is formed in the semiconductor layer and adjacent to the field insulating layer that has a first doped concentration. A second conductive source/drain region is formed in the semiconductor layer and is separated from the field insulating layer by a channel region. A conductive lightly doped region is adjacent to the channel region and the filed insulating region wherein the conductive lightly doped region has a first doped concentration. The conductive main region is next to the filed insulating region and it has the first doped concentration smaller than the second doped concentration and is separated from the channel region. A conductive region is formed in the semiconductor layer and is separated form the first drain region by a channel region. A deep part of the conductive region is formed in the semiconductor layer and it has a third doped concentration smaller than the second doped concentration and is separated from the surface of the semiconductor layer.

Description

4 60944 _ Case No. 88107363_ Year Month Date _ Amendment __ V. Description of the Invention (1) 5-1 Field of Invention:-The present invention relates to a forming method for forming a semiconductor element by a side diffusion method. 5-2 Background of the Invention: Laterally Diffused Metal-Oxide Semiconductor (LDM0S) has been widely used for logic elements, memory elements, or other voltage stabilizing elements on a single wafer of a substrate, and can usually be used in applications. Think of it as a separate element. The first picture is a cross-section of a conventional LDM0S transistor, including P-type substrate 1 00 'V-type channel 1 1 〇, P-type body 1 20, N + source 1 30, gate 1 4 0 , The drain electrode 150, the gate oxide layer 160, and the oxide layer 170. The V-shaped trench 110 can reduce the size of the LDM0S. The side diffused metal-oxide semiconductor transistor is commonly used in high-voltage integrated circuits. This technology can also be used in low-voltage circuits or logic circuit processes. Generally, it can also be applied to the sputtering layer with thick reverse potential, or to the thin sputtering layer. A voltage semiconductor element includes a high voltage integrated circuit having one or more transistors. The side-diffused metal-oxide semiconductor transistor for high-voltage integrated circuit applications focuses on its low resistance, high switching speed, and low gate driving force loss. Therefore, the device is based on a bi-carrier complementary metal-oxide semiconductor (Bipo 1 ar

Complementary Metal-Oxide Semiconductor (BiCMOS) has high cohesion in its process.

Page 5 460944 Case No. 88107363 A_η Modification The mixing in a class environment can be input to the substrate through the resistance of the transistor. A more common dual input bias is complicated. The size of the device and the breakdown voltage need to be optimized to minimize the collapse of the metal-oxide semiconductor. , The diffusion pressure of the smoke; and the description of the invention (2) When this circuit is energized, the power will be reduced by the switch in the communication area. The power switch will reduce this power, and when it is combined, the design must be offset. The dynamic I c element pressure is obtained, and the high transistor layer thickness of the collapsed conductor is obtained. The side spread is still high, so the side expansion is more severe than the comprehensive high-voltage crash chip. It will affect the reactance when the substrate is mixed with the single crystal of the circuit and there is a problem. The effect will be reduced. The problem is that when the analog system operates together, it depends on the higher doping layer breakdown voltage. Chip logic and switching power. For example, logic and power enter the analog area, that is, when other circuits of the chip should. The department uses a single bias group, so it will cause the voltage output element to collapse. The main point of the element design for the side-diffused metal-oxygen half-adjusted migration region to adapt the breakdown voltage is the low resistance. However, the two electrical device designs are incompatible with each other in the overall program design. Metal-oxide semiconductor device design The manufacturing process must integrate other high and low voltage components in a single crystal-3. Purpose and summary of the invention: In view of the above background of the invention, it is proposed to use side diffusion for side expansion.

Page 6 4 S ((I944 _ case number 88107363_ year month day amendment _ V. Description of the invention (3) Forming method of loose oxygen semiconductors. An embodiment is detailed in the second figure A to the second figure K of this process The steps are as follows. First, a conductive layer is formed, then an electric field insulation region is formed, and then a gate dielectric region is formed on a portion of the insulation region. Then, a deep portion of the first source / drain region is formed on the semiconductor layer. This deep part is doped with a conductive type dopant, which is the first doping concentration in this depth: usually the lightly doped part of the first drain region is formed simultaneously with the semiconductor layer and the electric field insulation region Partially adjacent and connected to the channel region. The lightly doped portion of the first drain region is doped with a conductive dopant at a second doping concentration lower than the first doping concentration. Slightly doped portion. Simultaneously formed with the semiconductor layer, adjacent to the gate region portion, and connected to the source region. The lightly doped portion of the first drain region is doped at a second concentration that is lower than the first doped concentration. Concentration, doped with a conductive type dopant.. The main part of a source / drain region is formed in the semiconductor layer. The part is adjacent to the gate / insulation area, and is connected to the lightly doped part. The main part placed deep inside is doped with a conductive dopant. Here, a third doping concentration is formed, which is lower than First and second doping concentrations. A second source / drain region is formed in the semiconductor layer, and the second source / drain region is doped with a conductive type dopant.

I As mentioned above, the deep portion and the lightly doped portion are simultaneously formed, and the deep portion and the lightly doped portion are simultaneously doped with a conductive type dopant. The formation of the second source / drain region includes the following steps: First, a slightly doped portion of the second source / drain region forms a channel. Second, the main portion forming the second source / drain region is adjacent to the slightly doped portion of the second source / drain region. Major portions of the first and second source / drain regions are formed simultaneously, while the second

Page 7 460944 _ / case No. 88107363 _ year and month q chromium, τ V. Description of the invention (4), the forming step of the source / drain region further includes the deep part of the second source / drain region, > in the semiconductor Layer, and is separated from the surface i-shaped 3 ',, and green areas by a slightly doped portion and a main portion. As shown in the second figure K, the high-voltage driving force that expands to the channel and in particular, the gate area is expanded toward the depth of the semiconductor layer, which indicates that the gate area is larger than the traditional structure shown in the first figure. Zone can get better 5-4 detailed description:

The first embodiment, such as the second diagram A to the second diagram K, details a procedure of a new invention of a memory cell with a slightly doped source / drain region of a person + A mouth juice. For the sake of brevity, it can be regarded as Switching transistor in a stacked capacitor process. / Douyi A 'is. Shi Xi oxide 12 is formed on the semiconductor > instrument // by thermal oxidation method, and the thickness of the oxide layer is 100 Angstroms to 300 Angstroms. The portion of the first polycrystalline silicon layer in the region 'is defined by the N-well 1 mask, and the second doped N-well 1' is as if the engraving 13 is formed by the transplantation method. The final doping parameters were 3E1 5 to 2E1 6 / cm3, and then N-wells 1, 13 were approached by thermal oxidation. The second diagram B shows N wells 1 '1 3, N wells 2, 14 and P wells 1, 15 by forming a second conductive layer by the well mask definition, and defining p wells by development. The thermal diffusion method was used to control the doping parameter to 3 £; 15 to 2E16 / cm3, and a continuous approach procedure was performed.

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V. Explanation of the invention (5) The J isolation method will make the trench 16 long & [well i 井 Well 2, and the trench isolation method will fully use anisotropy. The second secretary is a thermal oxidation method after removing the 12th grade oxidized layer 12 of the pad oxide layer, and the thickness of the pad oxide layer is about ι 00, = 200 angstroms. The first picture E shows that nitride is deposited by low pressure chemical vapor deposition. The thickness of the silicon nitride 17 is about 1000 angstroms to 3,000 angstroms. Case No. 881073 @@ As shown in the second F picture, the pad oxide layer 1 2 A removes the side wall of Yanqugou 16 2 ΓG picture is the active area mask process and the silicon nitride 17 part will also be continuous The ground-etched oxide layer 18 is formed on the top layer and has a width of about 3,000 angstroms to 1000 angstroms. The formation of the oxide layer i 8 is produced by using the dioxide 1 for insulative purposes, usually by a photolithography method and using a high density plasma (Hi Density Plasma). As shown in the second detail, the nitrided oxide 17 and the hafnium oxide layer m are removed respectively. As shown in the figure, the gate oxide layer 1 2 8 is deposited by a low pressure chemical vapor deposition method on the PL i 〇 surface, or thermally. Diffusion method or implantation method, the gate oxide layer is deep, = Ί # ⑽angular to 100 angstroms, and then N-doped polycrystalline silicon is 19 and backfilled into the channel a. The picture shows the gate mask The development etching process, and the formation of N-Li polysilicon 19. / # ′ As shown in the figure of Μf ~ I, the P-bottom 20 layer is defined by a P-bottom mask and then formed by thermal transplantation. Its doping parameters are 2 £ 16 to 2Ei7 / cm3. First, as shown in the first K diagram, the N and p sources of the transistor are 21 τ Ρ + ή = fire forming annealing is performed quickly to promote the diffusion of semiconductor ions. The region 21 is located above the ρ 嫄 / drain layer and below the semiconductor substrate. The advantage of this new structure is that the breakdown voltage is high in moderation-integration & 'and the new structure can also save Behind the wafer surface 0-

4 6 0 944 _Case No. 88107363_Year Month Date__ V. Description of the Invention (6) In the above implementation, for convenience of explanation, P and N have exaggerated diagrams. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 10 4 SO944 _Case No. 88107363_ Year Modification _ Brief Description of Drawings The first picture is a cross-section view of a transistor with a conventional source / drain region side diffused gold oxide semiconductor. The second diagram A to the second K diagram include an embodiment and details the process steps of the invention. The main representative symbols of the present invention: First picture: 100 substrates 110 trenches 120 P-type body 130 source 140 gate 150 gate 160 gate oxide layer 170 oxide layer Second A to second 11 substrate 12 silicon oxide 12A Pad oxide layer 12B Gate oxide layer 13 N well 1 14 N well 2

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Claims (1)

4 60 944 _ Case No. 88107363, Amendment 6. Scope of patent application 1. A kind of side diffusion gold / oxide semiconductor with doped source / drain, including at least: A semiconductor layer with a conductive layer; an electric field insulation region located in the semiconductor layer; a gate dielectric electrode located above the electric field insulation region portion; a gate electrode located at least above the channel region and the electric field insulation region portion; a conductive type A first drain region is formed on the semiconductor layer and is adjacent to the electric field insulation region having a first doping concentration; a first source region of a conductive type is formed on the semiconductor layer and has a first doping A second source of one concentration is separated by a channel region 'adjacent to the conductive edge region', the conductive type is spaced from the second doped thick conductive type forming region, and the conductive type is concentrated from the second doped concentration gate electrode. The drain region is adjacent to the conductive type, which is formed on the semiconductor layer, and is separated from the first drain region. One of the lightly doped portion has a slightly doped portion with the channel region and the electric field. A first doping concentration; the main part is adjacent to the electric field insulation region and is spaced from the channel region with a small first doping concentration; the semiconductor layer is formed on the semiconductor layer and a channel region and The first deep part is formed in the Conductor layer, and having a third dopant concentration to small degrees, and spaced apart from said top surface. 2. As described in item 1 of the scope of the patent application, a side diffusion metal oxide semiconductor with a gradient doped source / drain is formed, wherein the above-mentioned electric field insulation region is formed on the semiconductor layer, thereby separating the element from other elements. Layers. Page 11 4 60 94 | No. 881Q7363 Amendment VI. Patent application scope 3. As described in the first patent application scope, the side of the doped source / drain is diffused with gold oxide semiconductor, where the channel region is described above. Formed under the electric field insulation region. 4. As described in item 1 of the scope of the patent application, a side-diffused gold-oxygen semiconductor with a doped source / drain electrode, wherein the semiconductor layer includes at least silicon. 5. As described in item 1 of the scope of the patent application, the side-diffused gold-oxide semiconductor with a doped source / drain is gradient-doped, wherein the above-mentioned gate electrode includes at least polycrystalline silicon. 6. The side diffused metal-oxide semiconductor with a gradient doped source / drain as described in item 1 of the scope of patent application, wherein the first and second source / drain regions include rr-doped semiconductor and p-doped The channel region of the semiconductor. 7. The diffusion-diffused metal-oxide semiconductor with a gradient doped source / drain as described in item 1 of the scope of patent application, wherein the above-mentioned electric field insulation region is adjacent to a side · wall of a gate electrode. 8. Gradient doped source / drain side diffused gold-oxide semiconductors as described in item 1 of the scope of the patent application, wherein the semiconductor layer includes at least a semiconductor substrate. 9. As described in item 1 of the scope of the patent application, the side of the doped source / drain electrode is diffused with gold oxide semiconductor, wherein the deep part mentioned above is molded at this slight Page 12 460944 _Case No. 88107363_ Year Month Date _ Amendment _ 6. Scope of patent application Doped part. 10. As described in item 9 of the scope of the patent application, a side-diffused gold-oxygen semiconductor with a gradient doped source / drain is described, in which the deep portion mentioned above is lower than the main portion and is close to the main portion. " 11. As described in item 1 of the scope of the patent application, a side-diffused Au / S semiconductor with a gradient doped source / drain, wherein the above-mentioned first source / drain region includes: a lightly doped portion, and The channel region and the top surface are adjacent, the lightly doped portion has a first doping concentration; a main portion of the conductive type is adjacent to the electric field insulation region, and a first doping having a lower doping concentration is used. The impurity concentration is spaced from the channel region; and the deep portion of the conductive type is formed on the layer and has a third doping concentration less than the first doping concentration and the second doping concentration, and The top surfaces are spaced apart. 1 2. —A method for diffusing a metal oxide semiconductor with a gradient doped source / drain side, at least comprising: providing a semiconductor layer having a conductivity type; forming an electric field insulation region into the semiconductor layer; forming a gate dielectric An electric region is located above the electric field insulating region portion; a conductive type is formed in which a first drain region is formed on the semiconductor layer and is adjacent to the electric field insulating region having a first doping concentration; forming a second source / drain Region and the conductive type, formed on the semiconductor layer Page 13 4 60 944 _ Case No. 88107363 Amendment 6. The scope of the patent application and a channel region spaced from the first drain region; forming a lightly doped portion of the conduction type with the channel region Adjacent to the electric field insulation region, the lightly doped portion has a first doping concentration; the main part forming the conductive type is adjacent to the electric field insulation region, and the first portion has a first doping concentration less than a second doping concentration. The doping concentration is spaced from the channel region; a conductive type is formed and formed on the semiconductor layer, and a channel region is spaced from the first drain region; and a deep part of the conductive type is formed on the And is spaced from the top surface with a third doping concentration that is less than the second doping concentration. 13. The method as described in item 12 of the scope of patent application, wherein the above step further includes a step of forming a deep portion and a lightly doped portion simultaneously. 14. The method according to item 13 of the scope of patent application, wherein the above step further includes a step of forming a deep portion and a lightly doped portion simultaneously by the conductive implanted dopant. 15. The method according to item 14 of the scope of patent application, wherein the above-mentioned step further comprises: forming a lightly doped region in a deep portion of the second source / drain region and adjacent to the channel; and The second source / drain region forms a major region and is adjacent to the second source / non-doped region. m Page 14 4 · 6 Ο 944 Case No. 88107363 _Ά Amendment VI. Patent application scope 16. The method described in item 15 of the patent application scope, wherein the above steps further include: in the first source / draw area The main part is formed simultaneously with the main part of the second source / drain region. 17. The method as described in item 16 of the scope of patent application, wherein the second source / drain forming step further comprises: forming a deep portion of the second source / drain on the semiconductor layer and using the slight doping Miscellaneous regions are separated from the main region by the second source / > region. Page 15