A7 B7 457672 6552twf.doc/006 五、發明說明（,） 本發明是有關於一種半導體封裝基板結構，且特別是 有關於利用波形電鍍線，以改善基板分離製程中，因爲各 圖案化線路層間的對準誤差，造成導電跡線無法電性隔離 之問題。 就半導體構裝技術發展而言，由於半導體技術積集度 的提升，而且逐漸朝向功能整合之方向設計晶片，因此諸 多系統晶片（System On Chip，SOC)的產品相繼誕生。同 時隨著半導體產品資料處理能力的加強，相對地晶片所需 的輸入/輸出接點逐漸增多，且晶片的尺寸亦隨之增加，因 此因應的構裝技術也需符合此趨勢之需求，所以近年來高 密度，高腳位數的半導體構裝產品確實是與日遽增。在高 密度’闻腳位數半導體產品中，基板型承載器（substrate type carder)是經常使用的構裝元件，其主要包括堆疊壓合式及 積層式（build up)二大類。而針對球格陣列構裝（Ball Grid Array，BGA)用基板而言，則是以堆疊壓合式基板爲主流。 因爲半導體元件發展趨勢的影響’基板的接點數需求逐漸 提高，而基板佈線密度及面積亦隨之提高’使得基板製造 技術難度提高。 請參照第1圖，其所繪示爲習知半導體封裝基板剖面 不意圖。 如第1圖所示，封裝基板100包括圖案化線路層 102a〜102d、以及絕緣層106。絕緣層106分別配置於相鄰 的圖案化線路層102a、102b之間，圖案化線路層l〇2b、102c 之間，以及圖案化線路層102c、102d之間，以形成電性隔 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注f項再填寫本頁) ^i---^j —訂-------- 經濟部智慧財產局員工消費合作社印製 457672 65 52 twf. doc/0 0 6 五、發明說明（2) 離。絕緣層106中具有數個導電貫孔l〇8(conductive via)與 導電微孔l〇9(conductive micro via)，使得圖案化線路層 102a~102d彼此電性連接。而在圖案化線路層l〇2a、102d 表面則分別形成銲罩層Π8,並藉由定義形成開口 120, 暴露出圖案化線路層l〇2a、102d的部分表面，構成封裝基 板100之接點，包括金手指(gold finger)及靜球墊(ball pad)。 請參照第2圖，其所繪示爲對應第1圖習知半導體封 裝基板平面示意圖。 經濟部智慧財產局員工消費合作社印製 {請先閱讀背面之注意事項再填寫本頁) 如第2圖所示，以圖案化線路層l〇2b爲例，封裝基 板100由數個封裝單元區域110所組成，封裝單元區域110 彼此相鄰排列，而每一封裝單元區域110中分別具有數條 導電跡線112(trace line) ’半導體封裝基板1〇〇則是利用導 電跡線112及前述的導電貫孔或導電微孔，用以連接金手 指與銲球墊。由於封裝基板1〇〇線路密度要求愈來愈高， 因此無法將所有線路集中於表層，再串接於電鍍線，因此 在各層圖案化線路層均需配置有電鍍線。電鍍線116分別 配置於封裝單元區域110鄰接的邊界，且分別與每一封裝 單元區域110中的每一導電跡線112電性連接。電鍍線116 用以連接陰極’以進行接點的電鍍，於電鍍完成後，會將 電鍍線116 —倂切除，以使各導電跡線ι12間電性獨立。 請參照第3A圖與第3B圖，其所繪示爲對應第2圖習 知半導體封裝基板之圖案化線路層局部放大示意圖。 如第3A圖所示’習知電鍍線i16a、n6b設計的方式 爲沿著封裝單元區域110鄰接的邊界，而呈一垂直導電跡 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 經濟部智慧財產局員工消費合作社印製 457672 6552twf+doc/006 五、發明說明（多） 線112之直線’以匯接導電跡線112再接至電極進行電鑛。 如第3B圖所示，由於圖案化線路層i〇2a可能因叠合時， 與圖案化線路層102b之間產生偏移，同時使得圖案化線 路層102a的電鍍線116a與圖案化線路層102b的電鍍線 116b亦形成偏移。使得封裝單元區域11〇在進行分離的步 驟時，因爲僅能對準圖案化線路層l〇2a的電鍍線116a進 行切割，而切割刀的寬度120有限，若偏移量過大，切割 刀無法涵蓋內部圖案化線路層的電鍍線116b，則無法將圖 案化線路層102b上的電鍍線116b切除，而造成產品導電 跡線112短路，影響產品良率。 因此本發明之目的即在提供一種半導體封裝基扳，即 使圖案化線路層之間產生偏移，仍可順利將各圖案化線路 層上的電鍍線切除，防止產品導電跡線短路，提高產品良 率。 本發明的另一目的在於提出一種半導體封裝基板，即 使切割刀於分離步驟時產生偏移，仍可順利將各圖案化線 路層上的電鍍線切除，防止產品導電跡線短路，提高產品 良率。 根據本發明之上述及其他之目的，提出一種半導體封 裝基板’包括：數層圖案化線路層與至少一絕緣層。絕緣 層配置於相鄰的圖案化線路層之間，以形成電性隔離，其 中絕緣層中具有數個導電貫孔，使得圖案化線路層彼此電 性連接。其中半導體封裝基板具有數個封裝單元區域，彼 此相鄰排列，圖案化線路層分別由數條導電跡線所組成， 5 本紙張尺度適用中圉國家標準（CNS)A4規格（210 X 297公釐） — — — — — — — — — - ^ - ---l· I I I ^ ill — — — — — — . (請先閱讀背面之注意事項再填寫本頁) A7 B7 6552twf,doc/006 五、發明說明（/f > 而且在封裝單元區域相鄰的邊界分別具有一波形電鍍線， 波形電鍍線分別與同層的導電跡線電性連接，波形電鍍線 係在封裝單元區域相鄰的邊界於一預定寬度內迂迴擺盪。 依照本發明之較佳實施例，本發明半導體封裝基板， 僅需將封裝單元區域相鄰的邊界之電鍍線重新設計，可設 計電鍍線之波形呈一鋸齒波形 '方波形狀、Z形波、或呈 一正弦波，且使電鍍線在封裝單元區域相鄰的邊界於一預 定寬度內迂迴擺盪，即使圖案化線路層之間產生偏移，或 切割刀於分離步驟時產生偏移，仍可順利將圖案化線路層 上的電鍍線切除，防止產品信號短路，提高產品良率。 爲讓本發明之上述和其他目的'特徵、和優點能更 明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖繪示爲習知半導體封裝基板剖面示意圖。 第2圖繪示爲對應於第1圖之習知半導體封裝基板平 面示意圖。 第3A圖與第3B圖繪示爲對應第2圖習知半導體封裝 基板之圖案化線路層局部放大示意圖。 第4圖繪示爲根據本發明半導體封裝基板較佳實施例 的剖面示意圖。 第5圖繪示爲對應第4圖根據本發明半導體封裝基板 較佳實施例的平面示意圖。 第6A圖與第6B圖繪示爲對應第5圖根據本發明半導 6 — — — — — — — — — — —— - I I I l· I I I — 111 — — — — — ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） 457672 6552twf- doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f) 體封裝基板較佳實施例之圖案化線路層局部放大示意圖。 第7A圖至第7C圖繪示爲根據本發明半導體封裝基板 其他較佳實施例之圖案化線路層局部放大示意圖。 圖式之標記說明： 100 ' 200 :封裝基板 102a~102d、202a〜202d :圖案化線路層 106、206 :絕緣層 108、 208 :導電貫孔 109、 209 :導電微孔 110、 210 :封裝單元區域 112、212 :導電跡線 116、216 :電鍍線 118、218 :銲罩層 120、220 :開口 122、224 :切割刀寬度 222 :寬度 316 :鋸齒波形 416 : Z形波 516 :正弦波 實施例 請參照第4圖，其所繪示爲根據本發明半導體封裝基 板較佳實施例的剖面示意圖。 如第4圖所示，半導體封裝基板200中包括圖案化線 路層202a~202d、以及絕緣層206。絕緣層206分別配置於 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) Λ-----r---訂---------線. 經濟部智慧財產局員工消費合作社印製 457672 6552twf.doc/006 五、發明說明（έ) 相鄰的圖案化線路層202a、202b之間，圖案化線路層202b、 202c之間，以及圖案化線路層202c、202d之間，以形成 電性隔離。絕緣層206之材質比如爲玻璃環氧基樹脂(FR-4、FR-5)或雙順丁烯二酸醯亞胺三氮畊（Bismaleimide-Triazine, BT)等。而圖案化線路層202a〜202d，比如由-一銅 箔層經過微影蝕刻定義形成。絕緣層206中具有數個導電 貫孔208與導電微孔209,使得圖案化線路層202a〜202d 彼此電性連接。導電貫孔208比如利用機械鑽孔方式，再 經由塞孔製程形成。導電微孔209則利用雷射鑽孔，再經 由電鍍(electric plating)形成。而在圖案化線路層202a、202d 表面則分別形成銲罩層218,並藉由定義形成開口 220, 暴露出圖案化線路層202a、202d的部分表面，構成封裝基 板200之接點，包括金手指及銲球墊。其中銲罩層218包 括紫外線型綠漆及熱硬化型綠漆等，而塗佈綠漆之方法則 包括滾筒塗佈法（Roller Coating)、簾幕塗佈法（Curtain Coating)、網版印刷法（Screen Printing)、浸染法（Dip)以及 乾膜(Dry Film)形成方法等。 請參照第5圖，其所繪示爲對應第4圖根據本發明半 導體封裝基板較佳實施例的平面示意圖。 如第5圖所示，封裝基板200由數個封裝單元區域210 所組成，封裝單元區域210彼此相鄰排列，而每一封裝單 元區域210中分別具有數條導電跡線212,封裝基板200 則是利用導電跡線212用以連接金手指及銲球墊。由於封 裝基板200線路密度要求愈來愈高，因此無法將所有線路 8 本紙張尺度適用t固國家標準（CNS)A4規格（210 X 297公餐—) ulllliillll^i!l·!— 訂· — ！ I 線' (請先閱讀背面之注意事項再填寫本頁) 457 457 A7 B7 6552tv;f.doc/006 五、發明說明（q) 集中於表層，再串接於電鍍線，因此在內部的圖案化線路 層亦需配置有電鍍線。電鍍線216分別配置於封裝單元區 域210鄰接的邊界，且分別與每一封裝單元區域210中的 每一導電跡線212電性連接。電鍍線216用以連接陰極， 以進行接點的電鍍，於電鍍完成後，會將電鍍線216 —倂 切除，以使各導電跡線212間電性獨立。 第6A圖與第6B圖繪示爲對應第5圖根據本發明半導 體封裝基板一較佳實施例之圖案化線路層局部放大示意 圖。 如第6A圖所示，各圖案化線路層位於封裝單元區域 210相鄰的邊界之電鍍線216a、216b，係設計爲一方波形 狀，以匯接導電跡線112再接至電極進行電鍍，且使電鍍 線216a、216b在封裝單元區域210相鄰的邊界於一預定寬 度222內迁迴擺盪，寬度222可以大於分離（singulation)步 驟所使用之切割刀的寬度。 如第6B圓所示，由於圖案化線路層202a可能因疊合 時，與圖案化線路層202b之間產生偏移，使得對應的電 鍍線216a、216b亦產生偏移。雖因切割刀的寬度224有限， 即使圖案化線路層202a、202b之間產生偏移，或切割刀於 分離步驟時產生偏移，只要偏移量不超過寬度222，亦即 切割刀的切割區域，即寬度224涵蓋寬度222任何一邊的 電鍍線216a、216b，即可以使得封裝單元區域210在進行 分離時步驟時，仍可順利將各圖案化線路層上的電鍍線切 斷，防止產品之導電跡線212短路，提高產品良率。 9 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） ------Γ---訂---------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 457^ 457^ A7 6552twf,doc/006 _____B7___ 五、發明說明（i) 第7A圖至第7C圖繪示爲根據本發明半導體封裝基板 其他較佳實施例之圖案化線路層局部放大示意圖。 如第7A圖至第7C圖所示，電鍍線的形狀除了上述的 方波形狀外’只要在封裝單元區域210相鄰的邊界於一預 定寬度222內迂迴擺盪的任何波形都應可應用於本發明 中’舉例而言電鍍線之波形可以設計呈一鋸齒波形316、Z 形波416、或呈一正弦波516。當各圖案化線路層之間產 生偏移’或切割刀於分離步驟時產生偏移，只要與表面圖 案化線路層偏移量不超過寬度222，使得封裝單元區域210 在進行分離時步驟時，皆可順利將各圖案化線路層上的電 鍍線切斷，同樣可達到防止產品之導電跡線212短路，提 闻產品良率的目的。 綜上所述，本發明至少具有下列優點： 1. 本發明半導體封裝基板，僅需將封裝單元區域相鄰 的邊界之電鍍線重新設計，使電鍍線在封裝單元區域相鄰 的邊界於一預定寬度內迂迴擺盪，可在分離製程中，順利 將各圖案化線路層上的電鍍線切除，防止產品導電跡線短 路。 2. 本發明半導體封裝基板，可設計電鍍線之波形呈一 鋸齒波形、方波形狀、Z形波、或呈一正弦波，且在封裝 單元區域相鄰的邊界於一預定寬度內迂迴擺盪。在分離製 程中，即使圖案化線路層之間產生偏移，或切割刀於分離 步驟時產生偏移，仍可順利將各圖案化線路層上的電鍍線 切除，防止產品導電跡線短路，提高產品良率。 10 本紙張尺度適用中_國家標準（CNS)A4規格（210 X 297公釐） — I— iki!l·!·訂 *f!i !線· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 457 457 A7 B7 6552twf.doc/006 五、發明說明（） 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 ---------------— l·— — — 訂---------線- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規袼（210 X 297公釐）A7 B7 457672 6552twf.doc / 006 V. Description of the Invention (,) The present invention relates to a semiconductor package substrate structure, and particularly relates to the use of wave-shaped plating lines to improve the substrate separation process, because Misalignment causes a problem that conductive traces cannot be electrically isolated. As far as the development of semiconductor assembly technology is concerned, due to the increase in the accumulation of semiconductor technology and the design of chips towards functional integration, many System On Chip (SOC) products have been born. At the same time, with the enhancement of semiconductor product data processing capabilities, the number of input / output contacts required by the relatively small wafers has gradually increased, and the size of the wafers has also increased. Therefore, the corresponding construction technology must also meet the needs of this trend, so in recent years High-density, high-footprint semiconductor fabrication products are indeed increasing with each passing day. In high-density semiconductor products, the substrate type carder is a frequently used structural component, which mainly includes two types of stacked compression and build-up. For ball grid array (BGA) substrates, stacked compression-bonded substrates are the mainstream. Because of the influence of the development trend of semiconductor components, the number of contacts on the substrate is gradually increasing, and the substrate wiring density and area are also increasing accordingly, making the substrate manufacturing technology more difficult. Please refer to FIG. 1, which shows a conventional semiconductor package substrate cross section. As shown in FIG. 1, the package substrate 100 includes patterned circuit layers 102 a to 102 d and an insulating layer 106. The insulating layer 106 is respectively disposed between the adjacent patterned circuit layers 102a and 102b, between the patterned circuit layers 102b and 102c, and between the patterned circuit layers 102c and 102d, so as to form an electrical insulation sheet. Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (please read the note f on the back before filling this page) ^ i --- ^ j —Order -------- Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperatives 457672 65 52 twf. Doc / 0 0 6 V. Description of Invention (2) Leaving. The insulating layer 106 has a plurality of conductive vias 108 and conductive micro vias 10 so that the patterned circuit layers 102a to 102d are electrically connected to each other. On the surface of the patterned circuit layers 102a and 102d, solder mask layers Π8 are respectively formed, and by defining the opening 120, a part of the surface of the patterned circuit layers 102a and 102d is exposed to form contacts of the package substrate 100. , Including gold fingers and ball pads. Please refer to FIG. 2, which is a schematic plan view of a conventional semiconductor package substrate corresponding to FIG. 1. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs {Please read the precautions on the back before filling this page) As shown in Figure 2, using the patterned circuit layer 102b as an example, the packaging substrate 100 is composed of several packaging unit areas It is composed of 110, and the packaging unit regions 110 are arranged adjacent to each other, and each packaging unit region 110 has a plurality of conductive traces 112 (trace lines). The semiconductor package substrate 100 uses the conductive traces 112 and the aforementioned Conductive through-holes or conductive micro-holes are used to connect gold fingers and solder ball pads. Due to the ever-increasing requirements for the 100-circuit density of the package substrate, it is not possible to concentrate all the circuits on the surface layer and then serially connect them to the plating lines. Therefore, plating lines must be arranged in each layer of the patterned circuit layer. The plating lines 116 are respectively disposed at borders adjacent to the packaging unit region 110 and are electrically connected to each conductive trace 112 in each packaging unit region 110. The plating line 116 is used to connect the cathode ′ for the plating of the contacts. After the plating is completed, the plating line 116 is cut off to make each conductive trace 12 electrically independent. Please refer to FIG. 3A and FIG. 3B, which are partially enlarged schematic diagrams of the patterned circuit layer of the conventional semiconductor package substrate corresponding to FIG. 2. As shown in Figure 3A, the conventional plating line i16a, n6b is designed to follow a border of the packaging unit area 110 and present a vertical conductive trace. 4 This paper is in accordance with China National Standard (CNS) A4 (210 X 297 Public Love) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 457672 6552twf + doc / 006 V. Description of the Invention (Multi) The line of line 112 is connected to the conductive trace 112 and then connected to the electrode for power mining. As shown in FIG. 3B, when the patterned circuit layer 102a may overlap with the patterned circuit layer 102b due to overlap, at the same time, the plating line 116a and the patterned circuit layer 102b of the patterned circuit layer 102a are caused. The plated line 116b is also offset. When the packaging unit region 11 is subjected to the separation step, the plating line 116a of the patterned circuit layer 102a can only be aligned for cutting, and the width of the cutting blade 120 is limited. If the offset is too large, the cutting blade cannot cover The plating line 116b of the internal patterned circuit layer cannot cut off the plating line 116b on the patterned circuit layer 102b, resulting in a short circuit of the product conductive trace 112, which affects the product yield. Therefore, the object of the present invention is to provide a semiconductor package base plate, which can smoothly cut off the plating lines on each patterned circuit layer even if there is an offset between the patterned circuit layers, preventing short circuit of the conductive traces of the product and improving the product quality. rate. Another object of the present invention is to provide a semiconductor package substrate, which can smoothly cut off the electroplated lines on each patterned circuit layer even if the cutting blade shifts during the separation step, preventing shorting of the conductive traces of the product and improving the yield of the product. . According to the foregoing and other objects of the present invention, a semiconductor package substrate is proposed, which includes a plurality of patterned circuit layers and at least one insulating layer. The insulating layer is disposed between adjacent patterned circuit layers to form electrical isolation. The insulating layer has several conductive through holes so that the patterned circuit layers are electrically connected to each other. The semiconductor package substrate has several packaging unit areas, which are arranged next to each other. The patterned circuit layer is respectively composed of several conductive traces. 5 This paper size applies to the China National Standard (CNS) A4 specification (210 X 297 mm). ) — — — — — — — — — —-^---- l · III ^ ill — — — — — — (Please read the notes on the back before filling this page) A7 B7 6552twf, doc / 006 V. DESCRIPTION OF THE INVENTION (/ f > Furthermore, there is a corrugated plating line at the border of the packaging unit area, the corrugated plating line is electrically connected to the conductive trace of the same layer, and the corrugated plating line is at the border of the packaging unit area. It swings around a predetermined width. According to a preferred embodiment of the present invention, the semiconductor package substrate of the present invention only needs to redesign the plating lines adjacent to the border of the packaging unit area, and the waveform of the plating lines can be designed to have a sawtooth waveform. Square wave shape, Z-shaped wave, or a sine wave, and the plating line swings in a predetermined width around the border of the packaging unit area, even if there is an offset between the patterned circuit layers Or the cutting knife is offset during the separation step, and the plating line on the patterned circuit layer can still be cut off smoothly to prevent short circuit of the product signal and improve the product yield. In order to allow the above and other objects of the present invention, the features and advantages can be It is more obvious and easy to understand. The preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: Figure 1 shows a schematic cross-sectional view of a conventional semiconductor package substrate. Figure 2 shows It is a schematic plan view of a conventional semiconductor package substrate corresponding to FIG. 1. FIG. 3A and FIG. 3B are partial enlarged schematic diagrams of a patterned circuit layer corresponding to the conventional semiconductor package substrate of FIG. 2. FIG. A schematic cross-sectional view of a preferred embodiment of a semiconductor package substrate according to the present invention. FIG. 5 is a schematic plan view corresponding to FIG. 4 according to a preferred embodiment of a semiconductor package substrate of the present invention. FIG. 6A and FIG. Figure semiconducting 6 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. This paper is printed on the national standard (CNS) A4 specification (210 X 297 mm) 457672 6552twf-doc / 006 A7 B7 Explanation of the invention (f) Partially enlarged schematic diagram of the patterned circuit layer of the preferred embodiment of the body package substrate. FIGS. 7A to 7C are partial enlarged diagrams of the patterned circuit layer of the semiconductor package substrate according to other preferred embodiments of the present invention. Schematic representation of the diagram: 100 '200: package substrates 102a ~ 102d, 202a ~ 202d: patterned circuit layers 106, 206: insulating layers 108, 208: conductive through holes 109, 209: conductive micro holes 110, 210: Package unit areas 112, 212: conductive traces 116, 216: plating lines 118, 218: solder mask layers 120, 220: openings 122, 224: cutter width 222: width 316: sawtooth waveform 416: zigzag wave 516: sine Please refer to FIG. 4 for a wave embodiment, which is a schematic cross-sectional view showing a preferred embodiment of a semiconductor package substrate according to the present invention. As shown in FIG. 4, the semiconductor package substrate 200 includes patterned circuit layers 202 a to 202 d and an insulating layer 206. Insulation layer 206 is arranged on 7 paper sizes, applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling this page) Λ ----- r --- Order --------- Line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 457672 6552twf.doc / 006 V. Description of the Invention (Stripped) Between adjacent patterned circuit layers 202a, 202b, patterned circuits Electrical isolation is formed between the layers 202b and 202c and between the patterned circuit layers 202c and 202d. The material of the insulating layer 206 is, for example, glass epoxy resin (FR-4, FR-5) or bismaleimide-triazine (BT). The patterned circuit layers 202a to 202d are formed by, for example, a copper foil layer defined by lithographic etching. The insulating layer 206 has a plurality of conductive through holes 208 and conductive micro holes 209, so that the patterned circuit layers 202a to 202d are electrically connected to each other. The conductive through hole 208 is formed, for example, by using a mechanical drilling method and then through a plugging process. The conductive micro-holes 209 are drilled by laser and then formed by electric plating. A solder mask layer 218 is formed on the surface of the patterned circuit layers 202a and 202d, and a portion of the surface of the patterned circuit layers 202a and 202d is exposed by defining an opening 220 to form contacts of the package substrate 200, including gold fingers. And solder ball pads. The welding mask layer 218 includes ultraviolet-type green paint and heat-hardening type green paint, and the methods for applying green paint include roller coating method, curtain coating method, and screen printing method. (Screen Printing), Dip, and Dry Film Formation. Please refer to FIG. 5, which is a schematic plan view corresponding to FIG. 4 of the preferred embodiment of the semiconductor package substrate according to the present invention. As shown in FIG. 5, the package substrate 200 is composed of a plurality of package unit regions 210, the package unit regions 210 are arranged adjacent to each other, and each package unit region 210 has a plurality of conductive traces 212 respectively, and the package substrate 200 is The conductive traces 212 are used to connect gold fingers and solder ball pads. Due to the increasingly high density requirements of the package substrate 200 circuit, it is not possible to apply all paper circuits to the 8-paper standard (CNS) A4 specification (210 X 297 meals). Ulllliillll ^ i !! !! I line '(Please read the notes on the back before filling this page) 457 457 A7 B7 6552tv; f.doc / 006 V. Description of the invention (q) Concentrated on the surface layer, and then connected to the plating line, so the pattern inside The circuit layer also needs to be equipped with a plating line. The plating lines 216 are respectively disposed at the borders adjacent to the packaging unit area 210, and are electrically connected to each of the conductive traces 212 in each packaging unit area 210. The plating line 216 is used to connect the cathode to perform the plating of the contacts. After the plating is completed, the plating line 216— 倂 is cut off so that the conductive traces 212 are electrically independent. 6A and 6B are partial enlarged schematic diagrams of a patterned circuit layer corresponding to FIG. 5 according to a preferred embodiment of a semiconductor package substrate according to the present invention. As shown in FIG. 6A, the plating lines 216a, 216b at which each patterned circuit layer is located at an adjacent boundary of the packaging unit region 210 are designed in a square wave shape, and the conductive traces 112 are connected to the electrodes for electroplating, and The electroplating lines 216 a and 216 b are moved back and forth within a predetermined width 222 at a boundary adjacent to the packaging unit region 210, and the width 222 may be larger than the width of the cutting blade used in the singulation step. As indicated by circle 6B, the patterned circuit layer 202a may be offset from the patterned circuit layer 202b when superimposed, so that the corresponding plating lines 216a and 216b may also be shifted. Although the width 224 of the cutting blade is limited, even if there is an offset between the patterned circuit layers 202a and 202b, or the cutting blade is offset during the separation step, as long as the offset does not exceed the width 222, the cutting area of the cutting blade That is, the width 224 covers the plating lines 216a, 216b on either side of the width 222, that is, the packaging unit region 210 can still smoothly cut the plating lines on each patterned circuit layer during the separation step, preventing the product from conducting. The trace 212 is short-circuited to improve product yield. 9 This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) ------ Γ --- Order --------- line (Please read the precautions on the back first (Fill in this page again) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 457 ^ 457 ^ A7 6552twf, doc / 006 _____B7___ V. Description of the invention (i) Figures 7A to 7C show the semiconductor package substrate according to the present invention. A partially enlarged schematic diagram of the patterned circuit layer of the preferred embodiment. As shown in FIG. 7A to FIG. 7C, in addition to the square wave shape described above, any shape of the plating line that oscillates within a predetermined width 222 in the border of the packaging unit region 210 should be applicable to this In the invention, for example, the waveform of the plating line can be designed as a sawtooth waveform 316, a zigzag wave 416, or a sine wave 516. When an offset occurs between the patterned circuit layers, or an offset occurs during the separation step of the cutter, as long as the offset from the surface patterned circuit layer does not exceed the width 222, so that the packaging unit region 210 performs the separation step, All of the plating lines on the patterned circuit layers can be cut off smoothly, and the purpose of preventing short circuit of the conductive traces 212 of the product and improving the yield of the product can also be achieved. To sum up, the present invention has at least the following advantages: 1. The semiconductor package substrate of the present invention only needs to redesign the plating line adjacent to the boundary of the packaging unit area, so that the plating line is adjacent to the packaging unit area at a predetermined boundary. The circuitous swing within the width can smoothly cut off the electroplated lines on each patterned circuit layer in the separation process to prevent short circuit of the product's conductive traces. 2. The semiconductor package substrate of the present invention can be designed such that the waveform of the plating line is a sawtooth waveform, a square wave shape, a zigzag wave, or a sine wave. In the separation process, even if there is an offset between the patterned circuit layers, or the cutter is offset during the separation step, the plated lines on each patterned circuit layer can still be cut off smoothly to prevent short circuit of the product's conductive traces and improve Product yield. 10 This paper size is applicable _ National Standard (CNS) A4 specification (210 X 297 mm) — I— iki! L ·! · Order * f! I! Line · (Please read the precautions on the back before filling this page ) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 457 457 A7 B7 6552twf.doc / 006 V. Description of the Invention () Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, anyone familiar with this Artists can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. ---------------— l · — — — Order --------- line- (Please read the notes on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs The paper size printed by the Bureau's Consumer Cooperatives applies the Chinese National Standard (CNS) A4 (210 X 297 mm)