經濟部智慧財產局R工消費合作社印製 457592_B7_ 五、發明説明（） 5 -彳發明領域： 本發明係有關於半導體製造之領域，特別是有關於改 善半導體元件電性之裝置與方法。 5-2發明背景： 積體電路實際上是由數百萬的諸如電晶體、電容器及 電阻器等主動元件及被動元件所组成，為了供給積體電路 較強的計算能力及/或較大的儲存電容量，縮小元件尺寸或 缩小比例以提供較高的元件封裝密度，縮小元件尺寸之重 要特徵為能夠形成具有高品質、高介電常數薄膜的電容及 閘極介電層。 高介電常數的薄膜一般為諸如五氧化二钽及氧化鈦 等陶質薄膜（即金屬氧化物），當沉積這些薄膜時，它們將 趨向於在陰離子（氧氣）的晶格上產生空洞，目前的作法係 利用於含氧氣體中進行退火處理此薄膜而填滿這些空 洞。然而，此一退火處理的執行將造成電容的底層多晶矽 電極氧化，及Μ 0 S電晶體的底層矽基材氧化。此一底層 矽基材的氧化致使二氧化矽薄膜形成，而與高介電常數的 薄膜串接，因此降低了薄膜層之有效介電常數。 如此為了使諸如五氧化二钽之高介電常數薄膜形成 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 公釐） ---------i------IT------.¾ (請先閲讀背面之注意事項再填寫本頁) 457592五、發明説明（） 於底 層 免 障避 阻以 矽用 化， IL的 成要 形重 現是 發間 人之 吾 面 ’ 表 中材 構基 結矽 S 與 ο 料 M t 材 或數 中 常 容電 電介 於高 基 碎 ， 層而 該 之 應 對 及 化 氧 的 面 表 材 成 形 要 須 必 層 障 阻 化 氮 然的 QBa;aJ 減之 縮埃 量25 容 電 效 Ο 有 1 件於 元介 至 埃 的50幸 膜 9 不 薄氏， 數攝而 常於然 電低 。 介 在算 高須預 低必熱 降膜的 會薄程 不矽製 並化的 數I低 常該持 電 ， 保 介外於 低此便 其 。 1 於數成 致常形 以電溫 ， 介低 度效的 薄有度 而化 散氮 擴於 氧 生 於產 對陷 , 缺 層等 矽鍵 化斷 II上 薄加 的更 成 0 形層 下障 度阻 溫的 化 質 氮 品 的良 低不 於一 ’ 為 地言 流 電 漏 如 致 導 陷 缺。 鍵能 斷效 該件 ， 元 上的 面 良 介不 的之 間減 之縮 面量 表容 材電 基及 碎加 與增 碎的 一 基 成矽 形與 上矽 度化 溫IL 的於 低介 當除 相消 於以 法可 方且 ， σ 一 層陷 供障缺 提阻的 要矽上 必化面 有1介 ， 的 間 此實之 因結面 而表 薄材 述 概 及 的I 巨 明 Μ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消f合作社印製 矽於 與膜 膜薄 薄矽 矽化 化 氮 氮一 卜成 善 形 二 發 用本 種據 1 依 ο 法 於 問 之 面 表 方熱 的 ， 面上 介面 表 矽 之 材 基 中 境 環 的 含 包 少 至 2 Η 體 /V 氣氣 氫的 含境 於環 露此 曝’ 係中 膜例 薄施 矽實 化佳 氛較 時一 材之 基明 該發 理本 處於及 2 Ν 本紙浪尺度適用中国國家揉準（CNS) A4規格（210X297公釐） 2 Η 457592 五、發明説明（） 5-4圖式簡單說明： (請先閱讀背面之注意事項再填寫本頁) 第1圖為依據本發明形成半導體元件之製程流程圊。 第2a圖為包含一内層介電物質及具有氮化矽薄膜的底部 電容電極形成於基材上之截面示意圖。 第2b圖顯示於含H2/N2環境中退火處理第2a圖中的基材 之截面示意圖。 第2c圖顯示於第2b圖中的基材上形成一介電薄膜之裁面 示意圖。 第2d圊為顯示退火處理第2c圖中基材上的介電薄膜之截 面示意圖。 第2e圖為顯示於第2d圖中基材上形成上部電容電極之截 面示意圖。 第3圖為說明不同的電極電壓的變化對於具有未執行退火 處理氮化矽層的電容及以Η 2/N2執行退火處理氮化 矽層的電容之漏電流變化圖形。 第 4a圖為具有一氮化矽薄膜形成於基材上之裁面示意 圖。 經濟部智慧財產局員工消費合作社印製 第4b圖為顯示於含N 2/H2環境中執行退火處理第4a圖中 基材之截面示意圖。 第4c圖顯示形成介電薄膜於第4b圖中的基材上之裁面示 意圖。 第4d圖為執行退火處理第4c圖中的基材之載面示意圖。 第4e圖顯示於第4d圖中的基材上形成閘極與源/没極區 本紙張尺度適用中國國家標準（CNS ) Α4Β ( 210X：297公釐） ί 457592 Α7 ______Β7 五、發明説明（） 域之裁面示意圖。 (請先閱讀背面之注意事項再填寫本頁) 5-5發明詳細說明： 本發明描述用於增進半導體元件電性之新穎的方法 與裝置，於下列的詳細說明中描述許多特性諸如特殊的設 備及製程參數，用以對於本發明提供完整的了解。習知技 術者在不脫離本發明之精神範圍内，當可完成本發明所揭 露之結構與製程，於其他實施例中，習知的半導體製程設 備及方法未詳細地描述，以免非必要地混淆本發明。 經濟部智慧財產局員工涓費合作社印製 本發明係一種增進半導體元件電性之形成氣體退火 處理。根據本發明’形成一薄的氮化矽薄膜於矽基材表面 上，例如不限於一單晶矽基材或—多晶電容電極，然後利 用於約攝氏700度與攝氏850度之間的溫度加熱該基材， 然後曝露該基材於至少包含H2的環境中，較好於包含一 形成氣體環境（H W N 2環境）中，以執行退火處理該氮化矽薄 膜。本發明的退火處理步驟是用退火處理以去除介於矽與 氣化矽之間介面上的缺陷，這樣將有助於避免電荷於此介 面上被捕捉’而導致諸如高的漏電流及電容量縮減之不良 的元件效能。此外，於含形成氣體的環境中執行退火處理 該II化矽薄膜，藉著消除薄膜中的缺陷而改善氤化矽薄膜 的品質。藉著改善氤化矽薄膜的品質，其薄度約介於1 0 埃至2 5埃之間的氮化矽層可以提供結實的阻障層。此外， ( CNS ) Α4ϋ#- ( 210Χ297^Α ) 457592 A7 B7 五、發明説明（ 因為該H化石夕薄膜的品質執行一個退火處理步驟而隨 後改善’該退火處理步驟於低於攝氏950度的低氣化矽形 成/皿度’可以使用來縮減製程的熱預算。本發明的退火處 理製程的執行能夠產生高品質高效能的半導體元件，諸如 電容is與電晶體等。 第1圖及第2a~2e圖中，依據本發明揭露—種製 造半導體元件的方法°帛1圓係依據本發明的實施例中描 述製造半導體元件的製程流程_。第2a_2e圖中描述依: 本發明的實施例中形成氣體退火處理用來形成DR_記憶 胞的電♦。第4a-4e圖中係依據本發明的實施例_描述: 形成氣體退火處理製造—個M〇s電晶體。這些特殊的細 節僅用於說明本發明的實施例，非用以限定本發明。''田 (請先聞讀背面之注意事項再填寫本頁j Γ 經濟部智慧財產局員工消費合作社印製 於本發明之—實施例中，基材係用於製造動態隨機存 取記憶體（D R A Μ)記憶胞之基材，例如顯示於第2曰圖中之 基材200,該基材200包含具有一摻雜區域202的習知磊 晶梦基材201及一圖案化的内層介電層2〇4。形成一底部 多晶發電容電極206與擴散區域202接觸，及於ILD 204 之上a該底部的電容電極2 0 6係利用任何習知技術而形 成，例如藉由化學氣相沉積（CVD)全面沉積一多晶矽薄 膜，使用至少包含矽甲烷（SiH4)及H2的反應氣體，然後藉 著習知的微影及餘刻技術將全面沉積的材料圖案化成為 電極。該底部電極206 —般摻雜密度約介於2E20至5E20 本紙張尺度適用中國國家標率（q^iS )八4^格（ r'457592 A7 B7 五、發明説明（） atoms/cm3之間，底部電極206亦可為其他形態的矽電極 電容電極，例如半球型的粒狀多晶矽（HSG)或"rough poly” 電極，但並不受限於此’熟悉該項技術者於其它案例t可 以單晶矽基材2 0 1作為底部電極2 0 6。 如流程圆1 0 0的方塊圖1 0 2中所示之第一步驟，氮化 基材200而形成一薄的氮化矽阻障層205於底部電極206 上，如第2a圖中所示的底部的電極206，該氮化矽阻障層 2 0 5之目的為形成防護底部電極2 0 6的氡化防護阻障層。 因此氡氣無法滲透入多晶矽電極2 〇 6的粒狀邊界，形成氧 化物而導致電容介電物質的有效介電常數減少，及電極電 阻的增加。因為形成於氮化矽薄膜2 0 5中如針孔的缺陷， 可藉著本發明的形成氣體執行退火處理一薄的介於10-25 埃之間的阻障層，而予以消除掉，利用一薄的氮化矽層改 善產能，並以五氧化二钽（Ta2〇5)的高介電常數材料形成於 氬化矽層上縮減負電容衝擊。 一薄的氮化矽薄膜 2 0 5可以藉著任何習知的方法形 成，例如氮化矽薄膜205可藉由將基材200置入一低壓化 學氣相沉積（LPCVD)反應室中的熱氮化反應而形成，並將 該基材200加熱至介於攝氏800度至攝氏950度之間的溫 度，及曝露該基材200於氨氣（NH3)中。然後氨氣（NhU)與 曝露的碎基材表面反應’例如多晶石夕電極2 〇 6而形成氮化 石夕薄膜205。此外’ fil化石夕薄膜205可以藉著將基材200 本紙張尺度適用中國國家標準（CNS ) A4規格（> (請先閲讀背面之注意事項再填寫本頁) -s 經濟部智慧財產局員工消費合作社印製 57592 A7 ____ B7___ 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 曝露於南反應性的氮屑子中，利用位於边離放置基材200 之反應室外之腔室或反應室中微波解離NH3或N2氣體而 形成。因為氮化矽薄膜2 0 5的品質可藉著本發明的形成氣 _體執行退火處理而隨後改善，於相對低而且低於攝氏950 度的氮化溫度中用於形成氮化矽薄膜2 0 5。低的氮化溫度 係因為其縮減製程的熱預算，此製程對於如微處理器，及 高密度的動態隨機存取記憶體之現代高密度積體電路的 製程中’已變得越形重要。 經濟部智慧財產局K工消費合作社印製 其次，如流程圖100中的方塊圖1 〇4中，基材200 於「形成氣體」（N2/H2, forming gas)環境中執行退火處 理，而形成顯示於第2b圊中高品質退火處理的氮化矽層 209»依據本發明該基材200可以藉著放置基材200於快 速的熱處理器（RTP)反應室中而執行退火處理，諸如應用 材料之具有蜂巢狀的來源的RTP Centura，且加熱至介於 攝氏700度與攝氏850度之間，並且將氩氣（H2)與氮氣（N2) 通入反應室中，而建立含體積比90-99%的N2及1-10%的 H2所組成的氣體環境。於RTP反應室中將基材200執行 退火處理約60-1 80秒的時間，可適當地改善此薄氮化矽 阻障層2 0 5之積集度，並改善介於阻障層2 0 5與多晶矽電 極2 06之間的介面。於本發明的一實施例中，「形成氣體」 環境係藉著通入氮氣（N2)1.0s丨m及氩氣（H2>1〇〇sccm至處 理器的反應室中而建立。雖然一快.速熱處理器可完美地用 來實現本發明的形成氣體退火處理的執行，其他習知的裝 -;---------- 本紙張尺度適用中國國家榇準（CNS ) A4規格（2IOX297公釐） 457592 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 置例如爐管亦可用來將基材2 0 0進行退火處理，在利用爐 管退火處理的案例中，基材2 0 0可以於介於攝氏7 0 0度與 攝氏850度之間的溫度，於帶有含形成氣體（N2/H2)環境申 進行退火處理約3 0分鐘的時間。 籍著加熱及曝露該基材2 0 0於氫氣與氮氣中，諸如於 氮化矽薄膜2 0 5中的針洞之缺陷可被消除或大量地縮減， 因此，氧氣無法穿透過氮化矽阻障層2 0 9而氧化該矽電極 206。此外，於形成氣體中執行退火處理該基材 200，提 供可以穿透氮化矽層2 0 5的氫氣消除缺陷，例如介於氮化 矽層2 0 5與多晶矽電極2 0 6之間介面上的斷鍵缺陷，否則 該介面將捕捉電荷造成例如高的漏電流之不良元件效 能。因此，本發明的形成氣體退火處理能夠形成一薄而結 實的氮化矽阻障層2 0 9 ’且於氮化矽阻障層2 0 9及多晶矽 電極206之間形成高品質介面。 經濟部智慧財產局員工消費合作社印製 雖然本發明之較佳實施例係將基材2 0 0於含形成氣體 (H2/N 2)的環境退火處理，其他含氫氣（H2)環境的氣體亦可 用來執行退火處理，例如基材2 0 0可以如同上述利用至少 包含氫氣（H2)與氬氣（Ar)的環境，或一至少包含氫氣（H2) 及氦氣（He)的氣體環境中執行退火處理，此外，於含1 00 %的氫氣所紐·成的氣體環境中將基材200執行退火處理， 亦可得到如上述的好處。 本紙張尺度適用中國圉家標準（CNS ) A4規格（210 X it公釐） 在 57592 Λ7 Β7 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) 其次，如方塊圖106中所示，於基材200上形成一介 電薄膜，於本發明的一實施例中，高介電常數介電薄膜2 0 8 係全面沉積於丨L D 2 0 4上，且執行退火處理的氮化矽薄膜 209形成於基材200之底部電極206上，如第2c圖中所 示。於本發明的較佳實施例中，該介電薄膜為過渡金屬氧 化介電薄膜，例如五氧化二妲及氧化鈦，但不限於此。在 其他的實施例中，介電層208是用鈦摻雜的五氧化二钽薄 膜。此外，介電層208可以是組合的介電薄膜至少包含不 同介電薄膜之堆疊，例如Ta2〇5/Ti〇2/Ta2〇5之堆疊的介電 薄膜。此外，該介電層208可以是諸如鋇銘鈦酸鹽（BST) 及鉛锫鈦酸鹽或鐵電物質的壓電的介電物質。 經濟部智慧財產局員工消費合作社印製 於本發明中的其他實施例中，介電層2 0 8可以是諸如 二氧化矽及氮氧化矽的氧化矽介電物質，及氧化矽的组合 介電堆疊，及諸如習知的ΟΝΟ與NO與氬化氧化矽之氮化 矽薄膜。該氧化物的製造為習知的，且可用於製造閘極介 電層及電容介電物質中，例如，低溫二氡化矽薄膜可以藉 著使用諸如T E 0 S的矽源及Ο 2的氧氣源的化學氣相沉積 而形成- 為了形成一介電層208於基材200上，該基材可以放 進諸如一應用材料 CVD單晶片反應器之熱處理反應室 中，然後當於反應室中的壓力縮減至預定的沉積壓力時， 加熱該基材至預定的沉積溫度，然後將沉積氣體通入反應 本紙浪尺度適用中國國家標準i cns ) A4規格（2ΐοχϋ:釐） A7 B7 457592 五、發明説明（）Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, R-Consumer Cooperative, 457592_B7_ V. Description of Invention (5)-Field of Invention: The present invention relates to the field of semiconductor manufacturing, and in particular to a device and method for improving the electrical properties of semiconductor components. 5-2 Background of the Invention: Integrated circuits are actually composed of millions of active and passive components such as transistors, capacitors, and resistors. In order to provide integrated circuits with strong computing power and / or large Storage capacitance, reduction of component size or reduction ratio to provide higher component packaging density, an important feature of reduction in component size is the ability to form capacitors and gate dielectric layers with high quality, high dielectric constant films. High dielectric constant films are generally ceramic films (ie, metal oxides) such as tantalum pentoxide and titanium oxide. When these films are deposited, they will tend to create voids in the anion (oxygen) lattice. At present The method is to fill the voids by annealing the film in an oxygen-containing gas. However, the execution of this annealing process will cause the underlying polycrystalline silicon electrode of the capacitor to oxidize and the underlying silicon substrate of the MOS transistor to oxidize. The oxidation of this underlying silicon substrate results in the formation of a silicon dioxide film, which is connected in series with a film having a high dielectric constant, thereby reducing the effective dielectric constant of the film layer. Therefore, in order to form a high dielectric constant film such as tantalum pentoxide, the Chinese paper standard (CNS) A4 specification (210 X mm) is applied to this paper standard --------- i ------ IT ------. ¾ (Please read the notes on the back before filling in this page) 457592 V. Description of the invention () The barrier-free avoidance at the bottom is made of silicon, and the essential reproduction of IL is the hairpin The surface of the surface of the table's structure is composed of silicon S and ο material M t material, or the normal capacity of electricity is between the high base and the layer, and the corresponding surface and the formation of oxygen surface material must be barrier to nitrogen Of course, QBa; aJ is reduced by 25 Angstroms. Capacitance and electric efficiency 〇 There are 1 pieces of 50 fortunate film from Yuan Jie to Angstrom 9 not thin, and the number is usually low. If the calculation is high, the temperature must be low, the temperature of the falling film will be thin, and the number of silicon will not be low. I should always hold the power, and keep it low. 1 In the normal state, the electrical temperature and the low-efficiency thin nitrogen are diffused in the form of oxygen, which is generated by the oxygen generated in the depression, lack of layers and other silicon bond faults II. The degree of barrier and temperature resistance of chemical nitrogen products is not less than one ', which is caused by the leakage of electric current. The key can break the piece, the surface of the surface is reduced, the surface of the surface is reduced, and the surface of the material is electric, and the base of the addition and increase is broken into a silicon shape and the upper siliconization temperature IL. Can be eliminated by the method, and σ is a layer of depression and resistance. There must be 1 surface on the silicon surface. In this case, due to the surface, the sheet material is summarized as I. Ju Ming M (please (Please read the notes on the back before filling in this page) The staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, the cooperative, printed silicon on the thin film and thin silicon silicide, silicon nitrogen, nitrogen and nitrogen. The surface surface is hot, and the surface interface surface is made of silicon. The material in the environment ring contains as little as 2 Η body / V gas / hydrogen. The environment containing the environment is exposed to the environment. The basis of the previous material is that the paper is in the 2nd position. The paper scale is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) 2 Η 457592 5. Description of the invention () 5-4 Schematic illustration: (Please read the precautions on the back before filling out this page) Picture 1 is According to the present invention is formed in a semiconductor element manufacturing process flow of the pigsty. Figure 2a is a schematic cross-sectional view of a bottom capacitor electrode including an inner dielectric substance and a silicon nitride film formed on a substrate. Figure 2b shows a schematic cross-section of the substrate in Figure 2a after annealing in an H2 / N2 containing environment. Fig. 2c is a schematic diagram showing a cut surface of a dielectric film formed on the substrate in Fig. 2b. Figure 2d 圊 is a schematic cross-sectional view showing the dielectric film on the substrate in Figure 2c of the annealing process. Figure 2e is a schematic cross-sectional view showing the upper capacitor electrode formed on the substrate in Figure 2d. Fig. 3 is a graph illustrating changes in the leakage current of a capacitor having a silicon nitride layer that has not been annealed and a capacitor having a silicon nitride layer that has been annealed with Η 2 / N2, according to different electrode voltage changes. Figure 4a is a schematic cut-out view of a silicon nitride film formed on a substrate. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 4b is a schematic cross-sectional view of the substrate shown in Figure 4a when annealing is performed in an environment containing N 2 / H2. Fig. 4c shows a schematic cut-away view of the dielectric film formed on the substrate in Fig. 4b. FIG. 4d is a schematic view of the carrying surface of the substrate in FIG. 4c when the annealing process is performed. Figure 4e shows the formation of gate and source / non-electrode regions on the substrate in Figure 4d. The paper dimensions are applicable to the Chinese National Standard (CNS) Α4Β (210X: 297 mm) ί 457592 Α7 ______ Β7 V. Description of the invention () Schematic drawing of the domain. (Please read the notes on the back before filling out this page) 5-5 Detailed description of the invention: This invention describes a novel method and device for improving the electrical properties of semiconductor components. In the following detailed description, many characteristics such as special equipment are described. And process parameters to provide a complete understanding of the invention. Those skilled in the art can complete the structures and processes disclosed in the present invention without departing from the spirit of the present invention. In other embodiments, the conventional semiconductor process equipment and methods are not described in detail to avoid unnecessary confusion. this invention. Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs. The present invention is a forming gas annealing treatment for improving the electrical properties of semiconductor devices. According to the present invention, a thin silicon nitride film is formed on the surface of a silicon substrate, such as not limited to a single crystal silicon substrate or a polycrystalline capacitor electrode, and then used at a temperature between about 700 degrees Celsius and 850 degrees Celsius. The substrate is heated, and then the substrate is exposed to an environment containing at least H2, preferably in a gas-forming environment (HWN2 environment), to perform annealing treatment on the silicon nitride film. The annealing treatment step of the present invention is to use an annealing treatment to remove defects on the interface between silicon and vaporized silicon, which will help to prevent charge from being trapped on this interface and cause high leakage current and capacitance. Reduced poor component performance. In addition, the silicon dioxide film is annealed in an environment containing a formation gas, and the quality of the silicon oxide film is improved by eliminating defects in the film. By improving the quality of the silicon nitride film, a silicon nitride layer having a thickness between about 10 angstroms and 25 angstroms can provide a strong barrier layer. In addition, (CNS) Α4ϋ #-(210 × 297 ^ Α) 457592 A7 B7 V. Description of the invention (Because the quality of the H-fossil film performs an annealing treatment step and subsequently improves it, the annealing treatment step is at a temperature lower than 950 degrees Celsius The formation of siliconized silicon can be used to reduce the thermal budget of the process. The implementation of the annealing process of the present invention can produce high-quality and high-performance semiconductor components such as capacitors and transistors. Figure 1 and 2a ~ In the figure 2e, a method for manufacturing a semiconductor element is disclosed according to the present invention. The circle 1 describes the process flow for manufacturing a semiconductor element according to the embodiment of the present invention. The description in the figure 2a_2e is based on: formed in the embodiment of the present invention The gas annealing process is used to form the electricity of the DR_memory cell. Figures 4a-4e are according to the embodiment of the present invention. Description: The gas annealing process is used to manufacture a Mos transistor. These special details are only used for Explain the embodiments of the present invention, not to limit the present invention. '' Tian (Please read the notes on the back before filling out this page. J Mingzhi—In the embodiment, the substrate is a substrate for manufacturing a dynamic random access memory (DRA M) memory cell, such as the substrate 200 shown in the second figure. The substrate 200 includes a substrate The conventional epitaxial substrate 201 of the region 202 and a patterned inner dielectric layer 204 are formed to form a bottom polycrystalline capacitor electrode 206 in contact with the diffusion region 202, and above the ILD 204 a the capacitor electrode 2 at the bottom The 0 6 series is formed by any conventional technique, for example, a polycrystalline silicon thin film is completely deposited by chemical vapor deposition (CVD), a reaction gas containing at least silicon methane (SiH4) and H2 is used, and then by conventional lithography and The remaining technology is used to pattern the fully deposited material into an electrode. The bottom electrode 206 is generally doped at a density between 2E20 and 5E20. This paper scale is applicable to China ’s national standard (q ^ iS) of 8 ^^ (r'457592 A7). B7 V. Description of the invention () Between atoms / cm3, the bottom electrode 206 may also be a silicon electrode capacitor electrode in other forms, such as a hemispherical granular polycrystalline silicon (HSG) or "rough poly" electrode, but it is not limited. Here's the person familiar with the technology In this case, a single crystal silicon substrate 2 01 can be used as the bottom electrode 2 06. As the first step shown in the block diagram of the flow circle 100, the substrate 200 is nitrided to form a thin nitrogen. The siliconized silicon barrier layer 205 is on the bottom electrode 206, like the bottom electrode 206 shown in FIG. 2a. The purpose of the silicon nitride barrier layer 205 is to form a siliconized protective barrier that protects the bottom electrode 206. Therefore, radon cannot penetrate the granular boundary of the polycrystalline silicon electrode 206, forming an oxide, which causes the effective dielectric constant of the capacitive dielectric substance to decrease, and the electrode resistance to increase. Defects such as pinholes formed in the silicon nitride film 2005 can be eliminated by using the formation gas of the present invention to perform a annealing treatment of a thin barrier layer between 10 and 25 angstroms, using A thin silicon nitride layer improves productivity, and a high dielectric constant material of tantalum pentoxide (Ta205) is formed on the silicon argon layer to reduce the negative capacitance impact. A thin silicon nitride film 205 can be formed by any conventional method. For example, the silicon nitride film 205 can be formed by placing the substrate 200 in hot nitrogen in a low pressure chemical vapor deposition (LPCVD) reaction chamber. It is formed by chemical reaction, and the substrate 200 is heated to a temperature between 800 ° C and 950 ° C, and the substrate 200 is exposed to ammonia (NH3). The ammonia gas (NhU) then reacts with the exposed surface of the crushed substrate, such as a polycrystalline silicon electrode 206 to form a nitrided silicon film 205. In addition, the fil fossil evening film 205 can be adapted to the Chinese National Standard (CNS) A4 specification by applying the 200 paper size of the substrate (> (Please read the precautions on the back before filling out this page) -s Staff of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the Consumer Cooperative 57592 A7 ____ B7___ V. Description of the invention () (Please read the precautions on the back before filling this page) Exposure to the South Reactive Nitrogen Filings. Formed by microwave dissociation of NH3 or N2 gas in the chamber or reaction chamber. Because the quality of the silicon nitride film 2 05 can be subsequently improved by performing the annealing treatment on the formation gas of the present invention, it is relatively low and lower than 950 ° C It is used to form a silicon nitride film at a nitriding temperature of 205. The low nitriding temperature is due to the thermal budget of the reduced process. This process is useful for, for example, microprocessors and high-density dynamic random access memories. The process of modern high-density integrated circuits has become more and more important. It is printed by the K Industrial Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. As shown in block diagram 104 in flowchart 100, the substrate 200 is In the "N2 / H2, forming gas" environment, an annealing treatment is performed to form a high-quality annealing silicon nitride layer 209 shown in 2b 圊. According to the present invention, the substrate 200 can be quickly placed by placing the substrate 200 on the substrate. Heat treatment (RTP) reaction chamber to perform an annealing process, such as RTP Centura with a honeycomb-like source of applied materials, and heated to between 700 ° C and 850 ° C, and argon (H2) and Nitrogen (N2) is introduced into the reaction chamber to establish a gas environment containing 90-99% by volume of N2 and 1-10% of H2. The substrate 200 is annealed in the RTP reaction chamber for about 60-1 A time of 80 seconds can appropriately improve the accumulation degree of the thin silicon nitride barrier layer 205, and improve the interface between the barrier layer 205 and the polycrystalline silicon electrode 206. In the embodiment, the "forming gas" environment is established by passing nitrogen (N2) 1.0sm and argon (H2 > 100sccm) into the reaction chamber of the processor. Although a fast. Perfectly used to implement the formation gas annealing process of the present invention, other conventional equipment-; -------- -This paper size applies to China National Standard (CNS) A4 (2IOX297 mm) 457592 A7 B7 V. Description of the invention () (Please read the notes on the back before filling this page) For example, the furnace tube can also be used to The substrate 200 is annealed. In the case of furnace tube annealing, the substrate 200 can be at a temperature between 700 ° C and 850 ° C with a formation gas (N2 / H2) The environmental treatment is performed for about 30 minutes. By heating and exposing the substrate to hydrogen and nitrogen, defects such as pinholes in the silicon nitride film can be eliminated or greatly reduced. Therefore, oxygen cannot penetrate through the silicon nitride resistor. The barrier layer 209 oxidizes the silicon electrode 206. In addition, the substrate 200 is annealed in the formation gas to provide hydrogen that can penetrate the silicon nitride layer 205 to eliminate defects, such as the interface between the silicon nitride layer 205 and the polycrystalline silicon electrode 206. Defective bond breaking, otherwise the interface will trap charge and cause poor component performance such as high leakage current. Therefore, the formation gas annealing process of the present invention can form a thin and strong silicon nitride barrier layer 209 'and form a high-quality interface between the silicon nitride barrier layer 209 and the polycrystalline silicon electrode 206. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Although the preferred embodiment of the present invention is an annealing treatment of the substrate 200 in an environment containing a forming gas (H2 / N 2), other gases containing a hydrogen (H2) environment also It can be used to perform the annealing process. For example, the substrate 2 0 can be used as described above in an environment containing at least hydrogen (H2) and argon (Ar), or in a gas environment containing at least hydrogen (H2) and helium (He). The annealing treatment, in addition, performing the annealing treatment on the substrate 200 in a gas environment containing 100% hydrogen can also obtain the benefits as described above. This paper size is in accordance with Chinese Standard (CNS) A4 (210 X it mm) in 57592 Λ7 Β7 V. Description of the invention () (Please read the notes on the back before filling this page) Second, as shown in block diagram 106 As shown, a dielectric film is formed on the substrate 200. In one embodiment of the present invention, a high-k dielectric film 2 0 8 is completely deposited on LD 2 0 4 and annealed nitrogen is performed. A siliconized film 209 is formed on the bottom electrode 206 of the substrate 200, as shown in FIG. 2c. In a preferred embodiment of the present invention, the dielectric film is a transition metal oxide dielectric film, such as hafnium pentoxide and titanium oxide, but is not limited thereto. In other embodiments, the dielectric layer 208 is a thin film of tantalum pentoxide doped with titanium. In addition, the dielectric layer 208 may be a stacked dielectric film including at least a stack of different dielectric films, such as a stacked dielectric film of Ta205 / Ti〇2 / Ta205. In addition, the dielectric layer 208 may be a piezoelectric dielectric substance such as barium titanate (BST) and lead hafnium titanate or a ferroelectric substance. Printed in other embodiments of the present invention by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the dielectric layer 208 may be a silicon oxide dielectric such as silicon dioxide and silicon oxynitride, and a combined dielectric of silicon oxide Stack, and conventional silicon nitride films such as ONO and NO and argon silicon oxide. The manufacture of this oxide is conventional and can be used in the manufacture of gate dielectrics and capacitor dielectrics. For example, low-temperature silicon dioxide films can be made by using a silicon source such as TE 0 S and oxygen of 0 2 The source is formed by chemical vapor deposition-in order to form a dielectric layer 208 on a substrate 200, the substrate may be placed in a heat treatment reaction chamber such as an applied material CVD single wafer reactor, and then used in the reaction chamber. When the pressure is reduced to a predetermined deposition pressure, the substrate is heated to a predetermined deposition temperature, and then the deposition gas is passed into the reaction paper. The scale of the paper is applicable to Chinese national standards i cns) A4 specifications (2ΐοχϋ:）) A7 B7 457592 ()
室中，並形成一介電層Q 經濟部智慧財產局員工消費合作社印製 於本發明的較佳實施例中，介電物質2 0 8是五氧化二 组（T a2〇5 )，藉著熱化學氣相沉積而全面沉積一五氧化二錄 (Ta2〇5)介電薄骐，沉積氣體混合物至少包含一妲源，諸如 TAETO【Ta(OC2H5) 5】及 TAT-DMAE【Ta(OC2Hs) Λ (OCHCH2N ( CH3) 2 )】及諸如02或Ν20的氧氣源衧以 通入沉積反應室，當該基材加熱至介於攝氏300度與攝氏 5 0 0度之間的沉積溫度，且該反應室維持在介於〇 . 5 Τ ◦「「 至1 0 To rr之間的沉積壓力時，於加熱的基材上沉積氣體 的流量導致金屬有機含钽的先驅物熱分解，隨後沉積成五 氡化二钽薄膜。當〇2或N20以0.3SLM至1.0SLM的速準 通入反應室中，於一實施例中，TAET0或TAT-DMAE於 約每分鐘10毫克至50毫克之間的速率通入反應室中。 TAETO及TAT-DMAE可以藉著直接的液體注入而提供’ 或於進入沉積反應室之前利用一發泡器氣化。諸如N 2 ' Η 2 及He的載氣以介於0.5 SLM至2.0 SLM的速率之間，可 以用來傳送氣化的TAETO或TAT-DMAE液體至沉積反應 室中，持續沉積過程直到預定厚度的介電薄膜208形成， 一具有約50埃至200埃之間厚度的五氧化二钽（Ta2〇 5)介 電薄膜提供一合適的電容介電物質° 其次，如於流程圖1〇〇的方塊圖1〇8中所示’若需要 可將介電薄膜208以退火處理，而形成經過退火處理的介 本紙張尺度適用中國國家標準（CNS ) A4規格（2i〇X297公釐 457592 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（) 電層210，如第2d圖中所示。介電層210可以藉著任何 習知的及適合的退火處理製程進行快速熱退火，或於含至 少包含如〇2或N20之含氧的氣體環境中，於介於攝氏800 度至攝氏8 5 0度的溫度之間進行一爐管退火處理。此外， 介電薄膜208可於高反應性氧原子中進行退火處理，於退 火處理過中，藉著與基材2 0 0所放置的反應室處分開或遠 離的反應室中，以微波分解諸如〇2的含氧氣體所產生的 高度反應氧氣原子。利用遠端產生的反應性氡原子進行退 火處理，特別適合於退火處理過渡金屬氧化介電薄膜，諸 如五氡化二鈕（Ta205)介電物質。 本發明的下一步驟為完成元件的製程，如於流程圖 1 0 0的方塊圖1 1 〇中所示。如第2 e圖中所示，例如’一 上部的電容電極212形成於退火處理過的介電層210之 上，任何習知的技術可以用來形成上部的電極2彳2，包含 全面沉積一多晶矽薄膜，或諸如ΤΊ N的金屬薄膜於退火處 理過的介電薄膜2 1 0之上，然後利用習知的微影及蝕刻技 術將電極薄膜及介電層圖案化。 第3圖係描述於形成氣體環境中執行退火處理氮化矽 層205與底部的電極206，其如何將所製造電容的電性提 高的圖形。第3圖描述302及304兩圖形’此圖形顯示漏 電流如何隨著電容之不同的上部電極電壓而變動，該電容 具有一結構至少包含一摻雜多晶矽底部電極、一厚度約2 0 -12- (請先閡讀背面之注意事項再填寫本頁) 装In the room, a dielectric layer is formed. The consumer cooperative of the employee of the Intellectual Property Bureau of the Ministry of Economy is printed in a preferred embodiment of the present invention. The dielectric substance 208 is the second group of pentoxide (T a205). Thermal chemical vapor deposition is used to fully deposit a dielectric thin film of tantalum pentoxide (Ta205). The deposition gas mixture contains at least one tritium source, such as TAETO [Ta (OC2H5) 5] and TAT-DMAE [Ta (OC2Hs). Λ (OCHCH2N (CH3) 2)] and an oxygen source such as 02 or N20 to pass into the deposition reaction chamber. When the substrate is heated to a deposition temperature between 300 ° C and 500 ° C, and the When the reaction chamber is maintained at a deposition pressure between 0.5 Torr and 10 Torr, the flow rate of the deposition gas on the heated substrate causes the metal organic tantalum precursor to be thermally decomposed, and subsequently deposited into five Tritide thin film. When 〇2 or N20 pass into the reaction chamber at a rate of 0.3SLM to 1.0SLM, in one embodiment, the rate of TAET0 or TAT-DMAE is about 10 mg to 50 mg per minute. Into the reaction chamber. TAETO and TAT-DMAE can be provided by direct liquid injection 'or The chamber is previously gasified by a foamer. Carrier gases such as N 2 'Η 2 and He can be used to transfer the vaporized TAETO or TAT-DMAE liquid to the deposition reaction at a rate between 0.5 SLM and 2.0 SLM. In the chamber, the deposition process is continued until a predetermined thickness of the dielectric film 208 is formed. A tantalum pentoxide (Ta205) dielectric film having a thickness between about 50 Angstroms and 200 Angstroms provides a suitable capacitive dielectric substance. As shown in the block diagram 108 of the flowchart 100, 'If necessary, the dielectric thin film 208 may be annealed to form an annealed dielectric paper. The paper size is applicable to the Chinese National Standard (CNS) A4 specification ( 2i × 297mm 457592 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Electrical layer 210, as shown in Figure 2d. The dielectric layer 210 can be used by any conventional and suitable The annealing process is performed by rapid thermal annealing, or in a furnace tube annealing process at a temperature between 800 ° C and 850 ° C in an atmosphere containing oxygen containing at least 0 2 or N20. In addition, The dielectric film 208 can be highly reactive The annealing process is performed in the atom. During the annealing process, the highly reactive oxygen generated by the oxygen-containing gas such as 0 2 is decomposed by microwaves in a reaction chamber separated from or separated from the reaction chamber where the substrate 200 is placed. Atoms. The use of reactive erbium atoms generated at the far end for annealing treatment is particularly suitable for annealing treatment of transition metal oxide dielectric films, such as pentafluoride (Ta205) dielectric materials. The next step of the present invention is to complete the device. The process is shown in the block diagram 11 of the flowchart 100. As shown in Figure 2e, for example, 'an upper capacitor electrode 212 is formed on the annealed dielectric layer 210, any conventional technique can be used to form the upper electrode 2 彳 2, including A polycrystalline silicon film, or a metal film such as TN, is placed on the annealed dielectric film 210, and then the electrode film and the dielectric layer are patterned by conventional lithography and etching techniques. Fig. 3 is a pattern describing how the silicon nitride layer 205 and the bottom electrode 206 are annealed in a gas-forming environment to improve the electrical properties of the capacitors produced. Figure 3 depicts two graphs, 302 and 304. This graph shows how the leakage current varies with different upper electrode voltages of a capacitor. The capacitor has a structure that includes at least one doped polysilicon bottom electrode, and a thickness of about 2 0 -12- (Please read the notes on the back before filling this page)
'•IT Λ 本紙張尺度通用中國國家橾隼（CNS ) A4規格（210X297公釐） 457592 at B7 經濟部智慧財產局員工消費合作社印製'• IT Λ This paper is standard Chinese National Standard (CNS) A4 (210X297 mm) 457592 at B7 Printed by the Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs
五、發明説明 ) I I I 埃 的 氮 化 矽 阻 障 層 ，及 已 於 Ν 2〇 中 執 行 退 火 處 理 約 30 秒 I I I 的 時 間 ，厚 度 約 1 00埃 的 五 氧 化 二 钽 介 物 ftfr 以 及 — 氮 I I 化 欽 上 部 電 極 。於 302 圖 中 ，該氮化矽薄膜/ 多 晶 矽 電 極 未 請 I ! 以 形 成 氣 體 來 處 理 ，由 302 圖 中 可 見 1 該 電 容 具 有 好 的 漏 閱 I ] 電 流 Ϊ 但 只 有 9ΐΡ/μΓη2 的 低 電 容 量 7 該 低 電 容 量 係 由 於 形 面- 之 I I I 成 氧 化 矽 層 介 於 氮化 ;夕 薄 膜 與 多 晶 石夕 電 & 之 間 0 該 氧 化 事* I I 障 項 I 物 的 形 成 係 因 為 氮 化矽 阻 層 具 有 不 良 的 完 整 性 ί 於 五 氧 再 I I 填 ~"J 化 二 鉅 執 行 -退火處理 步 驟 之 過 程 中 使得氧氣 擴 散 穿 I 透 1 且 造 成 於 氮 化 矽層 之 下 二 氧 化 矽 的 形 成 〇 二 氧 化 矽 具 貝 __- I I 有 一 相 對 低 的 常 數 ，當 其 置 於 與 的 介 電 常 數 過 渡 金 屬 氧 I I 化 介 電 物 質 串 接 時 ，導 致 電 容 的 有 效 電 容 量 縮 減 Q 另 一 方 I I 面 J 圖 304 顯 示 — 電容 的 電 性 其 中 多 晶 矽 電 極 及 氮 化 矽 I 訂 層 已 利 用 本 發 明 的 形成 氣 體 退 火 處 理 1 如 圖 304 中 所 示 > I I 以 形 成 氣 體 處 理 過的電容與未處理過 的 電 容 電 極 具 有 相 I [ 同 的 漏 電 流 ( 該 處 理過 的 電 容 顯 示 比 未 處 理 過 的 電 容 稍 南 - I I 的 電 性 係 由 於 對五 氧 化 二 薄 膜 執 行 退 火 處 理 的 退 火 溫 度 稍 低 ) C 該 以 形成 氣 體 退 火 處 理 的 電 容 具 有 顯 者 地 I | 電 容 量 1 1 f F/μπη 2 該形 成 氣 體 處 理 過 的 電 容 具 有 較 電 容 I I 量 > 因 為 氮化矽 阻 章層 經 由『 升多成氣體」 的 作 用 而 較 結 實 1 I | 因 此 氧 氣 無 法於五氧化- 二组退 火 理 過 程 中 穿 透 該 氮 化 I I 矽 阻 障 層 0 因 為 氧 氣穿 透 已 被 消 除 或 實 質 上 被 縮 減 > 氧 化 I I 矽 層 因 此 不 能 形 成 於氛 化 矽 薄 膜 與 多 晶 矽 電 極 之 間 〇 於 it I i 方 式 中 一 形 ，成氣體處理過的 t 容 比 未 處 理 過 的 電 容 具 有 I I 較 高 的 電 容 量 此 外， 本 發 明 的 形 成 氣 體 退 火 處 理 改 善 氮 I I i -13 I I 本紙張尺度適用中國國家標準（CNS) A4規格（210X 297公釐} A7 457592 B7 五、發明説明（） 化矽層與多晶矽閘極電極之間的介面，有助於改善電容 量。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 如第4 a - 4 e圖中顯示的本發明之另一實施例中，本發 明之形成氣體退火處理係用於製造一金屬絕緣半導體 (Μ 1 S )電晶體。如第4 a圖中所示的第一步驟，氮化一單晶 矽基材402，以形成一薄的1 0-25埃的氮化矽薄膜401於 基材402上。然後如第4b圊中所示，於如上述之形成氣 體（N2/H2)中進行退火處理該基材400，以形成一結實的經 退火處理的氮化矽阻障層4 0 3，並消除存在於矽基材與氮 化石夕之間介面上的缺陷。其次，如第 4 c圖中所示* 一介 電層 404形成於經退火處理的氮化矽層 403上，介電層 4 0 4可以是任何的介電薄膜，例如C V D沉積二氧化矽薄 膜，或過渡金屬氧化薄膜，例如五氧化二妲，介電物質4 0 4 一般具有介於20埃至100埃之間的厚度。然後如第4c圖 中所示，介電薄膜4 0 4若需要可以退火處理，然後一閘極 電極材料例如多晶·ε夕或金屬或其組合物，可以全面地沉積 於經退火處理的介電物質406之上，然後如第4d圖中所 示，以習知的微影及蝕刻技術圊案化為一閘極電極4 0 8。 然後一對源/汲極區域4 1 0利用習知的離子植入或固態源 擴散技術形成於閘極電極4 0 8的兩側，以完成Μ Ο S元件 的製造。 因此，增強半導體元件的電性效能之方法與裝置已描 述於此。 _；_14^_ 本紙張尺度適用中國國家標準（CNS ) Α4現格（210Χ297公釐)5. Description of the invention) III Angstrom silicon nitride barrier layer, and tantalum pentoxide intermediary ftfr with thickness of about 100 angstroms and annealing time of about 30 seconds III in NH 2 and-nitrogen II Qin upper electrode. In the figure 302, the silicon nitride film / polycrystalline silicon electrode is not treated with I! To form a gas, as can be seen in the figure 302. 1 This capacitor has a good misreading. I] Current Ϊ, but only 9ΐP / μΓη2 low capacitance 7 The low-capacitance is due to the formation of the III-silicon oxide layer between nitride; the thin film and polycrystalline silicon & 0 the oxidation event * II barrier I the formation of the object is due to the silicon nitride resistance The layer has poor integrity. During the filling of the pentoxide and II, the process of annealing and annealing allows oxygen to diffuse through the substrate and cause the formation of silicon dioxide under the silicon nitride layer. Silicon dioxide __- II has a relatively low constant. When it is placed in series with a dielectric constant transition metal oxide II-type dielectric substance, it causes the effective capacitance of the capacitor to decrease Q. The other side is J-plane II. 304 display — Capacitance The polycrystalline silicon electrode and the silicon nitride I layer have been annealed using the formation gas of the present invention 1 as shown in Figure 304 > II to form a gas-treated capacitor and an untreated capacitor electrode having a phase I [The same leakage current (the treated capacitor shows slightly souther than the untreated capacitor-the electrical properties of the II are slightly lower due to the annealing temperature of the annealing process on the pentoxide film) With a prominent ground I | Capacitance 1 1 f F / μπη 2 The gas-treated capacitor has a larger capacity than the capacitance II > Because the silicon nitride barrier layer passes the function of "liters into gas", it is stronger 1 I | Oxygen cannot penetrate the nitride II silicon barrier layer during the pentoxide-two-annealing process. 0 Oxygen penetration has been eliminated or substantially reduced > The oxide II silicon layer cannot be formed in the atmosphere Between the siliconized film and the polycrystalline silicon electrode, it is formed in the it I i method, and the gas-treated t capacitance has a higher capacitance than the untreated capacitor. In addition, the gas-annealing treatment of the present invention improves nitrogen II. i -13 II This paper size applies Chinese National Standard (CNS) A4 (210X 297 mm) A7 457592 B7 V. Description of the invention () The interface between the siliconized layer and the polysilicon gate electrode helps to improve the capacitance . (Please read the precautions on the back before filling out this page.) In another embodiment of the present invention, as shown in Figures 4a-4e, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the forming gas annealing process of the present invention It is used to make a metal-insulated semiconductor (M 1 S) transistor. As shown in the first step in Fig. 4a, a single crystal silicon substrate 402 is nitrided to form a thin 10-25 angstrom silicon nitride film 401 on the substrate 402. The substrate 400 is then annealed in the formation gas (N2 / H2) as described in Section 4b (ii) to form a strong annealed silicon nitride barrier layer 4 0 3 and eliminates it. Defects in the interface between the silicon substrate and the nitride nitride. Secondly, as shown in Figure 4c *, a dielectric layer 404 is formed on the annealed silicon nitride layer 403. The dielectric layer 404 can be any dielectric film, such as a CVD-deposited silicon dioxide film , Or a transition metal oxide film, such as osmium pentoxide, the dielectric substance 4 0 4 generally has a thickness between 20 angstroms and 100 angstroms. Then, as shown in FIG. 4c, the dielectric thin film 4 0 4 can be annealed if necessary, and then a gate electrode material such as polycrystalline or epsilon or a metal or a combination thereof can be completely deposited on the annealed dielectric The electrical material 406 is then converted into a gate electrode 408 using conventional lithography and etching techniques as shown in FIG. 4d. Then a pair of source / drain regions 4 10 are formed on both sides of the gate electrode 408 using a conventional ion implantation or solid-state source diffusion technique to complete the fabrication of the MEMS device. Therefore, methods and devices for enhancing the electrical performance of semiconductor devices have been described herein. _; _14 ^ _ This paper size applies to the Chinese National Standard (CNS) Α4 is now (210 × 297 mm)