TW456101B - Treatment method and apparatus for power source disturbance caused by electromagnetic interference - Google Patents

Abstract

A kind of treatment apparatus for power source disturbance caused by the electromagnetic interference can be used in a power-on reset circuit of an electronic system, in which the treatment apparatus includes a logic circuit and a judgment circuit. The initial logic value of the status signal output by a logic circuit is the first logic value, and the first logic value is changed to the second logic value when the logic value of the input control signal is changed. After that, the logic value stays firmly at the second logic value without being affected by the control signal. The judgment circuit is used to judge the first time of power-on reset action and directly deliver the reset signal when a reset signal is received and the status signal is at the second logic value. Through the change of logic value for the control signal, the status signal is changed to the second logic value. When the reset signal is received and the status signal is at the second logic value, an error action caused by electromagnetic interference is judged and the delivery of reset signal is ceased. At the same time, a repair procedure can also be switched on to repair the effects of system caused by electromagnetic interference.

Description

456101 V. Description of the invention (l) — The present invention relates to a technology for preventing electromagnetic interference, in particular to a power-on reset circuit for generating a power-on reset signal (P〇wer_〇n Reset) in general electronic devices, to prevent In the process of using the electronic device, it is caused by an erroneous electromagnetic interference that causes a reset signal to be mistakenly caused to restart. When the computer system or various electronic devices are connected to the power supply and just started, the product uses a reset signal to connect the microprocessor (pr〇cess〇r) or the microcontroller ((: 〇11 〇〇11 € 1 " All registers (1 ^^ 51; 61_5) in) are all set to initial values to allow the electronic device to start or start in a certain state. This reset signal is generally through a power-on reset circuit (power_orl reset circuit ), The function of the power-on reset circuit is to detect the condition that the power supply voltage rises from 0V to the normal operating voltage, thereby generating a reset signal. At present, many technologies can be used to achieve the required power Reset signal reset circuit. The traditional reset circuit uses RC delay to detect the power supply voltage change at startup. This technology is not very sensitive to rapid voltage changes. But its disadvantage is that it needs to be used. To large capacitors. At present, most of the power-on reset circuits use the threshold voltage of CM0s (complementary metal-oxide-semiconductor) components, which is to compare the power supply voltage with the CMOS threshold voltage. Voltage to detect changes in power supply voltage. Although this technology is more sensitive to rapid voltage changes, it does not require the use of external capacitors and therefore costs less. For example, US Patent Publication Nos. 4, 633, 107 and 4, 970, 408 This kind of CMOS power-on reset circuit was revealed. However, in the actual application environment, the surroundings of electronic devices and computers are often

^ 561 〇 t 5. Description of the invention (2) ^ There will be interference from other electromagnetic fields, and these electromagnetic interference will be coupled into the integrated circuit through the output / wheel pin. This coupled electromagnetic interference will cause transient voltage / current pulses inside the integrated circuit, which may cause the system to have the following two adverse phenomena. The first is to change the logic state temporarily stored in the integrated circuit, such as affecting more important components like microprocessors or microcontrollers, and even cause the system to crash. The second is to cause the power supply voltage to change sharply instantaneously 'and then cause the boot reset circuit to misjudge the rising condition of the power supply voltage' to generate an unexpected reset signal to restart the system. In fact, due to the differences in circuit structure, the sensitivity of various power-on reset circuits to power supply voltage changes is very different. For example, some can only respond to changes in power supply voltage over a few ms, and some can only respond to Several ns power supply voltage pulses. For example, if the power-on reset circuit used is less sensitive to changes in power supply voltage, but the electromagnetic interference has actually affected the logic state of the registers in the microprocessor or other important components 'but the system has not been reset' Will make the system enter the wrong state and easily crash; on the other hand, 'if the power-on reset circuit used is more sensitive to changes in power supply voltage', the system is also easy to restart with slight interference, which will also cause the system Instability. In view of this, the purpose of the present invention is to provide a method and device for processing power disturbances caused by electromagnetic interference, which can detect electromagnetic interference phenomena that sufficiently affect the power-on reset circuit. Problems caused by changes in the register data. In addition, another object of the present invention is to provide a method and device for processing power source disturbance caused by electromagnetic interference, which can determine the purpose of the reset circuit when the power is turned on.

45 6 1 Ο 1 V. Description of the invention (3) 是否 Is the reset signal sent out really a reset signal generated at power-on? Or a reset signal caused by electromagnetic interference to prevent accidental reset of the system . According to the above-mentioned object, the present invention proposes a processing device for power disturbance caused by electromagnetic interference, which can be applied to a power-on reset circuit of an electronic system. The device includes a logic circuit for receiving a control signal and outputting an edge. When the initial logical value of the number 'like cancer k' is the first logical value and the logical value of the control signal is changed, the status signal is converted from the first logical value to the second logical value and is no longer controlled by the logical value of the control signal. And is fixed to the second logic value; and a judgment circuit coupled to the power-on reset circuit and the logic circuit 'when the reset signal of the power-on reset circuit is received and the status signal: is the first logic value' is delivered Reset signal and change the logic value of the control signal 'When the reset signal of the power-on reset circuit is received and the status signal is the second logic value', the delivery of the reset signal is stopped. At the same time, a repair procedure can be initiated to repair the effects of electromagnetic interference. ^ The logic circuit includes a single logic latch for outputting a status signal, and latching the status signal to the second logic value when the status signal is the second logic value; and an input device coupled to the single logic The latch also receives a control signal, which is used to make the state of the output of the single logic lock detector the first logic value according to the initial value of the control signal, and is used to change the logic value of the control signal to make the single logic latch The status signal output from the controller is converted into a second logic value. The early logic latch can be implemented in two types. The first type includes an NMOS transistor whose source is grounded; an inverter whose input terminal is connected

45 6 1 0 1 V. Description of the invention (4) Connect the drain of the NM0S transistor 'its output is connected to the gate of the transistor and outputs a status signal' and a resistor to connect a high voltage source and the transistor Of the extreme. The other type includes a transistor whose source is connected to a high-voltage source; an inverter whose input terminal is connected to the drain of the PM0s transistor, and whose wheel-out terminal is connected to the gate of the PM0S transistor and turns out. The status signal, and a resistor, connects the ground terminal and the drain of the PMMOS transistor. A capacitor can be connected across the non-pole and source of the NM0S (or PM0S) transistor to enhance its effect of latching to the second logic value when it is disturbed. In addition, the on-resistance value of the NMOS (or PM0S) transistor is preferably much smaller than the resistance value of the resistor. It can also enhance its effect of latching to the second logic value when it is disturbed. In addition, when the number of single logic latches and corresponding input devices exceeds one, a logic gate (such as a NOR gate) can be used to generate the required status signal, so as long as a set of single-logic latches and The corresponding input device can still maintain the original latch logic value after electromagnetic interference, which can ensure that the original function can still be achieved. In addition, the present invention also provides an electronic device, which includes a power supply voltage rising to a predetermined voltage series circuit for receiving a control signal signal, which is changed when the logic value of the control signal is changed when the electronic device is powered on. The second logic value, when the status signal is no longer subject to the above-mentioned control signal, is coupled to the electromagnetic interference detection device of the power-on reset circuit, and can be adapted to: a power-on reset circuit for sending at a value A reset signal; a logic signal and a status signal are rotated out. When the status initial logic value is the first logic value, and when the status signal is renumbered from the first logic value to the second logic value, the status signal changes and changes. Logic value; and a judgment and logic circuit '

Page 7 — 4 5 6J 〇1 V. Explanation of the invention (5) '' ---- When the above status signal is the first logic value, the logic value of the description control number is set 'When the weight of the power-on reset circuit is received, and the reset number is a second logic value, it is judged that the power source is disturbed by electromagnetic interference. The invention also provides a processing method of power disturbances caused by electromagnetic interference, which can be applied to a power-on reset circuit of an electronic system. First, when the system is started, a status value is set to the first logic value; when a reset signal is sent from the reset circuit and the status value is the first logic value, the reset signal is sent and set The state value is the second logic value; and = the reset signal sent by the power-on reset circuit is received and the state value is the ^ th logic. When the value is', the reset signal is stopped, and a repair program can be started to repair electromagnetic interference. The effect is that a single logic lock detector is used to maintain the state value to a second logic value to prevent electromagnetic interference from changing the state value. Brief description of the drawing: In order to make the above-mentioned objects, features and advantages of the present invention more It is obviously easy to understand, and a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: FIG. 1 shows a block diagram of a processing device for power disturbance caused by electromagnetic interference of the present invention. FIG. 2 shows this The detailed circuit diagram of the logic circuit of the first embodiment of the invention. FIG. 3 shows the flow of the method for processing the power disturbance caused by the electromagnetic interference of the first embodiment of the invention. .

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V. Description of the Invention (6) Fig. 4 shows the present invention. Explanation of symbols: 1 ~ power-on reset circuit; 2 ~ logic circuit; 2a ~ first logic circuit; 2b ~ second logic circuit; 3 ~ judgment circuit; ι〇 ~ input device; 2 ~ single logic latch '21 , 30-33, 41, 46, 47 ~ inverter; 23, 44 ~ resistance: 24, 43 ~ capacitor; π, 45 ~ PMOS transistor; 22, 42 ~ NM0S transistor; CTRL ~ control signal; FLAG ~ Status signal; RESET, reset signal; VDD ~ Power supply voltage. ° Example: The present invention can detect the phenomenon of electromagnetic interference on the one hand, so that the system has the opportunity to repair the stored values of different registers in the system that may be affected by electromagnetic interference. If the reset circuit malfunctions, a processing circuit and method are proposed to avoid accidental system reset. The embodiments are described in detail below with reference to the drawings. First embodiment of the poor month: Figure 1 shows a block diagram of a processing device for power disturbance caused by electromagnetic interference according to the present invention. As shown in the figure, symbol 1 represents a power-on reset circuit, which has the same operation as a power-on reset circuit. That is, when the power supply voltage is equal to a predetermined voltage in each integrated circuit, a reset signal reset is generated to reset the series Leiba, and pull the register. Symbol 2 represents a logic example such as: the control signal is 1 ^ and the status signal FLAG is output. At ', the initial value of the control signal CTRL when the system is turned on is a logical value V. Description of the invention (7)' '0 ", and the initial value of the status signal FLAG is set to a logical value', 丨 ,,. The logic value of the status signal FLAG will be affected by the logic value change of the control signal CTRL. When the logic value of the control signal CTRL changes (from If 〇 "to 1) ', the status signal flag will also be converted from " 1M to " 〇μ. But when the status signal FLAG is set to "0", the logic value of the status signal FLAG is not affected by the control signal CTRL and is fixed at "0". This characteristic is achieved through a single logic latch. This part is slightly Details later. The symbol 3 indicates a judgment circuit, which is coupled to the power-on reset circuit] and the logic circuit 2. When the reset signal RESET of the power-on reset circuit 1 is received and the status signal FUWG is " 丄 n, it indicates the reset The signal RESET is generated for the first time and indicates that the system is normally generated. Therefore, a reset signal RESET is delivered to the component to be reset. On the other hand, the control signal ^ is changed from " 〇 to 丨 丨, ，， ， Send to logic circuit 2 and let logic circuit 2 lock the status signal to 0 °. If you receive the reset signal RESEt of the power-on reset circuit 1 afterwards, and determine that the status signal F LAG is M 〇 ", it means that the reset signal RESET ^ is generated after the second time, and it is regarded as a malfunction caused by electromagnetic interference, so the delivery of the reset signal RESET is stopped. At the same time, a repair red sequence can be started to repair the influence of electromagnetic interference in the system.

Figure 1 illustrates two different power supply voltage VDD waveforms at the same time, which respectively represent the normal power-on situation (upper waveform) and electromagnetic interference (bottom. Square waveform). During normal startup, the control signal CTRL is " 〇 || and the status signal FLAG is " 1 ". When the power supply voltage VDD * 〇v gradually rises to a predetermined voltage value, the power-on reset circuit} will pull down the reset signal reset to "0π", which means that the system reset is not performed. When the judgment circuit 3 receives this reset Set signal RESET

5. Description of the invention on page 10 (8) When the status signal flag is " 1 ", the reset signal RESET is delivered to perform a system reset. At the same time, the control signal is used to change the hole (to become " wide) Change the status code FLAG to " 〇 ". On the other hand, if electromagnetic interference occurs during the operation of the system, which causes the power supply voltage VDD to oscillate, it will also trigger the power-on reset circuit 1 so that it again pulls down the reset signal RESET to 11 ″. But this At this time, the judging circuit 3 can judge the current reset signal RESET caused by electromagnetic interference according to the status signal FLAG (" 〇 ") sent by the logic circuit 2, without the need to reset the signal. RESET is sent to the component to be reset. As mentioned above, on the one hand, this device can be used as a detection circuit to detect the obvious electromagnetic interference phenomenon during system operation, so as to provide the CPU or other components for Repair actions in the system 'On the other hand, this device can also be used as a processing device when the power-on reset circuit 1 malfunctions, so as to prevent accidental reset and maintain the stability of the system. Among the above devices, the logic circuit 2 needs further explanation. According to the above, the function of the logic circuit 2 is to set the status signal FLAG to "(T at the time of power-on, according to which it can be used to deal with subsequent electromagnetic interference. The reset signal RESET caused by disturbance. Therefore, in principle, it can be implemented with a general data latch. However, from the perspective of practical application, the logic circuit 2 is best able to control the signal The CTRL generating circuit is disturbed or the internal circuit of logic circuit 2 is affected by electromagnetic interference 'can also keep the status signal FLAG as " (Γ, because if the status signal FLAG sent by logic circuit 2 is also changed by electromagnetic interference, the first 1 ® devices cannot guarantee their ability to perform their preset functions

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For those skilled in the art, it is also possible to use a general latch to implement circuit 2 and use various known anti-electromagnetic interference technologies to specifically prevent the judgment circuit 3 and the logic circuit 2 from being subjected to electromagnetic interference so that the status signal ^^ changes. In this case, this also conforms to the spirit of the present invention. Operation ^: Twenty-one-in this embodiment, another method is adopted, that is, the logic circuit 2 locks the status signal FLAG during the reset operation of the opening &closing; ", after that, it is no longer ^ ^ The input control signal CTRL changes the state signal FLAG, thereby preventing the control circuit 彳 #CTRL circuit from being affected by electromagnetic interference and changing its logic value to affect the state signal FLAG; in addition, a special design is required in logic circuit 2 ' Prevents internal electromagnetic interference from changing the status signal FLAG. Fig. 2 is a detailed circuit diagram of a logic circuit 2 according to the first embodiment of the present invention. As shown in the figure, the logic circuit 2 includes an inverter 30 at the input (receiving the control signal CTRL), an input, a single-logic latch, and inverters 31, 32 at the output (sending the status signal FLAG). And 33. The inverters 30-33 are used to adjust logic values and amplify signal levels. The input device 10 includes a PMOS transistor 11, which receives the control signal CTRL 'indirectly through the inverter 30, and can make a single logic latch 2 according to the initial value of the control signal CTRL (that is, " 0 "). The output status signal is almost "Γ", and when the logic value of the control hall number CTRL is changed (from " 〇 " to " 1 "), the status signal FLAG output by the single logic latch 20 is changed. Also changed from " 1 " to " 0. The single logic latch 20 includes an inverter 21, an NMOS transistor 22, a resistor 23, and a capacitor 24 'to output a status signal FLAG (indirectly through the output End inverters 31-33). The difference from ordinary latches is that this single logical latch 20 can only allow node N 丨 to latch on " 〇 ,, which means that

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4 5 6 丨 CM 5. Description of the invention (10) The state signal FLAG is latched at a logic value, '(Γ, but cannot be latched at a logic value " 1.) Therefore, the state can be allowed in a single logic latch 20 The signal FLAG is changed from "1" to "(Γ, but cannot be changed from" 〇 "to" 1 ". In the single logic latch 20, the inverter 21, the NMOS transistor 22, and the resistor 23 are mainly used. Connection configuration to achieve the purpose of latching the status signal FLAG to a single logic value "0". As shown in the figure, the source of the NMOS transistor 22 is grounded and the drain is connected to the resistor 23 and the input of the inverter 21 The input of the inverter 21 is connected to the drain of the NMOS transistor 22, and the wheel output is connected to the gate of the MOS transistor 2. The resistor 23 is connected to the supply voltage VDD and the drain of the transistor 22 When the node N1 is " 1 " and the node N2 is " 0 ", then the status signal FLAG is " 1 ", and the NMOS transistor 22 is in a non-conducting state, that is, an unstable state. Purpose of locking data; when node N1 is "0" and node N2 is " 1 " No. FLAG is " OM, and the NMOS transistor 22 is also in an on state, that is, a stable state, so the purpose of sample lock data can be achieved. With this structure, the status signal flag can be fixedly locked at a logic value. " 0 ". The following fully describes the operation of logic circuit 2 in Figure 2. First, when the system is turned on (not yet reset), the control signal CTRL is M (Γ, so the PMOS transistor 11 is in a non-conducting state (t urn 〇 ff), so node n 1 is now, 1 ”and node N2 is " 0 ". This makes the NMOS transistor 22 also in a non-conducting state, and the status signal FLAG is " Γ 'which is also the above Initial value. When the power-on reset circuit 1 sends a reset signal RESET and the judgment logic 3 accordingly pulls the control signal CTRL to "1", then the PM11 transistor 11 is turned on, so the node N1 is the node μ is, '1 ",

5 61 Ο 1 V. Description of the invention (11) At the same time, the NMOS transistor 22 is also in an on state. Using the architecture of the inverter 21 and the NMOS transistor 22, the status signal FLAG can be latched at "011. If the control signal CTRL unexpectedly drops from" Γ to "" 0 " during the subsequent operation, then PMOS Transistor 11 will also be in a non-conducting state, but NMOS transistor 22 will still maintain a conducting state. In other words, the status signal FLAG is no longer changed by the control signal CTRL, and will always remain at the logical value " 0 ". This characteristic is in line with the first condition of the aforementioned logic circuit 2 ', that is, the state signal FLAG will not be affected after being set to " (Γ

The control signal CTRL changes (which may be changed by electromagnetic interference) to change the logic value. The second condition of S in the aforementioned logic circuit 2 is that under the condition of electromagnetic interference, the state signal FLAG cannot be changed even if the logic circuit 2 is internally subjected to power disturbance or disturbance from other sources. In this embodiment, two mechanisms are mainly used to achieve this purpose. First, the single-plant logic latching mechanism of the inverter 21 and the switch 05 transistor U can keep the logic value of the node N1 at " 〇 " after the electromagnetic interference occurs, that is, the state signal is almost "still There is a high probability that it will be maintained at " 〇 ". Second, the resistance of the resistor 23 can be set to a higher resistance value, for example, set to 200K Ω or more. Because the general on-resistance of the NMOS transistor 22 when it is on Approximately between 1 (Ω to ten κ Ω, according to the voltage division relationship, the influence of the power supply disturbance amplitude on the power supply voltage VDD received at node 1 ^ 1 will be greatly reduced, so that the latched logic The value cannot be changed easily. Third, the use of a capacitor 24 connected across. Capacitor-generally has the role of stability? Lu Jin used capacitor 24 to provide a mechanism for voltage stabilization in the month of transient electromagnetic interference. Through the above three mechanisms Even if the logic power

45 610 1 Five 'invention description (m path 2 itself ^ is affected by electromagnetic interference, the logical value of node n tends to be "0π" is very high, so the status signal FLAG can be locked to the logical value,' 0 " His Majesty said that the present invention's method for processing power disturbances caused by electromagnetic interference, and Figure 3 shows a detailed flowchart of this processing method. First, when the system starts, 'the control signal CTRL can set the status signal FUG at r ( si). Therefore, when the reset signal reset is received for the first time (52), it can be checked that the status signal FLAG is set at " r (S3) ', so it is regarded as a reset process when the system is turned on, and it will be reset. The signal RESET is delivered to the component to be reset and the control signal CTRL is used to set the status signal FLAG to "quot; 〇" (S4). If a reset signal ("with") is received again, the L number can be checked. If FLAG is 0 (S 3), it is determined that electromagnetic interference caused the reset circuit to malfunction. Therefore, the delivery of this reset signal RESET is stopped, and the corresponding repair program can be started to check the internal register of the system. To the influence of electromagnetic interference (S5). Therefore, on the one hand, it can prevent the reset signal generated by the misoperation to reset the system, and on the other hand, it can also check the obvious electromagnetic interference conditions that the system is subjected to. It must be explained that this The logic values used in the embodiment are not intended to limit the present invention 'in practical application'. Those skilled in the art can still use different logic value settings to achieve the desired effect of this embodiment. Second embodiment: This The implementation example further strengthens the latching effect of the logic circuit 2 in the first embodiment, so that the state signal FLAG can maintain a higher probability at a logic value even under the influence of the logic circuit 2 itself by electromagnetic interference

Page 15 4 5 6 10 1 V. Description of the invention (13) " 0 ". The technique used in this embodiment is the concept of using multiple latches, that is, as long as one of the single logical latches can be maintained The latched logic value, the status signal FLAG can be latched to the logic value " 〇π, thereby improving its stability. 3 Figure 4 shows a group fine circuit diagram of the logic circuit 2 of the second embodiment of the present invention. As shown in the figure, the logic circuit 2 includes an inverter 30, a first logic circuit 2a, a second logic circuit 2b, and a NOR gate 33a. In fact, the inverter 30, the first logic circuit 2a, and the NOR gate 33a are completely equivalent The circuit structure shown in Figure 2 (where the inverter 33 is replaced by the NOR gate 33a). In addition, the inverter 30, the second logic circuit 2b, and the NOR gate 3 3a constitute another equivalent circuit. Among them, the logic value used by the second logic circuit 2b is opposite to that of the component polarity-Feng Ji circuit 2a. "K In the second logic circuit 2b, the NMOS transistor 42 functions as an input device, corresponding to the first logic circuit 2a. PM0S transistor!丨. In addition, the phaser 46, the PM0S transistor 45, the resistor 44 and the capacitor 43 constitute a single-logic latch, which respectively correspond to the inverter 2 in the first logic circuit 2 & NM0S transistor 22, the resistor The operation of 23 and capacitor 24 are basically the same, except that the logic values are opposite, so the second logic circuit will not be described again. It must be noted that when the state signal mG is ,, 〇 |, the point N3 is " r and the node N4 is 1 ,. 1 In this embodiment, the role of the second logic circuit ^ η 3 section 213 is mainly to prevent the logic circuit 2 itself from being electromagnetically disturbed ^ r Ding Fuzhen to enhance the stability of the state signal FLAG . Before being subject to Thunder +, say π, both men took office. / a electromagnetic interference while the status signal FLAG is still "0", inverter 32 (first logic thunder 9 w ^ slave circuit 2a) and inverter 47 (second logic

5. Description of the invention (14) Both circuits 2b) output y ,. If during the electromagnetic interference process, the output of one of the two inverters 32 or 47 is changed to "0", but the state signal FLAG can still be maintained by the action of the NOR gate 3 3a "" 〇 ". That is to say, even if any single logic latch in the first logic circuit 2a or the second logic circuit 2b fails to latch data normally under electromagnetic interference, it will not affect the logic value of the status signal FLAG. In this way, the original latching system can greatly strengthen the resistance to internal electromagnetic interference. In addition, in this embodiment, the use of a single logic latch with different polarities is also useful to prevent single-polarity electromagnetic interference from preventing status signals. ! ^ "Aided change. In addition, although the purpose of two polar phase signals FLAG, v is inverse J, but Q can add more than two meanings as long as there is only one purpose that can reduce the positive = state signal FLAG. Often, as above, but it is not used to limit it ~ Without departing from the essence of the present invention, whichever of the present invention will prevail. The foot target must be explained that the single logic latch of the second embodiment to achieve stability is not intended to limit the present invention, that is, the single logic latch. At this time, the data can be locked by the electromagnetic dry latch. The invention is stable. Although the present invention is disclosed in a preferred embodiment, anyone skilled in the art can make some changes and define the scope of the patent application attached to it within the scope.

Claims (1)

456 彳 Ο 1 6. Scope of patent application 1. A processing device for power disturbance caused by electromagnetic interference, which can be applied to a power-on reset circuit of an electronic system, which includes: a logic circuit for receiving a control signal and outputting a status signal, The initial logic value of the status signal is the first logic value, and when: the logic value of the control signal is changed, the status signal is converted from the first to the second logic value; and a judgment circuit is coupled to the power-on reset. Circuit and the above-mentioned logic circuit 'When the reset signal of the above-mentioned reset circuit is received and the status signal is the first logic value, the reset signal is delivered and the logic value of the control signal is changed. When the reset signal of the power-on reset circuit and the status signal is a second logic value, the delivery of the reset signal is stopped. 2. The processing device according to item 1 of the scope of patent application, wherein when the state signal output by the logic circuit is a second logic value, the state signal is no longer affected by the control signal to change the logic value. 3. The processing device according to item 1 or 2 of the scope of patent application, wherein when the determination device receives the reset signal of the power-on reset circuit and the status signal is a second logic value, the delivery of the reset is stopped. Signal and initiate a repair procedure to repair the effects of electromagnetic interference. 4. The processing device according to item 2 of the scope of the patent application, wherein the above-mentioned logic circuit includes: a single logic latch for outputting the above-mentioned status signal, and when the above-mentioned status signal is a second logic value, the above-mentioned status is changed. The signal is latched to a second logic value; and Page 18 5 6 10 1 6. Application scope ~ An input device 'coupled to the single logic latch and receives the control signal' is used to make the single logic lock detector wheel according to the initial value of the control signal. The state signal is a first logic value and is used to change according to the logic value of the control signal, so that the state signal output by the single logic latch is converted and fixed at the second logic value. 5. The processing device according to item 4 of the scope of patent application, wherein the single logic latch includes: an NMOS transistor with its source grounded; an inverter whose input terminal is connected to the drain of the NMOS transistor Its output terminal is connected to the gate of the NMOS transistor and outputs the above-mentioned status signal; and a resistor is connected to a high voltage source and the pole of the NMOS transistor. 6. The processing device according to item 5 of the scope of patent application, wherein the single logic latch further includes a capacitor connected across the minus and source of the above NMOS transistor. 7. The processing device according to item 5 of the scope of patent application, wherein the on-resistance equivalent value of the NM0S transistor is much smaller than the resistance value of the resistor. 8. The processing device described in item 5 of the scope of the patent application, wherein the input device is a PM0S transistor, and its wave and source are respectively connected to the ground terminal and the drain of the NM0S transistor, and its gate receives the above. Control signal ° 9. The processing device as described in item 4 of the scope of the patent application, wherein the single logical lock device includes: 19th child 6. Scope of patent application: a PMOS transistor whose source is connected to a high voltage source; an inverter whose input terminal is connected to the drain of the PMOS transistor; its output terminal is connected to the gate of the PMOS transistor and outputs the above State #; and a resistor connected between the ground terminal and the drain of the PMOS transistor. 10. The processing device according to item 9 of the scope of the patent application, wherein the single logic latch further includes a capacitor across the anode and source of the transistor. 1U The processing device according to item 9 of the scope of patent application, wherein the on-resistance equivalent value of the PMOS transistor is much smaller than the resistance value of the resistor. 12 Input pressure source and No. 13 Including the 14-state signal value of a logic input device, and the value of the first series. The processing device described in item 9 of the scope of patent application, wherein the above is an NMOS transistor, the drain and source of which are connected respectively The drain of the above PMOS transistor receives its control signal at its gate. The processing device as described in item 4 of the scope of the patent application, wherein the processing device is still included in series 2 for exceeding the above-mentioned single logical latch and the corresponding number of the above-mentioned wheels. A moment's sum produces the above-mentioned status signals required. A logic circuit for receiving a control signal and outputting a ## where the initial logic value of the status signal is the first logic and when the logic value of the control signal is changed, the upper value is converted to the second logic value and not Controlled by the above; ringing, fixed to the second logic value, including: a single logic latch to output the status signal, and when page 20 456101 ~ 0 bH) 6. Patent application: When the status signal is the second logic value, the status signal is latched and fixed to the second logic value; and an input device is coupled to the single logic latch and Receiving the control signal, so that the status signal output by the single logic latch is the first logic value according to the initial value of the control signal, and used to change the logic value of the control signal according to the initial value of the control signal, so that the single logic latch is The state signal output by the latch is switched and fixed at the second logic value. 15. The logic circuit as described in item 14 of the scope of patent application, wherein the single logic latch includes: an N M 0 S transistor whose source is grounded;-an inverter whose input terminal is connected to the above The output terminal of the NM0S transistor is connected to the gate of the NM0S transistor and outputs the above-mentioned status signal; and a resistor is connected to a high voltage source and the drain of the NM0S transistor σ 1 6. According to the patent application The logic circuit according to item 15 of the scope, wherein the single logic latch further includes a capacitor, which is connected across the drain and source of the NMOS transistor. 17 • The logic circuit as described in item 15 of the scope of patent application, wherein the on-resistance equivalent value of the NM0S transistor is much smaller than the resistance value of the above resistor. 1 8. The logic circuit according to item 15 of the scope of the patent application, wherein the input device is a PM0S transistor, and its drain and source are respectively connected to the ground terminal and the drain of the NM0S transistor, and its gate Receive the control signal. Page 21 4 5 6 1 〇1 6. Patent application scope 19. The logic circuit described in item 15 of the patent application scope, wherein the single logic lock detector includes: a PM0S transistor, the source of which is connected to a high voltage Source; an inverter whose input terminal is connected to the drain of the PM0S transistor, its output terminal is connected to the gate of the PM0S transistor and the status signal is rotated out; and a resistor is connected to the ground terminal and the PM0S transistor Drain. 20. The logic circuit according to item 19 of the scope of the patent application, wherein the single-logic latch further includes a capacitor, which is connected across the anode and the source of the PMOS electrical crystal. 21. The logic circuit as described in item 19 of the scope of patent application, wherein the on-resistance equivalent value of the PMOS transistor is much smaller than the resistance value of the above resistor. 22. The logic circuit as described in item 19 of the scope of the patent application, wherein the input device is an NM 0 S transistor, and its pole and source are respectively connected to the voltage source and the drain of the PM0S transistor. The gate receives the control signal. 23. An electromagnetic interference detection device that can be applied to an electronic device. It includes: a power-on reset circuit for sending a reset signal when a power supply voltage rises to a predetermined voltage value:. A logic circuit for receiving a control signal and outputting a status signal. The initial logic value of the status signal when the electronic device is powered on is a first logic value, and when the logic value of the control signal is changed, 6. The status signal of the patent application range is converted from the first logic value to the second logic value. When the status signal is the second logic value, the status signal is no longer affected by the control signal to change the logic value; And—the judging circuit is coupled to the above-mentioned power-on reset circuit and the above-mentioned logic circuit 'when the reset 彳 § number of the above-mentioned power-on reset circuit is received and the state # number is the first logic value, the control signal is changed A logic value. When the reset signal of the power-on reset circuit is received and the status signal is a second logic value, it is judged that the power source is disturbed by electromagnetic interference. 24. The detection device according to item 23 of the scope of the patent application, wherein when the above-mentioned judgment device judges that the power supply is disturbed by electromagnetic interference, it starts a repair procedure to repair the influence caused by electromagnetic interference. 2 5. If applying for a patent The detection device according to item 23 of the scope, wherein the above-mentioned logic circuit includes: — a single logic latch for outputting the above-mentioned status signal 'and latching the above-mentioned status signal when the above-mentioned status signal is a second logic value At a second logic value; and an input device, coupled to the single # latch and receiving the control signal 'for initial value of the control signal, so that the status signal output by the single logic latch is The first logic value is used to change the logic value according to the control signal, so that the state signal output by the single logic lock detector is converted and truly fixed at the second logic value = 2 6. As the 25th item of the scope of patent application The detection device, wherein the single logic latch includes: an NMOS transistor whose source is grounded, Page 4561 061 Application scope of patent 6-Inverter, whose input terminal is connected to the drain of the NMOS transistor, its wheel output is connected to the gate of the NMOS transistor and outputs the status signal; and a resistor 'Connect a high voltage source to the drain of the above NMOS transistor. 27. The detection device described in item 26 of the patent application scope, wherein the single logic latch further includes a capacitor connected across the recorded NMOS circuit. The > and pole and source of the crystal. 2 8. The detection device as described in item 26 of the scope of patent application, wherein the on-resistance equivalent value of the NM0S transistor is much smaller than the resistance value of the above resistor. 2 9. The detection device as described in item 26 of the scope of patent application, wherein the input device is a PM0S transistor, and its drain and source are connected to the ground terminal and the drain of the NMOS transistor, respectively. The pole receives the control signal. 30. The detection device according to item 25 of the scope of patent application, wherein the single logic latch includes: a PMOS transistor whose source is connected to a high voltage source; an inverter whose input terminal is connected to the PMOS The output terminal of the transistor is connected to the gate of the PMOS transistor and outputs the status signal; and a resistor is connected to the ground terminal and the drain of the PMOS transistor. 31. The detection device as described in item 30 of the scope of the patent application, wherein the single logic latch further includes a capacitor across the drain and source of the PMOS transistor. 4 5 61 〇1 VI. Patent application scope 3 2. The detection device as described in item 30 of the patent application scope, wherein the ON equivalent resistance value of the PM0S transistor is much smaller than the resistance value of the above resistor. 33. The detection device as described in item 30 of the scope of patent application, wherein the input device is a dragon 0S transistor, and its drain and source are connected to the voltage source and the drain of the PMMOS transistor, respectively. Its gate receives the above control number. 34. The detection device as described in item 25 of the scope of patent application, which further includes a logic gate to generate the above-mentioned required sum when the number of the single logical latch and the corresponding wheel-in device exceeds one. State ^ signal. 3 5. —A method for processing power disturbances caused by electromagnetic interference, which can be suitably used in a power-on reset circuit of an electronic system, including: when the electronic system is started, setting a state value to a first logic state = When the reset signal sent by the above-mentioned power-on reset circuit is above the logic value, the reset signal is delivered and the state I and the value are set to the second logic value; and when the reset signal sent by the above-mentioned power-on reset circuit is received, When the state value of the restatement is the second logic value, the above is stopped and the above 36. As described in the 35th of the scope of patent application; 'Includes a step: 々 in which it still receives the above-mentioned reset signal of the power-on reset circuit When it is the second logic value, start-repair: the influence caused by the above-mentioned state disturbance. / Re-private sequence, wrong to repair electromagnetic interference Page 25 456101 VI. Application for patent scope 3 7. The processing method described in item 35 of the scope of patent application, wherein a single logic latch is used to maintain the above state value as the second logic value, thereby preventing electromagnetic interference from changing the above Status value. Page 26