TW456045B - Ferroelectric transistor and its production method - Google Patents

Ferroelectric transistor and its production method Download PDF

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Publication number
TW456045B
TW456045B TW89117062A TW89117062A TW456045B TW 456045 B TW456045 B TW 456045B TW 89117062 A TW89117062 A TW 89117062A TW 89117062 A TW89117062 A TW 89117062A TW 456045 B TW456045 B TW 456045B
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Taiwan
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ferroelectric
dielectric
layer
ferroelectric transistor
scope
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TW89117062A
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Chinese (zh)
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Thomas Peter Haneder
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Infineon Technologies Ag
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Abstract

In a ferroelectric transistor, which in a semiconductor substrate (11) has two source-/drain-regions (12) and a channel-region arranged between the two regions (12), a dielectric inter-layer (13) is arranged on the surface of the channel-region. A ferroelectric layer (14) and a gate-electrode (15) are arranged above the dielectric inter-layer (13). The dielectric inter-layer (13) contains an oxide of an element, which is also contained in the ferroelectric layer (14). The dielectric inter-layer (13) and the ferroelectric layer (14) can be produced in a same process-chamber.

Description

456045 Α7 Β7 經濟部智慧財產局員工消費合作：id印製 五、發明說明（1 ) 本發明係關於一種鐵電質電晶體，其具有二個源極/ 汲極區，一個通道區及一個閘極電極，其中在閘極電極 和通道區之間設置一種鐵電質層（即，由鐵電質材料所 構成之層）。本發明亦渉及此種電晶體之製造方法。此 種電晶體之導電性是與鐵電質材料所構成之層之極化狀 態有關β此種鐵電質電晶體另外亦以永久性記億體來探 討0數位資訊之二種不同之邏輯値對應於鐵電質層之二 種不同之極化狀態。此種鐵電質電晶體之其它使用可能 性例如神經網路。 由於鐵電質材料（其配置在半導體基板之表面上）顯示 不良之界面特性，這對鐵電質電晶體之電性有不良之影 響，則建議在鐵電質電晶體中在鐵電質層和半導體材料 之間使用一種中間層，其可在半導體基板之表面上確保 一種足夠良好之界面（請參閱ΕΡ 0 566 585 Β1和Η, Ν. Lee et al, Ext. Abst. Int. Conf, SSDM, Haraatsu, 1997，page 382 to 383 )。可使用大部份之隔離用之穩 定之氧化物（例如，Ce02或Zr02 )作爲中間層。 已顯示的是：此種介於中間層和鐵電質層之間的界面 之品質是有限的。 本發明之目的是提供一種鐵電質電晶體，其中此種至 鐵電質層之界面已改良。此外，本發明亦渉及此種電晶 體之製法。 上述目的是由申請專利範圍第1項之鐵電質電晶體及 第11項之製造方法來達成。本發明之其它構造敘述在申 本紙張尺度適用中國國家標準（CNS)A4規格（210 297公釐） ------------V—裝·-ί (請先閲讀背面之注意事項#,填寫本頁) 訂： 456045 A7 B7 五、發明說明（y) 請專利範圍其它各項中。 (請先閱讀背面之注意事項异填寫本頁) 鐵電質電晶體在半導體基板中具有二個源極/汲極區 及一個介於其間之通道區。在通道區之表面上配置一種 介電質中間層Θ在介電質中間層上配置一個鐡電質層及 一個源極/汲極區。介電質中間層因此包含一種元素 (其亦包含在鐵電質層之材料中）之氧化物。這樣可在介 電質層因此包含一種元素（其亦包含在鐵電質層之材料 中）之氧化物，這樣可在介電質層和鐵電質層之間的界 面上防止各種表面反應（其會影響此界面之品質 >。以此 種方式可改良介電質中間層和鐵電質層之間的界面。 由於介電質中間層包含一種元素（其包含在鐵電質層 之材料中）之氧化物，則此介電質中間層和鐵電質層可 以同次（in situ)之方式在唯一之程序室中製成。因此 ，在其它情況中製成介電質中間層和製成鐵電質層之間 所需之程序室變換時之污染即可防止，此種污染同樣會 影響此二層間之界面之品質。 經濟部智慧財產局員工消費合作社印製 鐵電質層之製造可在CVD設備或濺鍍設備中進行。在 現代之CVD設備中使用先質（precursor)系統，其中對鐵 電質層之每一種組成都使用特定之先質源須調整不同 先質源之流量，使鐵電質層具有所期望之化學計量。爲 了在此種設備中製成介電質中間層，只使用各先質中之 一來製成此氧化物。因此須另外供應氧。然後不必由程 序室中取出此半導體基板即可另外使用其餘之先質來生 長此鐵電質層.。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 五、發明說明（ A7 B7 經濟部智慧財產局員工消費合作社印製 若在濺鍍反應器中製造此種鐵電質層，則就這些包含 在鐵電質層中之元素撕都設有不同之靶（target),爲了 製成此介電質中間層，則只使用此種添加氧之靶。鐵電 質層然後藉由另外使用其餘之靶而製成。 由這些元素之一（其包含在鐵電質餍之材料中）之氧化 物所構成之鐵電質層之其它優點是：這些包含在層組合 中之元素之數目可減少。因此特別是在介電質中間層和 鐵電質層之間可減少不期望之擴散過程β 鐵電質層較佳是由PZT^PbZrhTlxOs)所構成，介電 質中間層由Ti02所構成，鐵電質層由SrBi2Ta09(SBT) 所構成，介電質中間層由Ta205所構成》這些氧化物一 方面具有較高之介電常數（Ti02者）是20至80，Ta205者 是20至25)，另一方面是這些氧化物可用作將來產生MOS 電晶體時之閘極介電質且因此顯示一些極優良之特性。 在使用Ti02作爲介電質中間層時，介電質中間層之厚 度較佳是5至20nm。使用Ta205作爲介電質中間層時其 厚度是5至201111111 依據本發明之構成，在鐵電質層和閘極電極之間配置 一種介電質覆蓋層。這樣可防止閘極電極和鐵電質層之 間的漏電流，這些漏電流可使電荷由閘極電極經由鐵電 質層而移動至鐵電質層和中間層之間的界面。若此電晶 體隨後在相反之極性中操作，則這些電荷可補償此種由 鐵電質層之極化所造成之電場而防止其下方之電晶體通 道受到控制。藉由防止此種效應可使鐵電質電晶體之資 請 先 閲 面 之 注 意 事 項 η 填 寫 本 頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 456045 A7 B7 五、發明說明（年） 料保持時間變長* <請先聞讀背面之注意事項斧填寫本頁) 爲了完全排除這些經鐵電質層之漏電流，則有利之方 式是：在側面上藉由介電質側面覆蓋Μ而使鐵電質層隔 離。特別是Ce0'2或Zr02適合用作介電質側面覆蓋區。 本發明之範圍包括：由Ce02或Zr02形成介電質覆蓋層。 虫形成介電質中間層所用之材料來形成介電質覆蓋層 是特別有利的’因爲在此種情況下此介電質覆蓋層亦能 以同次（in situ)之方式製成而不須更換此種具有介電質 中間層和鐵電質層之程序室。 特別有利的是：由Ta205或ZrO^形成介電質覆蓋層， 這是因爲這些材料對氫而言是一種擴散位障。此外，456045 Α7 Β7 Consumption cooperation between employees of the Intellectual Property Bureau of the Ministry of Economic Affairs: ID printing 5. Description of the invention (1) The present invention relates to a ferroelectric transistor, which has two source / drain regions, a channel region and a gate. Electrode, in which a ferroelectric layer (that is, a layer composed of a ferroelectric material) is provided between the gate electrode and the channel region. The invention also relates to a method for manufacturing such a transistor. The conductivity of this type of transistor is related to the polarization state of the layer made of ferroelectric material. Β This ferroelectric transistor also discusses two different logics of zero-digit information with a permanent memory of billions. Corresponding to two different polarization states of the ferroelectric layer. Other uses of such ferroelectric transistors are possible, such as neural networks. Since the ferroelectric material (which is arranged on the surface of the semiconductor substrate) displays poor interface characteristics, which has a bad influence on the electrical properties of the ferroelectric crystal, it is recommended to use a ferroelectric layer in the ferroelectric crystal. An intermediate layer is used between the substrate and the semiconductor material to ensure a sufficiently good interface on the surface of the semiconductor substrate (see EP 0 566 585 Β1 and Η, Ν. Lee et al, Ext. Abst. Int. Conf, SSDM Haraatsu, 1997, pages 382 to 383). Most stable oxides for isolation (eg Ce02 or Zr02) can be used as the intermediate layer. It has been shown that the quality of this interface between the intermediate layer and the ferroelectric layer is limited. An object of the present invention is to provide a ferroelectric transistor in which the interface to the ferroelectric layer has been improved. In addition, the present invention also relates to a method for manufacturing such an electric crystal. The aforesaid object is achieved by the ferroelectric transistor in the scope of application for item 1 and the manufacturing method in item 11. The other structure description of the present invention applies the Chinese National Standard (CNS) A4 specification (210 297 mm) in the paper size of the application. ------------ V— 装 · -ί (Please read the Note #, fill out this page) Order: 456045 A7 B7 V. Description of the invention (y) Please refer to other items in the patent scope. (Please read the cautions on the back first and fill out this page first) Ferroelectric transistors have two source / drain regions and a channel region in between in the semiconductor substrate. A dielectric interlayer Θ is disposed on the surface of the channel region. A dielectric layer and a source / drain region are disposed on the dielectric interlayer. The dielectric interlayer therefore contains an oxide of an element which is also contained in the material of the ferroelectric layer. This prevents the dielectric layer from containing an oxide of an element (which is also included in the material of the ferroelectric layer), which prevents various surface reactions at the interface between the dielectric layer and the ferroelectric layer ( It will affect the quality of this interface> In this way, the interface between the dielectric interlayer and the ferroelectric layer can be improved. Since the dielectric interlayer contains an element (the material contained in the ferroelectric layer) Oxide), the dielectric intermediate layer and the ferroelectric layer can be made in the same process chamber in the same process. Therefore, the dielectric intermediate layer and the dielectric layer are made in other cases. Contamination during the transformation of the program room required between the ferroelectric layers can be prevented, and this kind of pollution will also affect the quality of the interface between the two layers. Manufacturing can be performed in CVD equipment or sputtering equipment. Precursor systems are used in modern CVD equipment, in which a specific precursor source is used for each composition of the ferroelectric layer, and different precursor sources must be adjusted. Flow to make ferroelectric Has the desired stoichiometry. In order to make a dielectric interlayer in such a device, only one of the precursors is used to make this oxide. Therefore, additional oxygen must be supplied. Then it is not necessary to remove this from the process room The semiconductor substrate can use the remaining precursors to grow this ferroelectric layer. The paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 5. Description of the invention (A7 B7 Intellectual Property Bureau, Ministry of Economic Affairs) Employee Consumer Cooperative printed that if such a ferroelectric layer is manufactured in a sputtering reactor, different targets are set for these elements contained in the ferroelectric layer. In order to make this dielectric In the middle layer, only such an oxygen-added target is used. The ferroelectric layer is then made by additionally using the remaining targets. It is made of an oxide of one of these elements (which is contained in the ferroelectric material). Another advantage of the ferroelectric layer is that the number of these elements contained in the layer combination can be reduced. Therefore, the undesired diffusion process can be reduced, especially between the dielectric intermediate layer and the ferroelectric layer. Β Ferroelectric The stratum is preferably composed of PZT ^ PbZrhTlxOs), the dielectric interlayer is composed of Ti02, the ferroelectric layer is composed of SrBi2Ta09 (SBT), and the dielectric intermediate layer is composed of Ta205. On the one hand, these oxides have higher dielectric properties. The constant (for Ti02) is 20 to 80, and for Ta205 is 20 to 25). On the other hand, these oxides can be used as the gate dielectric of MOS transistors in the future and therefore show some excellent characteristics. When Ti02 is used as the dielectric interlayer, the thickness of the dielectric interlayer is preferably 5 to 20 nm. When Ta205 is used as the dielectric intermediate layer, the thickness is 5 to 201111111. According to the constitution of the present invention, a dielectric covering layer is arranged between the ferroelectric layer and the gate electrode. This prevents leakage currents between the gate electrode and the ferroelectric layer, which can cause charges to move from the gate electrode through the ferroelectric layer to the interface between the ferroelectric layer and the intermediate layer. If the transistor subsequently operates in the opposite polarity, these charges can compensate for the electric field caused by the polarization of the ferroelectric layer and prevent the transistor channel below it from being controlled. By preventing this effect, you can make ferroelectric transistor crystals. Please read the above precautions. Η Fill out this page. The paper size applies to China National Standard (CNS) A4 (210 X 297 mm). 456045 A7 B7 V. Description of the invention (year) The material retention time becomes longer * < Please read the precautions on the back to fill out this page) In order to completely eliminate the leakage current of these ferroelectric layers, it is advantageous to: The dielectric side covers M to isolate the ferroelectric layer. In particular, Ce0'2 or Zr02 is suitable for use as a dielectric side coverage area. The scope of the present invention includes: forming a dielectric cover layer from Ce02 or Zr02. It is particularly advantageous to use the materials used by the insect to form the dielectric interlayer to form the dielectric cover layer, because in this case the dielectric cover layer can also be made in a situ manner without the need to Replace such a process room with a dielectric interlayer and a ferroelectric layer. It is particularly advantageous to form a dielectric covering layer from Ta205 or ZrO ^ because these materials are a diffusion barrier to hydrogen. In addition,

Ce02亦適合用作氫之擴散位障。在製造這些半導體組 件時，在製程結束通常在一種形成氣體（其含有氫）中進 行退火過程。藉由此種形式氣體-退火過程而使鐵電質 層退化，這是因爲鐵電質材料對氫而言是敏感的。藉由 設置由此種材料（其用作氫之擴散位障）所構成之鐵電質 覆蓋層而使鐵電質層受到保護而不會受氫之擴散所影 響。 經濟部智慧財產局員工消費合作社印製 半導體基板至少在鐵電質電晶體之區域中具有一種材 料，此種材料適合用來製成電子電路組件。此種材料較 佳是含有矽及/或鍺〇特別是單晶矽晶圓或SOI基板適 合用作半導體基板。 特別是摻雜之多晶矽，鉑或鎢適合用作閘極電極。此 外，閘極電極亦可爲一種多層結構。特別是在此種多層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 456045 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（^ ) 結構中可形成二極體結構。 鐵電質電晶體可爲P·或η·通道-電晶體，其可爲增強 型電晶體或空乏型（depletion)電晶體。 本發明以下將依據圖式中之實施例來詳述6 圖式簡單說明： 第1圖 鐵電質電晶體之切面圖，其介電質中間層是 由一種包含在鐵電質層中之元素之氧化物所構成。 第2圖 具有介電質中間層和介電質覆蓋層之鐵電質 電晶體之切面。 第3圖 鐵電質電晶體之切面圖，其中該鐵電質層完 全由介電質材料所圍繞〇 在一種由單晶矽所構成之半導體基板11(其在表面區 中具有摻雜物質濃度是數個l〇16cm_3之Ρ-摻雜區）中配 置二個源極/汲極區12，其是n + -摻雜的且摻雜物質濃 度是數個l〇2Gca·3(第1圖）。 基板11之介於二個源極/汲極區12之間且鄰接於半 導體基板11之表面之此一部份用作通道區。電晶體之此 區可含有一種額外之摻雜以便調整該導通（turn on)電 壓。在通道區之表面上配置介電質中間層13。介電質中 間層13含有Ti02且厚度是7ηκ。 在介電質中間層13之表面上配置一種鐵電質層14，其 含有 PZTtPbZrhTixOd 且厚度是 150nm。 在鐡電質14之表面上配置一種由鉑所構成之閘極電極 15，其厚度大約是50至lOOnm。 !!·装·1Ϊ (請先閱讀背面之注杳？事項#·-填寫本頁) 訂- 本紙張尺度適用中國國家標準<CNS>A4規格（210 X 297公釐） 456045 A7 B7 五、發明說明（h ) 另一方式是此介電質中間層13含有Ta205且厚度是5 至10nm。在此種情況下鐵電質層14含有SBT(SrBi2Ta209) 且厚度是100至150nm。 '在此種由單晶矽所構成之半導體基板21(其在表面區 域中具有數個l〇wcm·3摻雜物質濃度之p-摻雜區）中配 置二個源極/汲極區22,其是n + -摻雜的且摻雜物質濃 度是102ecm·3(第2圖）。 介於此二個源極/汲極區22之間且鄰接於半導體基板 21表面之此區域用作通道區。電晶體之此通道區可含有 額外之摻雜以便調整該導通電壓v在通道區之表面上配 置一種介電質中間層23,其含有Ta205且厚度是5至 1 5nra ° 在介電質中間層23之表面上配置一種鐵電質層24，其 含有 SBT(SrBi2Ta209 )且厚度是 100 至 150Ι1Π1。 在鐵電質餍24之表面上配置介電質覆蓋層25，其含有 乙1'02且厚度是5nm。在介電質覆蓋層25之表面上配置一 種由鉑所構成之閘極電極26，其厚度是50至100 nra* 在此種由單晶矽所構成之半導體基板31(其在表面區 域中具有一種摻雜物質濃度是數個l〇Mcra·3之p.摻雜區） 中配置二種源極/汲極區，其是n+-摻雜的且摻雜物質 濃度是數個102ecm·3(第3圖）。 半導體基板31之配置於此二個溽極/汲極區32之間 的部份是用作通道區。電晶體之此區可含有額外之摻雜 以便調整該導通電壓。在通道區之表面上配置介電質中 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之沒$項病填寫本頁) 裝 · 經濟部智慧財產局員工消費合作社印製 4 經濟部智慧財產局員工消費合作Fi中製 6 0 4 5 A7 ___B7 _____五、發明說明（7〉 間層33，其含有Ta2Os且厚度是5至lOnra。在介電質中 間層33之表面上配置由SBT(SrBi2Ta209 )所構成之鐵電 質層34，其厚度是100至150ηιη。在鐵電質曆34之表面 上配匱介電質覆蓋層35，其含有Ta 205且厚度是5至 10 n m 6 介電質中間層33，鐵電質層34和介電質覆蓋層35之 側面是以一種由Ce02所構成之介電質側面覆蓋區36來覆 蓋0 在介電質覆蓋層35之表面配置閘極電極，其含有n + -摻雜之多晶矽。閘極電極37之厚度是100至2 00nm。 本發明鐵電質電晶體之製造類似於標準M0S電晶體之 製造。介電質中間層13，23或33以及鐵電質層14，24 或34是在唯一之程序室中藉由CVD程序中之沈積過程或 藉由濺鍍且隨後被結構化而製成。源極/汲極區12，22 或32是藉由植入或擴散而形成。 閘極電極15* 26或37是藉由沈積或濺鍍且隨後被結 構化而產生。其可作爲硬遮罩使其下方之各層被結構化。 介電質覆蓋層25或35藉由沈積（較佳是在與先前各介 電質層23或33及鐵電質層24，34沈積時相同之程序室 中進行）且隨後意被結構化而形成。 介電質側面覆蓋區36可藉由沈積和非等向性蝕刻而以 間隔層（spacer)之形式產生而成。呙一方式是其亦可由 與介電質覆蓋層35相同之材料產生而成。在此種情況下 在鐵電質層34結構化之後沈積介電質覆蓋層35且進行 ------ ---------裝--- ..~, (請先閲讀背面之注意事項iv%窝本頁) 訂： 「 --線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐>Ce02 is also suitable as a diffusion barrier for hydrogen. When manufacturing these semiconductor components, an annealing process is usually performed in a forming gas (which contains hydrogen) at the end of the process. The ferroelectric layer is degraded by this form of gas-annealing process because the ferroelectric material is sensitive to hydrogen. The ferroelectric layer is protected from being affected by the diffusion of hydrogen by providing a ferroelectric covering layer composed of this material, which serves as a diffusion barrier for hydrogen. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics Semiconductor substrates have at least one material in the area of ferroelectric transistors, which is suitable for making electronic circuit components. Such materials preferably contain silicon and / or germanium. Especially single crystal silicon wafers or SOI substrates are suitable for use as semiconductor substrates. Especially doped polycrystalline silicon, platinum or tungsten are suitable as gate electrodes. In addition, the gate electrode may have a multilayer structure. Especially in this multilayer paper, the Chinese national standard (CNS) A4 specification (210 X 297 mm) applies. 456045 A7 B7. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. The description of the invention (^) can form two. Polar body structure. The ferroelectric transistor may be a P · or η · channel-transistor, which may be an enhanced transistor or a depletion transistor. The present invention will be described in detail in the following with reference to the embodiments in the drawings. Figure 6 is a brief description of the figure: Figure 1 is a cross-sectional view of a ferroelectric transistor. The dielectric intermediate layer is composed of an element contained in the ferroelectric layer. Made of oxide. Figure 2 Sectional view of a ferroelectric transistor with a dielectric interlayer and a dielectric coating. Fig. 3 is a cross-sectional view of a ferroelectric transistor, wherein the ferroelectric layer is completely surrounded by a dielectric material. A semiconductor substrate 11 composed of single crystal silicon (which has a doping substance concentration in a surface region) Are several P-doped regions of 1016 cm_3), and two source / drain regions 12 are arranged, which are n + -doped and the dopant concentration is several 10 2 Gca · 3 (Figure 1 ). This portion of the substrate 11 between the two source / drain regions 12 and adjacent to the surface of the semiconductor substrate 11 is used as a channel region. This region of the transistor may contain an additional doping to adjust the turn-on voltage. A dielectric intermediate layer 13 is disposed on the surface of the channel region. The dielectric interlayer 13 contains Ti02 and has a thickness of 7ηκ. A ferroelectric layer 14 is disposed on the surface of the dielectric intermediate layer 13 and contains PZTtPbZrhTixOd and has a thickness of 150 nm. A gate electrode 15 made of platinum is disposed on the surface of the pseudo-electrode 14 and has a thickness of about 50 to 100 nm. !! · Packing · 1Ϊ (Please read the note on the back first? Matters # · -Fill in this page) Order-This paper size applies to the Chinese national standard < CNS > A4 specification (210 X 297 mm) 456045 A7 B7 V. Description of the Invention (h) Another way is that the dielectric interlayer 13 contains Ta205 and has a thickness of 5 to 10 nm. In this case, the ferroelectric layer 14 contains SBT (SrBi2Ta209) and has a thickness of 100 to 150 nm. 'In such a semiconductor substrate 21 composed of single crystal silicon (which has several p-doped regions with a concentration of 10 wcm · 3 dopant in the surface region), two source / drain regions 22 are arranged. It is n + -doped and the doping substance concentration is 102ecm · 3 (Fig. 2). This region between the two source / drain regions 22 and adjacent to the surface of the semiconductor substrate 21 is used as a channel region. This channel region of the transistor may contain additional doping in order to adjust the on-voltage v. A dielectric interlayer 23 is provided on the surface of the channel region, which contains Ta205 and has a thickness of 5 to 15nra ° in the dielectric interlayer A ferroelectric layer 24 is disposed on the surface of 23, and it contains SBT (SrBi2Ta209) and has a thickness of 100 to 150 ll11. A dielectric coating layer 25 is disposed on the surface of the ferroelectric substrate 24, which contains B 1'02 and has a thickness of 5 nm. A gate electrode 26 made of platinum is disposed on the surface of the dielectric coating layer 25, and its thickness is 50 to 100 nra. In such a semiconductor substrate 31 made of single crystal silicon (which has One dopant concentration is a number of 10Mcra · 3 p. Doped regions. Two source / drain regions are configured, which are n + -doped and the dopant concentration is several 102ecm · 3 ( (Figure 3). A portion of the semiconductor substrate 31 disposed between the two yoke / drain regions 32 is used as a channel region. This region of the transistor may contain additional doping to adjust the on-voltage. Dispose the dielectric on the surface of the channel area. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the first item on the back and fill in this page). Printed by the Bureau's Consumer Cooperatives 4 Consumer Co-operation of the Intellectual Property Bureau of the Ministry of Economic Affairs Fi China 6 0 4 5 A7 ___B7 _____ V. Description of the Invention (7) Interlayer 33, which contains Ta2Os and a thickness of 5 to 10 nm. A ferroelectric layer 34 made of SBT (SrBi2Ta209) is arranged on the surface of the interfacial intermediate layer 33, and its thickness is 100 to 150 ηη. A surface of the ferroelectric calendar 34 is provided with a dielectric coating layer 35, which contains Ta 205 and the thickness is 5 to 10 nm. 6 The dielectric intermediate layer 33, the ferroelectric layer 34 and the dielectric covering layer 35 are covered by a dielectric side covering area 36 made of Ce02. A gate electrode is arranged on the surface of the electric capping layer 35, which contains n + -doped polycrystalline silicon. The thickness of the gate electrode 37 is 100 to 200 nm. The ferroelectric transistor of the present invention is similar to a standard MOS transistor. Manufacturing. Dielectric intermediate layer 13, 23 or 33 and ferroelectric layer 14, 24 or 3 4 is made in the only process chamber by a deposition process in a CVD process or by sputtering and subsequent structuring. Source / drain regions 12, 22 or 32 are formed by implantation or diffusion The gate electrode 15 * 26 or 37 is produced by deposition or sputtering and then structured. It can be used as a hard mask to structure the layers below it. The dielectric cover layer 25 or 35 is deposited by (It is preferably performed in the same process chamber as the previous dielectric layers 23 or 33 and the ferroelectric layers 24 and 34 were deposited) and is then intended to be structured to form. The dielectric side coverage area 36 can be borrowed It is produced by deposition and anisotropic etching in the form of a spacer. One way is that it can also be produced from the same material as the dielectric coating 35. In this case, ferroelectric After the structure layer 34 is structured, a dielectric cover layer 35 is deposited and carried out ------ --------- installation --- .. ~, (Please read the precautions on the back first. (Page) Order: "--The size of the paper used in the paper is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm >

Claims (1)

^ 456045 0ς88ςρ ABCD^ 456045 0ς88ςρ ABCD ' -Λ-Ν 厲請委員明示豺年1>ικ:!^π所提」 終正本有無费更實贺.£容是否准-T#-正 經濟部智慧財產局員工消費合作社印製 、申請專利範圍 （89年12月修正> 1. 一種鐵電質電晶體*其特徵爲： •在半導體基板（11)中設有二個源極/汲極區U2)及 一個介於其間之通道區， -在通道區之表面上配置一個介電質中間層（13)’ -介電質中間層（13)上方配置鐵電質層（14)及閘極電 極（15)， -介電質中間層（13)含有一種元素之氧化物，此種元 素亦包含在鐵電質層之材料中。 2. 如申請專利範圍第1項之鐵電質電晶體’其中鐵電質 層（14)含有331'(3“丨2了3209)且介電質中間層（13)含 有 Ta205 。 3·如申請專利範圍第2項之鐵電質電晶體，其中此介電 質中間層（13)之厚度是3至20nm。 4·如申請專利範圍第1項之鐵電質電晶體，其中鐵電質 層（14)含有PZT(PbZrxTi ^02)且介電質中間層（1 3 ) 含有Ti02 » 5. 如申請專利範圍第1項之鐵電質電晶體，其中此介電 質中間層（13)之厚度是3至20nm。 6. 如申請專利範圍第1至5項中任一項之鐵電質電晶體 ，其中此介於鐵電質層（24)和閘極電極（26)之間配置 一種介電質覆蓋層（25)。 7. 如申請專利範圍第6項之鐵電質電晶體，其中此介電 質覆蓋層（25)所含有之材料是和介電質中間層（23)者 相同。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝---：----tTi-------線 {請先間讀背面之注意事項再填寫本頁) \ 5 6 Ο 4 〇 as Β8 C8 D8 六、申請專利範圍 8. 申請專利範圍第6項之鐵電質電晶體，其中此鐵電質 層（34)在側面上介電質側面覆蓋區（36)所圍繞。 9. 申請專利範圍第7項之鐵電質電晶體，其中此鐵電質 層（34)在側面上介電質側面覆蓋區（36)所圍繞《 10. 如申請專利範圍第8項之鐵電質電晶體，其中此介電 質側面覆蓋區（36)含有 Ce02，Zr02，Si02_Si3N4。 11. 如申請專利範圍第1項之鐵電質電晶體，其中此閘極 電極（15,26)含有鉑，鋁，摻雜之多晶矽或鎢。 12. 如申請專利範圍第6項之鐵電質電晶體，其中此閘極 電極（15,26)含有鉑，鋁，摻雜之多晶矽或鎢。 13. —種鐵電質電晶體之製造方法，此鐵電質電晶體是 申請專利範圍第1至第12項中任一項所述者，其特徵 校 · 麻 ♦ 該介電質中間層（13)和鐵電質層（14)是在相同之程 序室中製成》 I-------------裝 ---：----訂------I--線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制衣 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚）'-Λ-Ν Members are strongly requested to indicate the leap year 1 > ικ:! ^ Π `` The final original is free of charge and more congratulatory. 容容 是否 准 -T #-Printed and applied by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy Patent Scope (Amended in Dec. 89) 1. A ferroelectric transistor * characterized by: • There are two source / drain regions U2 in the semiconductor substrate (11) and a channel in between -A dielectric intermediate layer (13) 'is arranged on the surface of the channel region-a ferroelectric layer (14) and a gate electrode (15) are arranged above the dielectric intermediate layer (13),-the dielectric The intermediate layer (13) contains an oxide of an element which is also contained in the material of the ferroelectric layer. 2. For example, the ferroelectric transistor of item 1 of the scope of patent application, wherein the ferroelectric layer (14) contains 331 '(3 "丨 2 3209) and the dielectric intermediate layer (13) contains Ta205. 3. · 如The ferroelectric transistor in the second item of the patent application, wherein the thickness of the dielectric intermediate layer (13) is 3 to 20 nm. 4. The ferroelectric transistor in the first item of the patent application, wherein The layer (14) contains PZT (PbZrxTi ^ 02) and the dielectric intermediate layer (1 3) contains Ti02 »5. For example, the ferroelectric transistor of the scope of patent application, the dielectric intermediate layer (13) The thickness is 3 to 20 nm. 6. The ferroelectric transistor according to any one of claims 1 to 5, which is arranged between the ferroelectric layer (24) and the gate electrode (26). A dielectric coating (25). 7. For example, the ferroelectric transistor of the scope of application for patent 6, wherein the material of the dielectric coating (25) is a dielectric interlayer (23) The size of this paper applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- install ---: ---- tTi ----- --Line {Please read the note on the back first Please fill in this page for more information) \ 5 6 〇 4 〇as Β8 C8 D8 VI. Application for patent scope 8. Application for patent scope No. 6 ferroelectric transistor, in which the ferroelectric layer (34) is dielectric on the side 9. The ferroelectric transistor in item 7 of the scope of patent application, wherein the ferroelectric layer (34) is surrounded on the side by the dielectric side covering region (36). . For example, the ferroelectric transistor in the scope of patent application No. 8 in which the dielectric side covering area (36) contains Ce02, Zr02, Si02_Si3N4. The gate electrode (15, 26) contains platinum, aluminum, doped polycrystalline silicon or tungsten. 12. For example, the ferroelectric transistor in the scope of patent application No. 6, wherein the gate electrode (15, 26) contains platinum, Aluminum, doped polycrystalline silicon or tungsten. 13. —A method for manufacturing a ferroelectric transistor, the ferroelectric transistor is described in any one of the first to the 12th of the scope of patent application, and its characteristics are corrected. Hemp ♦ The dielectric interlayer (13) and the ferroelectric layer (14) are made in the same program room. I- ------------ Install ---: ---- Order ------ I--line (Please read the notes on the back before filling this page) Intellectual Property Bureau of the Ministry of Economic Affairs Clothing printed by employee consumer cooperatives 12 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 cm)
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