d 5 59 3 0 4 2 3 ! t vv f. Jo c/0 0 8 A7 B7 五、發明説明（丨） 本發明是有關於一種積體電路的製造方法，且特別是 有關於一種半導體元件的製造方法。 夾著高熔點、穩定性及低電阻率等優點，金屬矽化物 (Metal Silicide)於積體電路製程上的應用，已愈來愈普遍。 而在深次微米的積體電路技術中，由於在線寬、接觸面積 及接面深度等逐漸縮小的情況下，爲了能有效地提高元件 的工作品質’降低電阻並減少電阻及電容(RC)所造成的信 號傳遞延遲，因此傾向於採用複晶金屬矽化物閘極 (Polycide)來取代習知的複晶矽閘極，而另於接面處形成金 屬矽化物以有效降低接面處之接觸電阻（Contact Resistance) ° 一般常用的金屬矽化物包括矽化鈦、矽化鎢、矽化鎳、 矽化鉬與矽化鉑等，其中以矽化鎢的應用最爲普遍。習知 矽化鎢的形成方法係採用化學氣相沉積法，其所沉積之矽 化鎢（WSix)，其値x値約在2.6至2.8，電阻約爲每平方單 位8歐姆(8歐姆/每平方單位）。爲了降低矽化鎢阻値，使 整個閘極導體層的電阻下降，以避免過高的電阻電容時間 延遲（RC Delay)，沉積之後的矽化鎢，必須再經由一到回 火（Annealing)步驟，以使矽化鎢的阻値下降至8歐姆/每平 方單位以下。 請參照第1A圖至第1D圖，係繪示習知一種以矽化鎢 製作半導體元件之鬧極的製造流程頗面示意圖。首先請參 照第1A圖，習知在基底100上形成並定義閘極氧化層 102、複晶矽閘極層丨〇4、矽化鎢層106與氮化矽層108所 組成之閘極結構Π0之後，爲了降低矽化鎢層106的阻値， 3 ：—.-------裝------訂-----:—線 (讀先閱讀背面之注意事項再填寫本萸) 經濟部中央標準局員工消f合作社印t 木紙張尺度適用中國國家標準i AJ规格(210X297公釐） Λ7 Β7d 5 59 3 0 4 2 3! t vv f. Jo c / 0 0 8 A7 B7 V. Description of the invention (丨) The present invention relates to a method for manufacturing an integrated circuit, and more particularly to a semiconductor device. Production method. With the advantages of high melting point, stability, and low resistivity, the application of metal silicide in integrated circuit manufacturing has become more and more common. In deep sub-micron integrated circuit technology, due to the gradual reduction of line width, contact area, and junction depth, etc., in order to effectively improve the working quality of components, 'reducing resistance and reducing resistance and capacitance (RC) Due to the signal transmission delay, polycide is preferred to replace the conventional polysilicon gate, and metal silicide is formed at the interface to effectively reduce the contact resistance at the interface. (Contact Resistance) ° Commonly used metal silicides include titanium silicide, tungsten silicide, nickel silicide, molybdenum silicide, and platinum silicide. Among them, tungsten silicide is most commonly used. The conventional method for the formation of tungsten silicide is chemical vapor deposition. The tungsten silicide (WSix) deposited has a 値 x 値 of about 2.6 to 2.8 and a resistance of about 8 ohms per square unit (8 ohms per square unit). ). In order to reduce the resistance of tungsten silicide, the resistance of the entire gate conductor layer is reduced to avoid excessive RC delay. After the deposition, the tungsten silicide must go through a step of annealing. Reduce the resistance of tungsten silicide to below 8 ohms per square unit. Please refer to FIG. 1A to FIG. 1D, which are schematic diagrams showing a conventional manufacturing process for manufacturing a semiconductor element made of tungsten silicide. First, please refer to FIG. 1A. After the gate structure Π0 is formed and defined on the substrate 100, the gate oxide layer 102, the polycrystalline silicon gate layer 丨 04, the tungsten silicide layer 106 and the silicon nitride layer 108 are known and defined. In order to reduce the resistance of the tungsten silicide layer 106, 3: ————————————————————————————- (read the precautions on the back before filling in this ) Staff of the Central Bureau of Standards, Ministry of Economic Affairs, Cooperative Society, Wood, Paper Standards Applicable to Chinese National Standard i AJ Specifications (210X297 mm) Λ7 Β7
4559 3 U 4 2 3 I t \ν Γ d <.» c / 0 0 8 五、發明説明（1) 並且修補閘極氧化層102於定義閘極圖案的蝕刻過程中在 其邊角（Edge)所造成之損壞，如圖式中，標記111所示之 處，通常會進行一道回火步驟。習知回火的步驟係於爐管 (Furnace)中執行，以同時進行氧化步驟，達到使矽化鎢層 106阻値下降爲低阻値得矽化鎢層106a與強化閘極氧化層 102之目的。 然而，在爐管中進行回火步驟時，矽化鎢層106與複 晶矽層104均會發生氧化。矽化鎢層106之氧化方向係朝 向側壁以外，而複晶矽層104之氧化方向則不僅會朝向側 壁以外，而是會在側壁內外發生。由於在爐管中進行回火 步驟耗時較長，因此，在複晶矽層104與矽化鎢106之側 壁所形成之氧化層Π2(通常稱之爲輕摻雜汲極氧化層， LDD Oxide)的厚度不但厚，而且在外觀上，位於矽化鎢106 之側壁的氧化層112較突出於位於複晶矽104之側壁者， 請參照第1 B圖所示。 然而，請參照第1C圖，後續形成源極/汲極區116與 間隙壁H8之後，氧化層112的厚度較厚以及其頂部較突 出的結果，會使得所形成之間隙壁U8其厚度128變得較 薄。當介電層120覆蓋於基底100上之後，於其中形成自 動對準接觸窗122過程中，一旦其蝕刻程序的蝕刻選擇比 不足而對間隙壁1 18造成損壞時，由於間隙壁118之厚度 128不足，將可能使得間隙壁U8被蝕穿而裸露氧化層 H2。而一般使用於介電層120之材質與氧化層112的蝕 刻性質又極爲相似，因此，當氧化層112裸露出來之後， 則很可能會完全被蝕刻去除，而造成塡入自動對準接觸窗 4 ^---.-------U------.玎------1^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作祍印製 本紙诙尺度適用中国國家標準（CNS )八4規格（210X2耵公犛） ' "" 4 5 5 9 3 0 4 23 ! [\ν Γ4559 3 U 4 2 3 I t \ ν Γ d <. »c / 0 0 8 V. Description of the invention (1) and repairing the gate oxide layer 102 at its edges (Edge) during the etching process defining the gate pattern ) Damage, as shown in the figure, marked 111, a tempering step is usually performed. The conventional tempering step is performed in a furnace tube to perform the oxidation step at the same time, so as to reduce the resistance of the tungsten silicide layer 106 to a low resistance to obtain the tungsten silicide layer 106a and strengthen the gate oxide layer 102. However, during the tempering step in the furnace tube, both the tungsten silicide layer 106 and the polycrystalline silicon layer 104 are oxidized. The oxidation direction of the tungsten silicide layer 106 is toward the outside of the side wall, and the oxidation direction of the polycrystalline silicon layer 104 is not only toward the outside of the side wall, but also occurs inside and outside the side wall. Since the tempering step in the furnace tube takes a long time, the oxide layer Π2 (commonly referred to as a lightly doped drain oxide layer, LDD Oxide) formed on the side walls of the polycrystalline silicon layer 104 and the tungsten silicide layer 106 The thickness is not only thick, but also in appearance, the oxide layer 112 located on the sidewall of tungsten silicide 106 is more prominent than the sidewall of polycrystalline silicon 104, please refer to FIG. 1B. However, please refer to FIG. 1C. After the source / drain region 116 and the spacer H8 are subsequently formed, the thickness of the oxide layer 112 is thicker and the top of the oxide layer 112 is more prominent. As a result, the thickness of the formed spacer U8 is 128. Get thinner. After the dielectric layer 120 is covered on the substrate 100, in the process of forming the automatic alignment contact window 122 therein, once the etching selection ratio of the etching process is insufficient to cause damage to the spacer 1 18, the thickness 128 of the spacer 118 is 128 If it is insufficient, the spacer U8 may be eroded and the oxide layer H2 is exposed. Generally, the material used for the dielectric layer 120 and the etching property of the oxide layer 112 are very similar. Therefore, when the oxide layer 112 is exposed, it is likely to be completely removed by etching, which will cause the intrusion to automatically align the contact window 4 ^ ---.------- U ------. 玎 ------ 1 ^ (Please read the notes on the back before filling out this page) Employees of the Central Bureau of Standards, Ministry of Economic Affairs, Consumer Consumption Cooperation诙 The dimensions of the printed paper are in accordance with China National Standards (CNS) 8-4 specifications (210X2). '&Quot; " 4 5 5 9 3 0 4 23! [\ Ν Γ
:/OOS A7 B7 經濟部中央標準局員工消.費合竹社印裂 五、發明説明（令） 122之金屬層126與複晶矽層104或矽化鎢層106a發生不 期望的短路現象，如第1D圖虛線130所示之處。 習知爲避免上述氧化層112厚度過厚所衍生的問題， 通常會以降低爐管溫度的方式或是採用縮減回火時間的 方法進行回火的程序。然而，上述二種方法雖可使氧化層 112的厚度變得較薄，但是，矽化鎢層106的阻値卻不能 有效的降低以達到需求。 有鑑於此，本發明提供一種半導體元件的製造方法， 以解決習知在爐管中進行回火步驟時，無法兼顧降低輕摻 雜汲極氧化層厚度、不均勻性以及閘極之矽化鎢層阻値的 問題。 本發明提出一種半導體元件的製造方法，此方法係將 已形成有一層矽化鎢層的基底置於反應室中，通入純氧 氣、一氧化二氮氣體或是以惰性氣體稀釋的氧氣，進行快 速熱氧化步驟，以降低矽化鎢層的阻値，並使得矽化鎢層 之側壁上所形成之氧化層的厚度較薄於習知者。 依照本發明實施例所述，上述之快速熱氧化步驟係在 攝氏850度至1100度之間進行，所需時間爲10秒至120 秒。由於此步驟係在攝氏850度至1100度的高溫環境下進 行，因此可以使矽化鎢層的阻値由每平方單位爲8歐姆下 降爲每平方單位5至6歐姆。而且，由於此步驟的時間非 常短，因此，矽化鎢層側壁所形成之氧化層可以較薄且較 爲均勻，以使後續所形成之間隙壁之厚度較厚，避免習知 間隙壁厚度過薄所衍生的問題。此外，當此矽化鎢層係用 以製作閘極時，則在定義閘極圖案的過程中，蝕刻程序對 I---------霁------1T-----.1^ (請先閱讀背面之注意事項再填寫本頁) ΐ—纸張尺度適用肀國國家標準（CNS )如设格（2 1 ϋ X 297公釐 455930 42 3li .d υ c / 0 0 8 Α7 Β7 五、發明説明（0) 閘極之閘極氧化層其邊角所造成之損壞，亦可以在此快速 熱氧化步驟中予以補強。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1D圖，係繪示習知一種半導體元件的製 造流程的剖面示意圖；以及 第2A圖至第2D圖係繪示根據本發明之一較佳實施 例，一種之半導體元件之製造流程的剖面圖。 圖式之標記說明： 100 ' 200 基底 102 ' 202、202a 聞極氧化層 104、204、204 a 複晶砂層 106a、206、206a、206 b 矽化鎢層 氮化矽層 (請先閱讀背面之注意事項再填寫本頁) *-° Γ 經濟部中央標準局員工消贫合作社印製 106 108 110 111 118 120 122 126 1.28 130 208 210 閘極結構 211 缺陷 218 間隙壁 220 介電層 222 自動對準接觸窗 金屬層 厚度 短路之處 208a 頂蓋層 Μ民張尺度適π巾歐國家標準f. CNS ) Λ4規格210X297公釐） :/()08 A7 B7 經濟部中央標準局员工消費合泎.杜印^ 五、發明説明（女 224 距離 226 導體層 實施例 本發明之實施例係以矽化鎢金屬層應用於閘極時其半 導體元件之製造方法作爲說明，然而，本發明之方法並不 限定於閘極之應用，亦可以適用於以矽化鎢作爲導線或位 元線的製程當中。 首先，請參照第2A圖，提供一基底2〇〇,在此基底200 上已形成有一層閘極氧化層202、複晶矽層204、矽化鎢金 屬層206與頂蓋層208。閘極氧化層202的形成方法例如 爲熱氧化法，而複晶矽層204的形成方法例如爲化學氣相 沉積法。矽化鎢層206的形成方法例如是以六氟化鎢（WF6) 與矽烷爲氣體源，在攝氏300度至400度之間，以低壓化 學氣相沉積法，將矽化鎢層206沉積於複晶矽層204之 上。所沉積之矽化鎢（WSix)層206，其X値之大小約在2.6 至2·8左右’阻値約爲每平方單位8歐姆。頂蓋層208之 材質例如爲化學氣相沉積法所形成之氮化矽。 接著’請參照第2Β圖，以典型的微影成像與蝕刻程 序定義上述之頂蓋層208、矽化鎢金屬層206、複晶矽層 2〇4與閘極氧化層202，以形成由頂蓋層208a、矽化鎢金 屬層206a、複晶矽層2〇4a與閘極氧化層202a所組成之閘 極結構210。 然後’請參照第2C圖，與習之方法不同的是本發明 之熱氧化步驟係在反應室（Chamber)中進行，其可以快速 熱氧化（Rapid Therinai 〇xidation，RTO)的方式，使上述所 (諳先閱讀背面之注意事項再填寫本頁j ---------------^------ΪΤ-----，—線’--.——^----- 太紙張（㈣財㈣綠& A7 B7 455930 423 I twf doc/008 五、發明説明（匕） 沉積之矽化鎢（WSix)層206a，其X値之大小由2.6至2.8 左右下降爲2.2的矽化鎢層206b，此矽化鎢層206b之電 阻較低、且較爲穩定。此步驟的施行，亦可以使閘極氧化 層202a其邊角處再度發生氧化，而形成氧化層212,以強 化在上述之蝕刻程序中，於其邊角處所產生之缺陷21 1(繪 示於第2B圖）。較佳的快速熱氧化步驟係通入純氧氣、一 氧化二氮氣體，或是以惰性氣體，例如爲氮氣予以稀釋的 氧氣爲氧化氣體源，在攝氏850度至1100度的溫度之下， 進f了的時間爲10秒至12 0秒。 由於此步驟係在攝氏850度至1100度的高溫環境下進 行，因此可以使矽化鎢層206 a的阻値由每平方單位爲8 歐姆下降爲每平方單位5至6歐姆的矽化鎢層206b。而 且，由於施行此步驟的時間非常短，因此，即使矽化鎢層 206b與複晶矽層204a其側壁氧化的特性有所差異，其所 形成之氧化層212之厚度的差異性亦不會有明顯的差距， 而且所形成之氧化層212其厚度亦較薄於習知方法所形成 者。因此，由於本發明之方法可以使氧化層212的厚度較 薄且較爲均勻，故，不會有習知方法所形成之氧化層厚度 不均且過厚，使得後續所形成之間隙壁過薄以及其所衍生 的問題。 其後，請參照第2D圖，在基底200中形成源極/汲極 區216,並在閘極結構210之側壁形成間隙壁218。其後’ 在基底200上覆蓋的一層介電層220，並在其中形成自動 對準接觸窗222。由於間隙壁218與氧化層212之間的距 離224因氧化層212的厚度較薄且較爲均勻而得以延長。 i: / OOS A7 B7 Employees of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China. Feizhuzhu Printing 5. Disclosure of the Invention (Order) 122 The metal layer 126 and the polycrystalline silicon layer 104 or tungsten silicide layer 106a have an unexpected short circuit, such as The place indicated by the dotted line 130 in FIG. 1D. Conventionally, in order to avoid the problems caused by the excessive thickness of the above-mentioned oxide layer 112, the tempering process is usually performed by reducing the temperature of the furnace tube or by reducing the tempering time. However, although the above two methods can make the thickness of the oxide layer 112 thinner, the resistance of the tungsten silicide layer 106 cannot be effectively reduced to meet the demand. In view of this, the present invention provides a method for manufacturing a semiconductor device to solve the conventional problem of reducing the thickness, unevenness of the lightly doped drain oxide layer, and the tungsten silicide layer of the gate electrode when performing the tempering step in the furnace tube. The problem of obstruction. The invention provides a method for manufacturing a semiconductor device. This method is to place a substrate having a tungsten silicide layer formed in a reaction chamber, and pass in pure oxygen, dinitrogen monoxide, or oxygen diluted with an inert gas to perform rapid operation. The thermal oxidation step is to reduce the resistance of the tungsten silicide layer and to make the thickness of the oxide layer formed on the sidewall of the tungsten silicide layer thinner than that of a conventional person. According to the embodiment of the present invention, the above rapid thermal oxidation step is performed between 850 ° C and 1100 ° C, and the time required is 10 seconds to 120 seconds. Since this step is performed in a high temperature environment of 850 ° C to 1100 ° C, the resistance of the tungsten silicide layer can be reduced from 8 ohms per square unit to 5 to 6 ohms per square unit. Moreover, since the time of this step is very short, the oxide layer formed on the sidewall of the tungsten silicide layer can be thinner and more uniform, so that the thickness of the subsequently formed spacer wall is thicker and the thickness of the conventional spacer wall is avoided to be too thin Derived problems. In addition, when this tungsten silicide layer is used to make a gate electrode, in the process of defining the gate pattern, the etching process is performed on I --------- 霁 ------ 1T ---- -.1 ^ (Please read the notes on the back before filling out this page) ΐ—The paper size applies the national standard (CNS) such as the grid (2 1 ϋ X 297 mm 455930 42 3li .d υ c / 0 0 8 Α7 Β7 V. Description of the invention (0) Damage caused by the corners of the gate oxide layer of the gate can also be reinforced in this rapid thermal oxidation step. In order to make the above and other purposes, features, The advantages and advantages can be more obvious and easy to understand. The following is a detailed description of a preferred embodiment and the accompanying drawings. The brief description of the drawings is as follows: Figures 1A to 1D show a conventional semiconductor A schematic cross-sectional view of the manufacturing process of the device; and FIGS. 2A to 2D are cross-sectional views showing the manufacturing process of a semiconductor device according to a preferred embodiment of the present invention. 102 '202, 202a, oxidized oxide layer 104, 204, 204 a polycrystalline sand layer 106a, 206, 206a, 206 b tungsten silicide Silicon nitride layer (Please read the notes on the back before filling this page) *-° Γ Printed by the Poverty Alleviation Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 106 108 110 111 118 120 122 126 1.28 130 208 210 Gate structure 211 Defect 218 The partition wall 220 dielectric layer 222 automatically aligns with the thickness of the metal layer of the contact window and short circuit 208a The top cover layer M scale is appropriate π European standard f. CNS) Λ4 size 210X297 mm): / () 08 A7 B7 Economy Consumption of employees of the Central Bureau of Standards. Du Yin ^ V. Description of the invention (female 224 distance 226 conductor layer embodiment The embodiment of the present invention is described using a method of manufacturing a semiconductor element when a tungsten silicide metal layer is applied to a gate electrode. However, the method of the present invention is not limited to the application of a gate electrode, and can also be applied to a process using tungsten silicide as a wire or a bit line. First, please refer to FIG. 2A to provide a substrate 200, where A gate oxide layer 202, a polycrystalline silicon layer 204, a tungsten silicide metal layer 206, and a cap layer 208 have been formed on 200. The method for forming the gate oxide layer 202 is, for example, a thermal oxidation method, while the polycrystalline silicon layer 204 Forming party For example, the chemical vapor deposition method. The method for forming the tungsten silicide layer 206 is, for example, tungsten hexafluoride (WF6) and silane as a gas source at a temperature of 300 ° to 400 ° C. A tungsten silicide layer 206 is deposited on the polycrystalline silicon layer 204. The deposited tungsten silicide (WSix) layer 206 has an X 値 size of about 2.6 to about 2.8 'and a resistance of about 8 ohms per square unit. The material of the cap layer 208 is, for example, silicon nitride formed by a chemical vapor deposition method. Next, please refer to FIG. 2B. The above-mentioned cap layer 208, tungsten silicide metal layer 206, polycrystalline silicon layer 204 and gate oxide layer 202 are defined by a typical lithography imaging and etching procedure to form a top cap. The gate structure 210 is composed of a layer 208a, a tungsten silicide metal layer 206a, a polycrystalline silicon layer 204a, and a gate oxide layer 202a. Then, please refer to FIG. 2C. The difference from Xi's method is that the thermal oxidation step of the present invention is performed in a reaction chamber (Chamber), which can rapidly thermally oxidize (Rapid Therinai Oxidation, RTO), so that (谙 Please read the precautions on the back before filling in this page j --------------- ^ ------ ΪΤ -----, —line '--.—— ^ ----- Taiji Paper (㈣ 财 ㈣ 绿 & A7 B7 455930 423 I twf doc / 008 V. Description of the invention (dagger) The deposited tungsten silicide (WSix) layer 206a has a size of X 値 from 2.6 to 2.8 The tungsten silicide layer 206b, which dropped to 2.2 from the left and right, has a low resistance and is relatively stable. The performance of this step can also cause the gate oxide layer 202a to oxidize again at its corners to form an oxide layer. 212, to strengthen the defects 21 1 (illustrated in Figure 2B) generated in the corners of the above etching process. The preferred rapid thermal oxidation step is to pass pure oxygen, nitrous oxide gas, or Oxygen gas source is oxygen, which is diluted with inert gas, such as nitrogen. At a temperature of 850 ° C to 1100 ° C, the time of f is 1 0 seconds to 120 seconds. Since this step is performed in a high temperature environment of 850 ° C to 1100 ° C, the resistance of the tungsten silicide layer 206 a can be reduced from 8 ohms per square unit to 5 to 6 per square unit. Ohmic tungsten silicide layer 206b. Moreover, since the time for performing this step is very short, even if the characteristics of the sidewall oxidation of the tungsten silicide layer 206b and the polycrystalline silicon layer 204a are different, the thickness of the oxide layer 212 formed There will be no obvious difference in the difference, and the thickness of the formed oxide layer 212 is also thinner than those formed by conventional methods. Therefore, the method of the present invention can make the thickness of the oxide layer 212 thinner and more uniform. Therefore, there will be no uneven and excessive thickness of the oxide layer formed by the conventional method, which will cause the subsequent formation of the partition wall to be too thin and its problems. Thereafter, please refer to FIG. 2D in the substrate 200 A source / drain region 216 is formed, and a gap wall 218 is formed on the side wall of the gate structure 210. Thereafter, a dielectric layer 220 is covered on the substrate 200, and an automatic alignment contact window 222 is formed therein. Wall 218 with oxidation The distance 224 by the thickness of the oxide layer 212 is thinner and more uniform and is extended between the 212. I
I 8 ! .—.-------^------V------$ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局一®:工消贽合：&、社印製 纸伕尺度域;r；中忒國家標準，:CNS 1 Λ4#,格· ：!】0〆以7公趋.i 經濟部中央標準扃員工消費合泎社印？ili 455930 a 7 423 I (wf doc/008 __B7 五、發明説明（’）） 因此，本發明之方法可以避免習知，請參照第1C圖，在 形成自動準接觸窗1 2 2的過程中，一旦其触刻程序的触 刻選擇比不足而對間隙壁〗1 8造成損壞時，由於間隙壁 1 18之厚度過薄’使得間隙壁1 18被蝕穿，造成氧化層112 被蝕刻去除，導致的塡於自動對準接觸窗122之導體層 126與複晶矽層104或矽化鎢層106a發生的短路現象。 因此，依照以上實施例所述，本發明在反應室中進行 高溫快速熱氧化步驟之優點是可以強化閘極氧化層在定 義閘極結構之蝕刻過程中所造成缺陷、降低矽化鎢層之阻 値，並且使形成於複晶矽層與矽化鎢層之側壁的氧化層的 厚的變得較薄且較爲均勻。因此，可以避免習知無法兼顧 降低輕摻雜汲極氧化層厚度、不均勻性以及閘極之矽化鎢 層阻値所衍生的問題。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 9 (請先閱讀背面之注意事項再填寫本頁) --^--------^-I.-------^------π-----ί ^ — 1.---I 8! .—.------- ^ ------ V ------ $ (Please read the notes on the back before filling this page) Elimination: &, printed paper scale scale; r; China National Standard :: CNS 1 Λ4 #, Grid ·: 0] to 7 common trends. I Central Standard of the Ministry of Economics 扃 Employee Consumption Social seal? ili 455930 a 7 423 I (wf doc / 008 __B7 V. Description of the invention (')) Therefore, the method of the present invention can be avoided. Please refer to FIG. 1C in the process of forming the automatic quasi-contact window 1 2 2 Once the gap selection ratio of the engraving process is insufficient to cause damage to the partition wall, the thickness of the partition wall 118 is too thin, so that the partition wall 18 is eroded, and the oxide layer 112 is etched away, resulting in The short circuit phenomenon between the conductive layer 126 of the automatic alignment contact window 122 and the polycrystalline silicon layer 104 or the tungsten silicide layer 106a occurs. Therefore, according to the above embodiments, the advantages of performing the high-temperature rapid thermal oxidation step in the reaction chamber of the present invention are that it can strengthen the defects caused by the gate oxide layer during the etching process to define the gate structure and reduce the resistance of the tungsten silicide layer In addition, the thickness of the oxide layer formed on the sidewall of the polycrystalline silicon layer and the tungsten silicide layer becomes thinner and more uniform. Therefore, it is possible to avoid the problems caused by the inability to reduce the thickness, non-uniformity of the lightly doped drain oxide layer, and the resistance of the tungsten silicide layer of the gate. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 9 (Please read the notes on the back before filling out this page)-^ -------- ^-I .------- ^ ------ π ----- ί ^ — 1 .---
ϋΚ度適;η中闺κ家燥準（cvs) λ识,¾ ; 公霉ϋΚ 度 适; η 中 闺 κ 家 燥 准 (cvs) λ, ¾; male mold