4 52 9 / I五、發明說明（1) 本發明係有關於一種CCD (電荷耦合元件； charge-coupled device)的製造方法，特別是有關於一 種可改善CCD之電荷轉移效率（charge transfer efficiency; CTE)及避免相鄰之轉移閘極電極 (transfer gate electrode)發生短路的+導體製程。 習知技術 CCD係甴許多沿著半導體矽基底表 ............. 極體所構成’使其具有移位暫存器（shift register )或 順序記憶器的功能。當一個反轉電壓（inverting voltage )施加到一M0S二極體時，會得到兩種態（state )。非平衡態會擴大半導體基底表面下方的深^乏區 (deep depletion region)，在少數載子累積時則為平 衡態。當這兩種位階分別代表數位的〇釦丨時，則形成具 操作性質的元件1此，當許多少數載子從^衡離連 ，移到平衡態時，則產生電位的類比訊龍。利用上述的、 CCD可以得到密度極高的移位暫存器或是順音 地應用在影像處理系統和數位信號處理7统中 :如掃描器 '數位相機、傳真機、影 =中 置之内部架構的示意圖。，上==測裝 感應單元（Ρ,〜Ρ )、且有雷H像裝置包括影像 份。當光線入射至影像感應單元（p '以及輪出電路部 轉為電荷而累積然後在場位移f 1〜Pn )時，光能會被4 52 9 / I V. Description of the invention (1) The present invention relates to a method for manufacturing a CCD (charge-coupled device), and particularly to a method capable of improving charge transfer efficiency (CCD) of a CCD; (CTE) and + conductor process to avoid short circuit between adjacent transfer gate electrodes. Conventional technology CCD is based on a lot of semiconductor silicon substrates.............. The polar body is formed to make it have the function of shift register or sequence memory. When an inverting voltage is applied to a MOS diode, two states are obtained. The non-equilibrium state enlarges the deep depletion region below the surface of the semiconductor substrate, and becomes an equilibrium state when minority carriers accumulate. When these two levels represent the digits of the digits, respectively, an element with operational properties is formed. When many minority carriers move from equilibrium to equilibrium, an analogy of potential is generated. Using the above-mentioned CCD, a very high-density shift register can be obtained or applied in a smooth manner in image processing systems and digital signal processing systems: such as scanners' digital cameras, fax machines, and video cameras. Schematic diagram of the architecture. , Upper == test equipment induction unit (P, ~ P), and the H-image device includes an image. When light is incident on the image sensing unit (p 'and the wheel-out circuit section are converted into electric charges and accumulated, and then the field displacement f 1 ~ Pn), the light energy will be
Uield shlft )期間傳送 4 529 7 7 五、發明說明（2) 到對荷轉移部份（SH]〜Μ)，藉由將時脈信號必 1、0 2施加至電荷轉移部份（SHi‘〜SHn )的轉移閘極電 極，而依序將各電荷轉移部份（SH:〜)中所存 串列輸由至輸出放大器（〇p ),以將電荷轉換為對應之： 壓位準viffi。如上所述，因爲資料係由—系列的電荷在導 體基底内轉移，因〜此電荷轉稃的完整性和正確性 轉移效半）是相當重要的。 何 第2圖係為利用習知之CCD的半導體製程所完成之CCD 結構的頂梘圖，第3圖和第4圖分別為第2圖之I丨I _丨I ^和 IV-IV切線的剖面圖。習知在半導體矽基底2〇〇上依序形成 氧化層202、氮化層204及氧化層2 0 6的轉移閘極電極之堆 疊介電層後’於其上方繼續形成複晶矽層2〇8，之後利用 濕式熱氧化法於複晶矽層2 〇 8的表面形成氧化層2 1 〇，接著 再沈積一層複晶矽層2 1 8，並藉由乾式蝕刻法定義形成翼 形複晶矽層218 ’其中複晶矽層208和翼形複晶矽層218係 為轉移閘極電極。 然而’先前在複晶矽層2 0 8表面形成氧化層2 1 〇時，由 於複晶矽層208在靠近其下方之堆疊介電層的邊角處之氧 化層210的成長速度較他處為慢，故氧化層21〇在此處的厚 度較為薄’使得此處的絕緣效果相對較差，且電容量亦較 高，因而容易造成電荷轉移時間延遲，而影孿雷揞鳇效 率。此外，當利闬乾式餘刻免足義複晶矽層2 0 8以形成翼 形複晶矽層2 1 8時，在靠近氡化層2 1 0之角落處會有複晶矽 殘餘物2 18a (如第4圖所示）’因此造成兩個相鄰的翼形Uield shlft) 4 529 7 7 V. Description of the invention (2) To the charge transfer part (SH) ~ M), by applying the clock signal to 1, 0 2 to the charge transfer part (SHi '~ SHn) transfer gate electrode, and the serial stored in each charge transfer part (SH: ~) is sequentially input to the output amplifier (0p) to convert the charge into the corresponding: voltage level viffi. As mentioned above, because the data is transferred by the series of charges in the substrate of the conductor, the completeness and correctness of the charge transfer (the transfer effect is half effective) is quite important. The second figure is a top view of a CCD structure completed using a conventional CCD semiconductor process, and the third and fourth figures are the cross sections of I 丨 I _ 丨 I ^ and IV-IV in Figure 2 respectively. Illustration. Conventionally, a stacked dielectric layer of an oxide layer 202, a nitride layer 204, and an oxide layer 206 of a transfer gate electrode is sequentially formed on a semiconductor silicon substrate 200, and a polycrystalline silicon layer 2 is further formed thereon. 8. Then, a wet thermal oxidation method is used to form an oxide layer 2 1 0 on the surface of the polycrystalline silicon layer 2 08, and then a polycrystalline silicon layer 2 1 8 is deposited, and a wing-shaped polycrystalline is defined by dry etching. The silicon layer 218 ′ includes the polycrystalline silicon layer 208 and the wing-shaped polycrystalline silicon layer 218 as transfer gate electrodes. However, when the oxide layer 2 10 was previously formed on the surface of the polycrystalline silicon layer 208, the growth rate of the oxide layer 210 at the corners of the stacked dielectric layer near the polycrystalline silicon layer 208 was lower than that of the other layer. Slow, so the thickness of the oxide layer 21 is thinner here, which makes the insulation effect here is relatively poor, and the capacitance is also high, so it is easy to cause the delay of the charge transfer time, and affect the efficiency of the twinning. In addition, when the Ricci dry-type free-cut polycrystalline silicon layer 2 0 8 is formed to form a wing-shaped polycrystalline silicon layer 2 1 8, there will be a polycrystalline silicon residue 2 near the corner of the polycrystalline silicon layer 2 1 0. 18a (as shown in Figure 4) 'thus creating two adjacent wings
第5頁 五、發明說明（3) 複晶石夕層218發生短路’因面率。再者 在定義複晶矽層208時，暴露出的氧化層2〇丘|到 轟擊，易產，因而影響轉移閘極電極之 層仑 電性質。 ，包增的介 有鑑於此、’本發明提供—種可降低第一層複晶碎Page 5 V. Description of the invention (3) A short circuit occurred in the polycrystalite layer 218 due to the surface area. Furthermore, when the polycrystalline silicon layer 208 is defined, the exposed oxide layer 20 Å | to the bombardment is easy to produce, thus affecting the layer electrical properties of the transfer gate electrode. In view of this, the present invention provides a method for reducing the fragmentation of the first layer of multiple crystals.
角地和第二層複晶矽層間之電容量的方法，以改s 之電荷轉移效率。 τ 又吾t.CD 再者，本發明提供一種可避免靠近氧化層21〇之 處有複晶矽殘餘物發生，藉以濟免使CCD發—i短路。' :匕外’本發明提供一種可改善轉移閘極電極之介電層的品 質之方法。 因此，本發明提供一種CCD之半導體製程，其包括： 在基底上形成第一介電層，^^第一介電層上依序形成第 一複晶矽層和第二介電層，接著定義第二介電 晶砂、，使第一複晶石夕層做為第一轉移閘極雷梅，之德於 第二介電廢釦皂一棘移開極電極的側壁形成間隙壁，剝除 部份電―層後’於第二介電層二見尊一介電層 上，之後於第三介電層上形成第二轉移問 極電。 ， 依據本發明之較佳實施例’其中第—轉移閘極電極的 介電層係為第一介電層’第二轉移問極電極的介電層係為 已部份剥除的第一介電層和第三介電層。 由於第一轉移.蟬的側壁形成有間隙壁，可藉由 增加此間隙壁的尺寸以增加第一轉移閘極電極側壁的^緣 452977 五、發明說明（4) 範圍（innge fieid)，來降低第一和第二轉移閘極電 間之電容量，以改善CCD的電荷轉移效率。此外，並可藉 以避免於第一轉移間極^之I落外斜 而得以避免相鄰之第二轉移閘極電極間的短恭。 為讓本發明之上述目的、特徵及優點能更明顯易僅， 下文特舉一較佳實施例’並配合所附圖式，作詳細說明如 下 ： 【圖式簡單說明】 第1圖係概要顯示CCD影像感測裝置内部架構之示意 圖。 第2圖係緣示根據習知之半導體製程所完成之ccd的頂 視圖。 第3圖係繪示第2圖之I Π - II I切線的剖面圖。 第4圖係繪示第2圖之IV- I V切線的剖面圖。 第5 A圖至第5 E圖係繪示根據本發明一較佳實施例之 CCD的製造流程剖面圖。 【符號說明】 200〜半導體矽基底；2〇2、206、210〜氧化層； 2 0 4 -氮化層； 208、218〜複晶矽層； 2 1 8 a〜複晶石夕殘餘物；3 0 0〜基底 302、306〜氧化層； 304~氮化層； 3 0 8、3 1 8〜複晶矽層（轉移閘極電極）； 3 11〜溝槽3 1 4 a〜間隙璧； 3 0 7〜轉移閘極電極的介電層；The method of the capacitance between the corner ground and the second polycrystalline silicon layer is to improve the charge transfer efficiency of s. τ and t.CD Furthermore, the present invention provides a method to avoid the occurrence of polycrystalline silicon residues near the oxide layer 21, thereby avoiding the short circuit of the CCD. ': Dagger outside' The present invention provides a method for improving the quality of a dielectric layer of a transfer gate electrode. Therefore, the present invention provides a semiconductor process for a CCD, which includes: forming a first dielectric layer on a substrate, and sequentially forming a first polycrystalline silicon layer and a second dielectric layer on the first dielectric layer, and then defining The second dielectric crystalline sand makes the first polycrystalline spar layer as the first transfer gate ray plum, and the second dielectric waste button soap removes the side wall of the electrode electrode to form a gap, and peels off Part of the electricity-after the layer, is formed on the second dielectric layer and the second dielectric layer, and then a second transfer electrode is formed on the third dielectric layer. According to a preferred embodiment of the present invention, wherein the dielectric layer of the first transfer gate electrode is the first dielectric layer, the dielectric layer of the second transfer gate electrode is the first dielectric layer that has been partially stripped. An electrical layer and a third dielectric layer. Due to the first transfer. The side wall of the cicada is formed with a gap wall. The size of the gap wall can be increased to increase the edge of the side wall of the first transfer gate electrode. 452977 5. Description of the invention (4) The range (innge fieid) can be reduced. Capacitance between the first and second transfer gate electrodes to improve the charge transfer efficiency of the CCD. In addition, it is possible to avoid a short slope between adjacent second transfer gate electrodes by avoiding the slope of the first transfer gate electrode. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy, a preferred embodiment is given below in conjunction with the accompanying drawings, and described in detail as follows: [Simplified description of the drawings] Figure 1 is a schematic display Schematic diagram of the internal structure of a CCD image sensing device. Fig. 2 is a top view showing a CCD completed according to a conventional semiconductor process. FIG. 3 is a cross-sectional view showing a tangent line II-III in FIG. 2. FIG. 4 is a cross-sectional view showing the IV-IV tangent line in FIG. 2. 5A to 5E are cross-sectional views illustrating a manufacturing process of a CCD according to a preferred embodiment of the present invention. [Symbol description] 200 ~ semiconductor silicon substrate; 202, 206, 210 ~ oxide layer; 204-nitride layer; 208, 218 ~ polycrystalline silicon layer; 2 1 a ~ polycrystalline stone residue; 3 0 0 ~ substrate 302, 306 ~ oxide layer; 304 ~ nitride layer; 3 0 8 3 18 8 ~ polycrystalline silicon layer (transfer gate electrode); 3 11 ~ trench 3 1 4 a ~ gap 璧; 3 0 7 ~ the dielectric layer of the transfer gate electrode;
第7頁 I五、發明說明（5) | 310、312、314、3 16 介電層。 \ 【實施例】 為了避免因第一層複晶石夕層邊角處之介電層的厚度較 薄’使付第一層複晶發層易於此角落殘留，而影響CCD的 品質，因此本發明提供一種CCD的製造方法，可以分別控 制第一層複晶矽層側邊以及頂鄯的介電層之厚度，以提高 介電層的品質’而得以避免圖案化後之相鄰的第二層複晶| 矽層發生短路。 - 第5A圖至第5E圖係繪示根攄本發明一較佳實施例之 CCD的製造流程剖面圖。 首先請參照第5A圖，提供基底300，比如是半導體石夕 基底’於基底300上形成轉移閘極電極的介電層3〇7 ,比如 是由氧化層302、氮化層304和氧化層306所組成的堆疊結 構或是其他類似此性質者。之後，於轉移閘極電極的介電 層3 07上依序沈積複晶矽層3〇8和介電層31〇，再將複晶矽 層308和介電層310圖案化，以於其中形成露出轉移閘極電 極的介電層307之溝槽311，使複晶矽層308做為轉移閘極 電極之用。其中介電層31〇比如是*TE〇s為反應氣體進行 化學氣相沈積而成的氧化物，其厚度約為15〇〇埃至5〇〇〇埃 之間，且介電層31 0係在利闬非等向性蝕刻法蝕刻複晶矽、 層308時做為硬罩幕之用。 接著請參照第5B圖，於轉移閘極電極的介電層3〇7、 介電層31 0以及複晶矽層3 〇 8的表面依序順應性 (conformal )覆蓋介電層312和314。其中介電層312的Page 7 I. Description of the invention (5) | 310, 312, 314, 3 16 dielectric layer. [Example] In order to avoid that the thickness of the dielectric layer at the corners of the first polycrystalline spar layer is thinner, making the first polycrystalline hair layer easy to remain at this corner, which affects the quality of the CCD, so this The invention provides a CCD manufacturing method, which can separately control the thickness of the side of the first polycrystalline silicon layer and the thickness of the top dielectric layer, so as to improve the quality of the dielectric layer, so as to avoid the adjacent second patterned layer. Layer complex | The silicon layer is shorted. -Figures 5A to 5E are cross-sectional views showing the manufacturing process of a CCD based on a preferred embodiment of the present invention. First, please refer to FIG. 5A, a substrate 300 is provided, such as a semiconductor stone substrate. A dielectric layer 3 of a transfer gate electrode is formed on the substrate 300, such as an oxide layer 302, a nitride layer 304, and an oxide layer 306. The composition of the stacked structure or other similar to this nature. Thereafter, a polycrystalline silicon layer 308 and a dielectric layer 310 are sequentially deposited on the dielectric layer 307 of the transfer gate electrode, and then the polycrystalline silicon layer 308 and the dielectric layer 310 are patterned to be formed therein. The trench 311 of the dielectric layer 307 of the transfer gate electrode is exposed, so that the polycrystalline silicon layer 308 is used as the transfer gate electrode. The dielectric layer 310 is, for example, an oxide formed by chemical vapor deposition of * TE0s as a reaction gas, and has a thickness of about 15,000 angstroms to 50000 angstroms. It is used as a hard mask when the polycrystalline silicon and the layer 308 are etched by a non-isotropic etching method. Next, referring to FIG. 5B, the dielectric layers 3007, 310, and polycrystalline silicon layer 308 of the transfer gate electrode sequentially conformally cover the dielectric layers 312 and 314. Of which dielectric layer 312
第8頁 4 5297 五、發明說明 質較佳的是氮化妙’厚度約為10()埃至6⑽埃之間，用以做 為蝕刻終止層之罔；介電層314的材質較佳的氧化矽’比 如是由TEOS為反應氣體進行化學氣相沈積而成，厚度約為 1500埃至5000埃之間。 接著請參照第5C圖，進行非等向性蝕刻製程，佐以介 電層312為蝕刻終止層，使介電層314於溝槽3ΐι内之複晶 夕層308和其上方的介電層3iq之侧壁轉為間隙壁。 值得注意的是，藉由控制間隙壁314a的大小，可以控 制複晶石夕層30-8和後^形—成極電檸之間的側 i。卩份之，而其控制方法包括控制介電層3 1 $的沈 積厚度或者是控制蝕刻介電層314的時間。而控制複晶矽 層3 0 8頂部的介電層3 1 〇之厚度，則可以控制複晶矽層3 〇 8 和後續形成之另一轉移閘極電極之間的水平部份之電容 量。因此’增加製程的可變性。 接著請參照第5 D圖，依序剝除暴露出的介電層3〗2和 部份轉移開極電極的介電層307 (比如是氧二層63)12/直 至暴露出氮化矽層304。其中剝除介電層312的方法比如是 濕敍刻法，剝除氧化層306的方法比如是濕敍刻法。 由於在蝕刻複晶矽層3 0 8時，轉移閘極電極的介電層 307的上部份（在此實施例係指氧化層3〇 6 )已受到電漿蝕 刻的直接轟擊，故易有缺陷產生，因而會影響到整個轉移 閘極電極的介電層307之介電性質。而本發明係將此受損 傷的部份利用濕蝕刻法剝除，用以避免剩餘之轉移閘極電 極的介電層307 (在此實施例係指氮化矽層3〇4 )受到電粱Page 8 4 5297 5. Description of the invention The better quality is nitride nitride with a thickness of about 10 () angstroms to 6 angstroms, which is used as the etching stopper; the material of the dielectric layer 314 is better. For example, silicon oxide is formed by chemical vapor deposition of TEOS as a reaction gas, and has a thickness of about 1500 angstroms to 5000 angstroms. Next, referring to FIG. 5C, an anisotropic etching process is performed, and the dielectric layer 312 is used as an etch stop layer, so that the dielectric layer 314 is in the polycrystalline layer 308 in the trench 3 and the dielectric layer 3iq above it. The side wall turns into a gap wall. It is worth noting that, by controlling the size of the partition wall 314a, the polycrystalline stone layer 30-8 and the side i between the shape of the slab and the cathode can be controlled. For example, the control method includes controlling the deposition thickness of the dielectric layer 3 1 $ or controlling the time for etching the dielectric layer 314. Controlling the thickness of the dielectric layer 3 10 on top of the polycrystalline silicon layer 308 can control the capacitance of the horizontal portion between the polycrystalline silicon layer 308 and another transfer gate electrode formed later. Therefore 'increases the variability of the process. Next, referring to FIG. 5D, the exposed dielectric layer 3 and the dielectric layer 307 (such as the oxygen second layer 63) that partially transfer the open electrode are sequentially stripped. 12 / Until the silicon nitride layer is exposed 304. The method for removing the dielectric layer 312 is, for example, a wet engraving method, and the method for removing the oxide layer 306 is, for example, a wet engraving method. When the polycrystalline silicon layer 308 is etched, the upper part of the dielectric layer 307 of the transfer gate electrode (in this embodiment, the oxide layer 306) has been directly bombarded by plasma etching, so it is easy to have Defects are generated, which will affect the dielectric properties of the dielectric layer 307 of the entire transfer gate electrode. In the present invention, the damaged part is stripped by wet etching to prevent the remaining dielectric layer 307 of the transfer gate electrode (in this embodiment, the silicon nitride layer 304) from being subjected to electric beams.
4 5 2 9 7 7 五、發明說明（7) 蝕刻的傷害，再於其上方沈積一層品質較好的介電層 31 6，如第5E圖所示，以做為轉移閘極電極的介H30I的 一部份，其中介電層316的材質比如是高溫熱氧化層（HTO layer )，其厚度與氧化層306的厚度相同。 接著請繼續參照第5E圖，於整個基底300上順應性覆 蓋一層介電層316後，於介電層316上方沈積一層複晶矽層 3 1 8 ’並將其圖案化成翼形複晶矽層3丨8。上述所形成的第 一層複晶矽層308和第二層翼形複晶矽層318係做為轉移閘 極電極之用。 由上述可知，與第一層複晶矽層308對應的轉移閘極 電極之介電層307包括氡化層3〇2、氮化矽層3〇4和氧化層 306，而與第二層翼形複晶矽層318對應的轉移閘極電極之 介電層307包括氧化層3〇2、氮化矽層3〇4和介電層^ 綜上所述，本發明至少具有下列優點： 辟二“由於第—層複晶妙層外-圍的介電層係分I頂部知側 土兩卩伤’故可分^^_其_厚j，增加製程的可變性。. 勒《• 乂 t於第一層複晶石夕I外圍的介電層並非像傳統的以 熱氧化法於其表面形成 』=的： 層時，發生殘… 1:陷而而可；f:定義第二複晶石夕 之間，^短路。 而侍以避免相鄰的翼形她夕層 3. 第一層複晶妙層和笔-昆迎以、隹日"a 層厚度較為均勻。 .一一' 形複e曰矽層之間的介電 4. 藉由控制第—層 複Ba矽層側邊之間隙壁的大小，以 4 52 9 7 五、發明說明（8) 增加邊緣範圍，藉以降低此處的電容量，進而改善電荷轉 移效率。 5.不論是與第一層複晶矽層對應的轉移閘極電極之介 電層，或是與第二層翼形複晶矽層對應的轉移閘極電極之 介電層，均沒有受到電漿蝕刻的傷害，故品質較利用習知I 的CCD半導體製程所製得的為好= | 雖然本發明已以較佳實施例揭露如上，然其並非用以 限制本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可做更動與潤飾，因此本發明之保護範圍 當事後附之申請專利範圍所界定者為準。4 5 2 9 7 7 V. Description of the invention (7) Etching damage, and then deposit a good quality dielectric layer 31 6 on top of it, as shown in Figure 5E, as the dielectric H30I of the transfer gate electrode A part of the dielectric layer 316 is, for example, a high temperature thermal oxidation layer (HTO layer), and the thickness of the dielectric layer 316 is the same as that of the oxide layer 306. Next, please continue to refer to FIG. 5E. After compliantly covering a dielectric layer 316 over the entire substrate 300, a polycrystalline silicon layer 3 1 8 'is deposited on the dielectric layer 316 and patterned into a wing-shaped polycrystalline silicon layer. 3 丨 8. The first polycrystalline silicon layer 308 and the second wing-shaped polycrystalline silicon layer 318 formed as described above are used as transfer gate electrodes. It can be known from the foregoing that the dielectric layer 307 of the transfer gate electrode corresponding to the first polycrystalline silicon layer 308 includes a halide layer 302, a silicon nitride layer 304, and an oxide layer 306, and is in contrast to the second layer wing The dielectric layer 307 of the transfer gate electrode corresponding to the shaped polycrystalline silicon layer 318 includes an oxide layer 302, a silicon nitride layer 304, and a dielectric layer. In summary, the present invention has at least the following advantages: "Because the dielectric layer of the outer layer of the first-layer complex layer and the surrounding layer is divided into two, the top soil and the two lateral soils are injured, so they can be divided ^^ _ 其 _ 厚 j, increasing process variability. Le" • 《t The dielectric layer on the periphery of the first polycrystalite I is not formed on the surface by the traditional method of thermal oxidation. "=: When the layer is left, a residue occurs ... 1: sinking is OK; f: defines the second polycrystal There is a short circuit between Shi Xi. And to avoid the adjacent wing shape, she Xi layer 3. The first layer of polycrystalline layer and pen-Kun Yingyi, the next day " a layer thickness is more uniform ... one by one ' The shape is called the dielectric between the silicon layers. 4. By controlling the size of the spacer on the side of the first-layer Ba silicon layer, 4 52 9 7 V. Description of the invention (8) Increase the edge range to reduce this. Electric capacity This improves the charge transfer efficiency. 5. Whether it is the dielectric layer of the transfer gate electrode corresponding to the first polycrystalline silicon layer or the dielectric of the transfer gate electrode corresponding to the second wing-shaped polycrystalline silicon layer Layers are not damaged by plasma etching, so the quality is better than that produced by the conventional CCD semiconductor process = | Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention Anyone who is familiar with this skill can make changes and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the scope of the patent application attached.
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