TW452933B - Manufacturing method for buried tiny metal connection - Google Patents

Abstract

The present invention discloses a manufacturing method for a plurality of buried metal connections on the semiconductor substrate, which includes the following steps: first, forming a dielectric layer on the semiconductor substrate and making a plurality of insulation blocks on the upper surface of the dielectric layer; in which each insulation block has the width of 3X and there is 5X spacing between two insulation blocks; next, forming a first sidewall spacer with width of 1X on the sidewall of the insulation block; then, removing the insulation block and forming a second sidewall spacer with width of 1X on the sidewall of the first sidewall spacer; forming the filler into the gaps between the two neighbored second sidewall spacers; and, removing the second sidewall spacer; using the first sidewall spacer and the filler as the etching mask for anisotropic etching on the dielectric layer to form a plurality of trench structures in the dielectric; then, filling metal into the plurality of trenches to form a plurality of metal connections buried in the dielectric layer.

Description

452933 V. Description of the invention (1) " Field of invention: The present invention relates to a semiconductor process, in particular, a method for repeatedly manufacturing side wall spacers' to define a related process of a plurality of buried buried fine metal wires. Background of the Invention: With the continuous progress of the semiconductor industry, in the development and design of ultra-large integrated circuits (ULSI), in order to meet the design trend of high-density integrated circuits, the size of various components has been reduced to sub-micron. Although, by reducing the size of various components in the chip, a semiconductor 1C device with a high integration density can be effectively produced and the operating efficiency of the designed integrated circuit can be further improved. However, due to the continuous shrinking of components, The related semiconductor process has encountered unprecedented difficulties, and the complexity of the process has continued to increase. Generally speaking, 'in the semiconductor process', the main factor determining the degree of component accumulation is the ability of lithography. Among them, the pattern on the photomask can be transferred to the semiconductor substrate through the micro process to determine the pattern of each material layer in the integrated circuit, and thereby form the entire semiconductor circuit structure. However, as the size of the semiconductor element Continued shrinking makes patterning on light more difficult. In addition, it is subject to the lithographic resolution, exposure error (Focus) error, image transmission accuracy,

--- V. Description of the invention (2) _________ and the available space have greatly increased. , ',' All lead to the difficulty of defining subtle cases. Especially in the area of the volume φ #, hundreds of tens of ^^ are formed, which are often electronically connected to a specific area on the wafer. Design components, and the layers and functional layers used to connect these components. As a result, a variety of materials are often deposited on the wafer to increase the density of the components. However, when the components are small. In this way, the gap between these components will become extremely narrow, and it will encounter great challenges. When making metal connections between these components, it will be dry. In addition, due to the connection & t operating voltage, electrical The miniaturization of the circuit size has made the requirements of various components standard. Because :: ^ The resistance values allowed must meet the strict transmission speed. In the design of the integrated circuit of the electronic signal that reduces the excessive resistance, the gold connection pattern is often increased as much as possible. area. However, in this case, the metal pattern occupies most of the surface of the wafer, which hinders the production of other components. Therefore, how to make a large-area metal connection in a limited space to increase the element operation rate 'has become an important issue in the current semiconductor manufacturing process. Object and Summary of the Invention The object of the present invention is to provide a method for fabricating a plurality of vertical fine metal wires in a dielectric layer.

45293 3 V. Description of the invention (3) The substrate of Feng Conductor has disclosed a method for making a plurality of buried metal wires on the upper side and forming i. First, a dielectric layer is formed on a semiconductor substrate. Then the insulating layer is shown on the dielectric layer ® as a stop: two insulating layers; ϊ: = on the first insulating layer ", and touch u and mean that a plurality of insulating blocks are on the first Any two insulations C on the insulation layer have a width of 3 units (3x), and after the block, the deposition flute has an interval width of about 5 units (5x).丄 有 IV 单 =) absolutely: two to form the thickness of the first side roll M 4 χ. Next, the first film layer is etched to form a marginal block.丨 The middle gap wall is on the side wall of the insulating block, and then a plurality of absolute units (3 ×) are separated by a distance of 3 :: There are about 3 gap walls between the first side wall gap walls, and then two, followed by deposition The second film layer is interposed between the first sidewalls. The second film layer is then etched on the thick gap wall having at least about 1 unit (X). Then, the first side wall spacer is deposited on the surface of the first side wall spacer. The second layer is on the second side wall spacer and the first side material, and the thickness of the third film layer is as follows: -Membrane layers of the same material to form fillers in the phase: two soap positions (lx). The third film is etched again and the third side wall is formed :::: In the gap between the two side wall gaps, a selective etching process is used later, and = is on the second side wall gap. With-between the side wall spacer and the filler, the two side wall spacer 'is the first gap. Use the second-sidewall space; have a width of 1 unit (⑴ empty etching mask power, the first insulation layer invites the wall spacer and the filler as an electrical layer to perform anisotropy #etch,

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A plurality of trench junction walls, fillers, and first metal are formed in the plurality of trenches in the dielectric layer. Then, a plurality of spacers between the three sidewalls and the first trench are formed to form a plurality of strips, and the insulating layer between the first sidewalls is removed. Also, fill in the metal wiring. Detailed description of the invention: The present invention ^ provides a method for defining a fine metal connection in a trench. The layer "f" is repeatedly deposited on the insulating block on the surface of the semiconductor substrate, and an etching process is performed to define a sidewall gap on the insulating block. And 'controlling the thickness of the deposited film layer | J, will effectively adjust the width of the sidewall spacers produced ... The minimum allowable width of the process. Next, by using the sidewall spacer as an etching mask, the dielectric layer underneath is etched 'to produce a trench structure with a fine width. Then, the metal deposition and grinding process is performed to define the fine metal lines in these trenches. The detailed description of the present invention is as follows. Β Please refer to the first figure. 'Firstly, a semiconductor substrate 10 is provided to deposit the required film layer. [Wherein' This semiconductor substrate 10 can be used for a single crystal with a crystal orientation of &lt; 100 &gt; Shi Xilai made it up. Generally speaking, other types of semiconductor materials, such as gallium arsenide, germanium, or silicon on insulator (SOI) on the insulating layer can also be used as the semiconductor here. The substrate 10 is used. In addition, because the characteristics of the surface of the semiconductor substrate 10 do not have a special effect on the present invention, it is 45293 3 V. Description of the invention (5) The crystal orientation can also be selected as <110> or <111> . Next, a dielectric layer 12 can be formed on the upper surface of the semiconductor substrate 10. In a preferred embodiment, the dielectric layer 12 is made of a silicon oxide material having a thickness of 300 to 12 Angstroms. It should be particularly noted that before the dielectric layer 12 is formed, various active components, passive components, peripheral circuits, and the like necessary for manufacturing integrated circuits have been formed on the surface of the semiconductor substrate 10. That is, the surface of the semiconductor substrate 10 already has various functional layers and material layers required. As for the deposition of the dielectric layer 12, a chemical vapor deposition (CVD) method can be used to use tetraethyl silicon. Acid salt (TEOS) at a temperature of about 60 to 80 °. C, the pressure is about 0 to 10 Torr to form the desired silicon oxide. Then, a first insulating layer 14 may be formed on the upper surface of the dielectric layer 12. In the preferred embodiment, the 'A-th insulating layer 14 may be composed of a silicon nitride material having a yield of about 3 ㈣ to m. Among them, it can be about 400 to 45. c, and middle: the reaction gas SiH4 is introduced, and M is 3 to form the required nitride material. This first insulating layer 4 can be used as a dielectric layer 12 ′ to prevent the dielectric layer 12 ′ to prevent the dielectric layer from being etched. In the scribe process, the second insulating layer 16 is formed on the third side. In a preferred embodiment, this second absolute range is between 500 and 300 angstroms, and it passes through the ion spine 6 and is selected to have a thickness of about ′ when a hydrofluoric acid solution is used as the material. Such as clams this second insulation layer 1 6

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5. Description of the invention (6) Materials. Next, the photoresist layer 18 can be applied and defined to define the shoe engraving rate as shown in the first figure, which will be much higher than the undoped oxide stone cloth photoresist layer 18 on the upper surface of the second insulating layer 16 Perform the well-known steps of exposure, development, and cleaning, as shown in the block pattern. Referring to the second figure, after the pattern of the photoresist layer 8 is defined, the photoresist layer 18 is used as an etching mask to perform an etching process on the second insulation layer 16 until it reaches the upper surface of the first insulation layer 14. In this way, the pattern on the layer 18 can be transferred to the second insulating layer 16 to form a plurality of insulating blocks 20 of the second figure. Among them, each insulating block 20 has a width of 3 units (3X) 'and is located between any two insulating blocks 20, which is about 5 units (5X) ^ In general, when the first When the second insulating layer 16 is made of a silicon oxide material, erbium, CHF3 / CF4, CHF / 2, CH3CHF2, and CF4 / 〇e can be selected as an etchant. 3 Subsequently, the first film layer 22 can be uniformly deposited on the surfaces of the insulating block 20 and the first insulating layer 14. In a preferred embodiment, the material of the first film layer μ may be polycrystalline silicon. As for the thickness of the first film layer 22, it can be set to i units (ιχ) left 'and right according to the width unit of the above-mentioned insulating block 20. The preferred thickness can be controlled between 100 and 500 angstroms. Next, "refer to the third figure, perform a non-uniform etch-back process on the first film layer 22" to form a first sidewall spacer 24 on the sidewall of the insulating block 20. Wherein, when the material of the first film layer 22 is made of polycrystalline silicon,

Using SiCl4 / Cl2, BC13 / C12, HBr / Cl2 / 〇2, HBr / 02, Br2 / SFd SFs as an etchant 'and using reactive ion etching (RIE), the 6 = film layer 22 is subjected to an etching procedure. Please refer to the fourth figure, and then perform a selective etching process, the insulating block 20 on the semiconductor substrate 10. In this way, on the surface of the first-name, marginal layer 14, only the first-thickness partition wall 24 with a width of about i units (ιχ) will be left. And, between any two first sidewall gaps: the width of the space (spacmg) is about 3 units (3χ). Among them, the 2 ° material is doped oxide stone, and dilute hydrofluoride can be used as an elixir. The higher 1 liquid of the doped oxygen-cutting material can reduce the removal of the insulating area. The potential damage to the insulating layer 14 on the side is possible. Li 4 Xingdi — Please refer to the fifth figure, after removing the insulation = wall spacer 24 and the first insulation. The second film layer 26 can be oxidized by doping. 2. The thickness of the second film layer 26 is controlled by the sub-layer so that A is about Ai plus unit ⑽. The preferred thickness can be controlled in the order of two to one, as shown in the sixth figure to form the second Side:; ::, on the side wall where the second film is engraved. In this way, m8 is provided on each of the first side wall spacers 24 and the spacer walls 28 in / 一: 丨 the wall spacer 24 and the second The width of the `` side wall '' units.

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Etch for 1-inch solid sheet. As far as the adjacent second side wall spacer 28 is concerned, the width of the gap therebetween is approximately (1 X). In a preferred embodiment, such as anisotropic red, such as reactive ion etching, the second film layer 26 can be applied to the etchant used to remove silicon dioxide. o2, CF4 / 〇2, c4F8 / 〇2, ch2f2, c4f8. Then, referring to the seventh figure, a third film layer 30 is deposited on the first-fourth, the first sidewall spacer 24 and the second sidewall spacer 28 And the gap t on the side of the second side wall spacer 28. In a preferred embodiment, the third film layer 30 has a thickness of about 100 to 500 Angstroms' and its material can be selected from many Then, as shown in the eighth figure, the third film layer 30 is subjected to an etch-back process until it reaches the first side wall gap 24 and the second side wall gap 28 to remove the first side wall gap. The third film layer 30 on the upper surface of the wall 24 and the second side wall gap wall 28. In this way, the filler 32 a can be made into the gap between two adjacent second side wall gap walls and located at the edge A third sidewall spacer 34 is formed on the second sidewall spacer 28. Please refer to the ninth figure, and then perform a selective etching process, To remove the second sidewall spacer 28 between the first sidewall spacer 24 and the filler 32. At the same time, the second sidewall spacer 28 between the first sidewall spacer 24 and the third sidewall spacer 34 is also removed. Will be removed. Wherein, when the material of the second side wall spacer 28 is doped oxide, hydrofluoric acid vapor can be used as the etching

4 5 293 3 Five 'Explanation (9) etchants to remove them completely. In addition, since the first sidewall spacer 24, the third sidewall spacer 34, and the filler 32 are made of a polycrystalline silicon material, the inscription is not affected in this selective money-engraving process. In this way, the structure shown in the ninth figure can be formed. That is, between the adjacent first sidewall spacers 24 and the filler 32 (including the third sidewall spacers 34), there will be a gap of about 1 unit width (IX). Next, referring to the tenth figure, the first sidewall spacer 24, the filler 32, and the second sidewall spacer 34 are used as the engraved masking power to expose the exposed first insulating layer 14 and the dielectric layer 12 below it. A non-uniform etching process is performed to form a plurality of narrow trenches 36 in the dielectric layer 12. Among them, a plasma etching process such as a reactive ion etching process may be used to sequentially remove the first insulating layer 14 and the dielectric layer 12. Then, as shown in FIG. 11, the first sidewall spacer 24, the third sidewall spacer 34, the filler 32, and the remaining first insulating layer 14 located above the dielectric layer 12 are removed. Next, a metal layer µ is deposited on the dielectric layer 12 and filled in the plurality of narrow trenches 36, as shown in the twelfth figure. Subsequently, referring to the thirteenth figure, the CMP process is performed on the metal layer 38 until it reaches the dielectric layer 12 to remove a part of the metal layer 38 on the surface of the dielectric layer 12. In this way, a plurality of extremely fine buried metal lines (Ultra Hne buried metal) located between the dielectric layers and the 2 in the figure can be formed.

Unes) 40. Among them, each of the trench metal connections 40 has about 1

45293 3 V. Description of the invention (ίο) Bit width (IX) 'and there is a dielectric layer 12 with a width of about 1 unit (IX) in two adjacent trenches, to provide effective insulation and area.隔 效应。 The effect. Using the method of the present invention, it is possible to make finer and more line widths under the current line width limitation of the semi-conductive bone process. For example, in the above description, the insulating block 20 having a width of about 3X only needs to be used once. Then, the thickness of the side can be used to adjust the width of the side wall spacer. The process of depositing a film layer and defining the side wall spacer is performed on a semiconductor substrate with a 3X pattern to achieve a further purpose. Although the present invention is exemplified as above with a preferred example, the spirit of the present invention and the entity of the invention are limited to this implementation, and modifications made without departing from the spirit and scope of the present invention are included in the scope of patent application. &amp; 40 connections, with metal connection photolithography process for lithography in the metal connection 40 process, to control the deposited film. In this way, reducing the component size by defining a small width is not intended to limit it. Therefore, the following should be included in the 45293 3 formula. With the following detailed description combined with the attached instructions, the above content and the many advantages of this invention can be easily understood, of which: The first figure is the semiconductor substrate A plan view showing the steps for sequentially forming a dielectric layer, a first insulating layer, a second insulating layer, and a photoresist layer on a semiconductor substrate; the second image is a cross-sectional view of a semiconductor substrate, showing the deposition of a first film layer on Steps on the surface of the insulating block; The third figure is a cross-sectional view of the semiconductor substrate, showing the steps for defining the first sidewall spacer on the side of the insulating block; the fourth figure is a cross-sectional view of the semiconductor substrate, showing the removal of the insulating block Steps: The first gap is covered with the layer-by-layer film, the side film is two-thirds-three-dimensionally formed and shaped, and the figure is displayed. The figure is cut off; the step is cut off. The upper body of the body, the body, the surface, the guide, the guide, the half of the surface, the half of the wall, the wall, the side of the picture, the side of the picture, the fifth side, the seventh side, the first side, and the third side of the wall. Side entry, filling two floors Fill in the second step of the electric step, and move it to the wall to show the gap and the gap between the steps. Among them, the wall chart, the second side of the wall, the second wall, the second wall, and the bottom wall. The bottom half of the body, the side body, the body gap, the second half, and the second half. The side wall is a side view.

Among the steps, page 14 45293 3 Brief description of the diagram The eleventh figure is a semiconductor substrate surface view showing the steps of removing the etching mask on the dielectric layer; the twelfth figure is a cross-sectional view of the semiconductor substrate, showing A step of depositing a metal layer on the dielectric layer; and FIG. 13 is a cross-sectional view of a semiconductor substrate showing a step of defining a fine metal wire in the dielectric layer.

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Claims (1)

45 293 3 Sixth, the method of applying for a patent ^, this method of making a plurality of buried metal lines on a semiconductor substrate, the method includes at least the following steps: forming a dielectric layer on the semiconductor substrate; the The absolute marginal block is on the upper surface of the dielectric layer ... the gate of each block °° the width of two units (3 ×), and any two of the insulating regions 3 ′ have a space of about 5 units (5 ×) in width ; 彳 at a first side wall gap on the side wall of the insulating block, the first side wall gap in the basin has about! Xuandi removes the plurality of insulating blocks; forms a second sidewall spacer on the sidewall of the first sidewall spacer, and the second sidewall spacer has about 1 unit (1 X) width; forming a gap between two adjacent second side wall spacers, wherein the filler has a width of about 1 unit (IX); removing the second side wall spacer; Using the first sidewall spacer and the filler as an etching mask to perform an anisotropic engraving of the Λ; 丨 electrical layer to form a plurality of trench structures in the dielectric layer; and, filling the metal with the plurality of To form a plurality of metal lines in each of the trenches. 2. The method according to item 1 of the patent application, wherein the dielectric layer is made of silicon oxide material. The method according to item 1 of the patent application, wherein the first Side wall Page 16 45293 3 VI. Patent Application Fan® The partition wall and the filler are made of silicon materials for more than 7 days. Side 4. If the wall gap of item 1 of the scope of the patent application is made of doped oxygen cutting material, the above-mentioned method of item 5 of the scope of the patent scope, if ordered, has a trench structure of 'about] units (U) The width. The method described in item 6 of the patent application range, wherein the edge region f :: further includes: forming a silicon nitride layer on the upper surface of the dielectric layer :, ::, and the silicon nitride layer Can be used as an etch: the dielectric layer below. s 丨 ^ μ The edge is located in the spirit 7 using the method of the first scope of the patent 'wherein the above-mentioned insulating region is doped with a silicon oxide material. The wire 8 has the method of item 1 of the scope of patent application, wherein the above-mentioned metal is about 1 unit (IX) wide. Method 9 ~ Kind of making a plurality of buried metal wires on a semiconductor substrate 'The method includes at least the following steps: forming a dielectric layer on the semiconductor substrate; a layer; / forming a first insulating layer on the dielectric Layer top surface as an etch stop 452933 Forming a second insulating layer engraved with the second insulating layer on the first name, with the upper surface of the insulating layer, the width of each of them, and the interval width of any two of the insulating regions;-the upper surface of the insulating layer; defining a plurality of insulating regions Block between the first and the insulating block having 3 units (3X) between the blocks 'having about 5 units (5X) faces', wherein the first film layer wall gap wall deposits a film layer on the insulating block The insulating block table has a thickness of at least about 1 unit (1X); the first film layer is etched to form a first side wall; = the plurality of insulating blocks, of which two adjacent ones of the first There is a gap width of about 3 units (3X) between the side wall gaps; this second layer is formed on the surface of the first side wall gap, wherein the second film layer has a thickness of at least about 1 unit (IX) A etching the second film layer to form a second sidewall spacer on the first sidewall spacer; a depositing a third film layer on the surface of the second sidewall spacer and the first sidewall spacer The third film layer has the same material as the first film layer, and the first film layer The thickness of the film layer is about 1 unit (1χ); the third film layer is described to form a filler in a gap between two adjacent second sidewall spacers, and a third sidewall spacer is formed at the edge. On the second sidewall spacer; v using a selective etching process to remove the second sidewall spacer, wherein the gap between the first sidewall spacer and the filler has a gap of 1 unit (IX) in width; Page 18 452933 VI. Scope of patent application 'The wall gap wall, the third side wall gap wall and the filler are etched; two r η Γ the first insulating layer and the dielectric layer are anisotropically etched to form several The trench structure is in the dielectric layer. The first sidewall spacer, j ^ = 2 and the first insulation layer are removed, and 11 ′ filling and the second sidewall spacer are filled with metal to the plurality of trench alignment lines. Gully to form a plurality of metal companies. For example, item 9 of the scope of patent application is composed of silicon oxide material. The method, wherein the dielectric layer is escaped 11. As in the method of claim 9 in the scope of patent application, the m layer and the third film layer are made of polycrystalline silicon material. In the above-mentioned first 1 2 · method of claim 9, the film layer is made of a doped silicon oxide material. x. Article 13. The method of item 9 in the scope of patent application, the love insulating layer is made of silicon nitride material. The method of item 14. in item 9 above, the insulating layer is made of doped silicon oxide material. 15. Listing 15. The method of claim 9 of the patent scope, in which the above-mentioned gold 45293 3 6. The scope of patent application The connection has a width of about 1 unit (1 X). 16. The method according to item 9 of the scope of patent application, wherein the above procedure for defining a metal connection includes the following steps: depositing a metal layer on the upper surface of the dielectric layer and filling the plurality of trench structures; and performing chemical machinery A grinding process to remove a portion of the metal layer on the upper surface of the dielectric layer and define the metal connection in the trench structure. Page 20