TW452906B - A skew calibration means and a method of skew calibration - Google Patents

Abstract

Automatic test equipment for memory device testing with means for providing a high accuracy of transferring and receiving signals when testing a semiconductor device under test (DUT) by intelligent skew calibration of a timing system. The means for automatic skew calibration of a transceiver comprises a plurality of input registers (2, 3) for transmitting signals; a plurality of output registers (4, 5, 6) for receiving signals; a main clock driver (9) for generating a main clock signal; a reference clock driver (24) for generating reference signals for calibrating the registers; the said reference clock driver (24) being associated with the said main clock driver (9); and a plurality of phase shift means (12, 13, 14, 15, 16) comprising at least one set of phase shift means associated with each said plurality of registers, for the relative alignment of the register's timing within each plurality. The calibration is performed using a common time base which is distributed by means of a transmission line having predetermined wave characteristics.

Description

Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Sub-Ministry. 452906 V. Description of Invention (1) Description of the invention The technology of the invention The present invention is an automatic test device 用作 _tic which is used for semiconductor # g, B, ^ & mutual device test test equpment ATE) 'And more specifically, the present invention relates to a device such as a tester used to test and measure semiconductor devices such as memory and an ancient method of timing correction.... . In particular, the present invention relates to the correct five automatic corrections for the timing of the ATE input and output pin drivers. The present invention is particularly applicable to a test device used to test semiconductor memory and logic circuits, so that logic circuits and memories may be applied to a part or a mold & tSet for precise and continuous testing. BACKGROUND OF THE INVENTION 'Test systems for testing semiconductor devices should be able to test every new generation of devices at the fastest speed of new devices. "The test device for digital circuits generates various waveforms at the desired timing and detects the voltage level of the waveform. It compares the data read from the device under test with expectations. The timing system is one of the most critical specifications of the tester. Typical systems today provide a resolution of 60 picoseconds, a maximum driver-to-drive skew of 500 picoseconds, and an edge position error of 700 picoseconds. The overall timing accuracy is within plus or minus 15 nanoseconds. For a new generation of high-speed devices, the accuracy should be within a few hundred picoseconds. To achieve this higher accuracy, it is important to calibrate the timing of the test device. The invention is particularly suitable for memory devices. Semiconductor memory will have a considerable number of input and output pins-such as 36 pins-and tested at a time of 16-4 mega-squares. Compatible with national standards (CNS); U specifications (210 X 297 mm) I- ·· --------- I--install ill — --- order--1 -'--- ”I — cable (Please read the precautions on the back before writing this page) Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 452906 A7, _________ B7 V. Description of the Invention (2) or 32 memory, so 36 x 32 tester pins are required. Therefore, many testers need to Basic structural units, each unit needs timing correction, because it is necessary to ensure that the time point of all voltage transitions' to the DUT pins and the time between the data output from the device under test and the expected data are relative to one another The benchmark is correct. However, these transitions often occur at different times. 'The reason is that signals that pass through a channel to a DUT must pass through cables, formatters, drives, and other devices with different electrical characteristics. As a result Time variation is called "skew" Generally speaking, calibration involves measuring the offsets in the input and output channels of each system and performing offset compensation with variable delays in each channel (for example, please refer to US No. 5,274,796g). Hardware, software, and hardware A combination of software can be used to control the delay compensation. Traditional methods include sequential correction of the timing of the tester's pins relative to a reference pin or an external reference (see, for example, US Patent No. 5,712,855). Because pin correction measurements require Sequentially, it takes a lot of time to use this method. The amount of measurement data required is also large; so the transmission and calculation time will be long and unfavorable. Another traditional method to alleviate the above problems is described in US No. 5,477,1 In the patent, the calibration is performed in a parallel manner. This method shortens the time required for timing measurement, but it increases the cost of the entire measuring device because it uses many local sequencers, each device under test (⑽τ) is connected to each branch. There is a sequencer on the pin. Another device for performing offset adjustment in parallel to all the terminals of the IC tester is described in EP 356,967 A2. This known method The disadvantage is that the offset adjustment system is 1 ..------------------------------------------------ line (please read the back side first) ; I will write this page again, I would like to write this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 sand 7 light) 45 2 90 6 A :. __B7 V. Description of the invention (3 Manual operation by an operator Implementation. Another widely used correction technique uses a time domain reflectometer (TDR) based on transmission line theory. According to transmission line theory, if a waveform passes through a transmission line and the transmission line is terminated by anything different from the line's characteristic impedance, then The waveform is reflected back through the line. If the line ends in an open circuit, the reflected wave is equal to the transmitted wave and the reflected wave is detected by the pin electronics. Using TDR technology, an automatic correction circuit is provided to measure the channel delay to the open contact point of the tester. However, the disadvantage of this method is that it requires many delay compensation circuits for each pin driver. This kind of test is performed relative to a common reference point. The method of automatic timing correction is described in "Maximising and maintaining AC test accuracy in the manufacturing environment" by RJ Bulaga and EF Westermann. Nashville, 199. Buden, IEEE 976-985. However, this known method is suitable for correcting non-periodic_ such as non-synchronous-test signal offsets and requires the use of many large pieces of hardware, which makes the system too dense and costly. It takes about 30 seconds to perform—a full calibration, which is too slow for traditional memory. An automatic offset correction circuit described in U.S. Patent No. 5,384,78 1 provides a multi-channel signal source correction technique that uses a device to change the delay based on an offset signal and determine the correction of the delay. The circuit includes a pair of crossover and flip-flops and a microprocessor. This method takes into account the time variation of different flip-flop changes. It provides a kind of fast k-positive method, which can be easily and frequently executed to correct the bias in the signal source.-This paper is applicable to national standards (CNS) A.] specifications (21〇X 297). ---------- Installation—— f Please read the precautions on the back before writing this page). -Line · Consumer cooperation with employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. A7. B7 printed by the Bureau ’s Consumer Cooperative. V. Description of Invention (4) Shift error. But this technology becomes extremely complicated as the number of signal sources increases; moreover, it is too costly in a semiconductor memory test setup with many signal sources. One of the main limitations of the known k-number offset correction method is that the accuracy of the measured signal offset decreases with the increasing speed and repetition rate of each new-generation high-speed synchronization device. In a modern environment, not only the input / output signal offset compensation is required, but also the accuracy of the measurement offset itself must be greatly improved, because the offset itself has many error sources and offset compensation delays. The need to improve the accuracy of offset correction has created a need for a fast automatic correction system, which needs to be able to provide extremely accurate automatic correction in a test system with many signal sources. SUMMARY OF THE INVENTION The object of the present invention is to provide an ATE system that can perform highly accurate semiconductor testing by maintaining accurate timing characteristics of registers and providing accurate calibrations related to multiple signal sources, while reducing test time and testing. Cost and simplify test head characterization. The advantage of the present invention is that an ATE system has the ability to use an error correction circuit incorporated in the tester's test head to reduce or substantially eliminate timing deviations between different signal sources, thereby improving test accuracy and providing a high-speed synchronous memory device. Acceptable and acceptable tests. According to the present invention, a register for flashing in and out of DUT data is placed in the test head or a card on the test head that contains a probing pin or slot to reduce the signal path to and from the trainer and thus avoid The timing signal is missing ... Partial house control can be achieved only by calibrating the register of the tester. Therefore, the overall system is greatly simplified. -7-] III · I — I ---- Order '" " ------ • ^ Please read the precautions on the back side first, and then hide this page) Standards apply to Chinese National Standard (CNS) Al ίΐίΓ (2Ϊ〇X 297) 452906 A7— B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (5) Because it is not necessary to use a programmable delayer for each pin And the monofilament to be corrected is also ❹, compared, m ㈣ for each pin drive ϋ correction. By using a dollar reference clock driver to correct the output register, the delay between the time when the register actually latches the input data and the edge of the reference clock can be measured with greatly improved accuracy. An important advantage of the system of the present invention is that it also allows fast corrections to various DUTs. This advantage is particularly important because various characteristics of a DUT itself can interfere with the operation of the register and affect the accuracy of the offset correction. The essence of the present invention is an automatic offset correction device for offset correction of a transceiver. For example, it is used to correct the offset of the signal transmitted to the dut and received from the DUT during the test procedure. High-accuracy test of the body device. The calibration is performed using a common time base that is available at different points on the calibration circuit. A reference signal is distributed from the reference clock source to the output register by this calibration circuit. The device of the invention can be incorporated into the tester's test head, or it can be implemented as a separate unit connected to the tester's test head. The number of input and output registers is defined by the number of registers in the DUT under test and can be one hundred or more. The register may be implemented as, for example, but not limited to, a flip-flop, a latch, or any other device suitable for latching signals. The traditional clock generator can be used as the main clock source. The reference clock circuit may include multiple phase shifting devices-such as a set of programmable delayers-to provide a means to delay the signal relative to the main clock. The main clock source can be implemented using, for example, SY89429A Phase Lock Loop PLL manufactured by Synergy Semiconductor Corp. (USA) or Analog Devices-8-This paper standard is applicable to China National Standard (CI \ 'S) A4 Specifications (2) 0 X 297 male S) — 1 ^ ------------ „------- line (Please read the precautions on the back before writing this page) 452906 A7 B7 Equipment 5. Description of the invention (6-pulse generator 'or similar products produced by Vitalec or Edge Semiconductors. An important feature of the present invention is that the DUT can be connected to the calibration device during the calibration operation, thereby allowing the electrical characteristics of the DUT to be It is considered. DUT characteristics such as the valley can be measured after the tester is calibrated. This feature is particularly important for the CMOS logic circuit, because the timing in the CMOS varies with the load capacitance. In addition, the traditional tester is different. As long as a new DUT is tested, the test head of the tester must be changed, and the present invention allows the same tester to be used to test different types of DUTs. In summary, the calibration device of the present invention can be used to calibrate different signals commonly referred to as transceivers. ^ Send and Receive The timing of the receiving and receiving system. A special case of the transceiver is an electronic circuit tester for measuring the conductor device. Therefore, in one phase, the present invention is an automatic offset correction device for correcting the transceiver. Device, especially when the semiconductor device is tested, the automatic offset correction device includes: a plurality of input registers for transmitting signals; a plurality of output registers for receiving signals; a main clock device For generating a main clock signal; a reference clock device for supplying a reference number for register calibration; the reference clock device is associated with the main clock device; and a plurality of first phase shift devices, Including at least one set of phase shifting devices each associated with the temporary storage benefits for relatively aligning the timings of the plurality of temporary storage devices. Xigu temporary storage The correction device includes a transmission having a predetermined waveform characteristic. Wheel line, used, -9- This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ------------- Installation · ------ -Order ---- ^ ------- line (please read the notes on the back before writing Page) The consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints multiple devices 452 90 6 A, B7 V. Description of the invention (The employee cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a reference signal from the reference clock device to the output register. The car is very good. The phase shift device of each group includes at least one phase shift device associated with each independent register to delay the timing of the register. To further improve its accuracy, it is advisable to use a multi-correction device. It further includes a set of second phase shifting devices associated with the plurality of registers, so that the timings of the registers among the many registers can be relatively aligned, "" Many input registers and the register Wait for many output registers to connect to the main clock device via this device. The -important special temporary storage of the present invention ^. An output register is operable to correct the plurality of inputs: =, the second set of phase shift devices includes at least one phase shift device associated with a plurality of registers in each temple. At this time, the flash register is connected in series to the reference input m register and other input registers through the transmission line. 'The many, all components are all part of the tester test head. Another modification of the present invention is that the phase includes: a method for automatic transceiver offset correction, a stepping disk for outputting a plurality of transceivers for temporary material correction; clock edge: = positive transceiver The delay steps of the register input register will measure the measured delay steps. 2.Wang wants to align the edges of the clock. Please read the notes on the back first.

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452906 Α7_ · Β7 ____ .. V. Description of the Invention (8) Preferably, the method further includes a step of correcting each programmable delay device before the step of correcting the output register. The method preferably further includes a step of improving the accuracy of the test system, wherein the transceiver is used by determining the minimum feasible time delay between the reference clock edge and the point in time of the latch data of the register. This correction can be performed on each scratchpad or on many scratchpads. Please also note that this measurement can be performed on each element of data transferred to or from the register. Another phase state of the present invention is a test system for testing a semiconductor device, which includes a timing device, an error logic circuit, and a central control unit, and a set of input registers and a set of outputs. Temporary storage These registers are corrected by the correction device and / or the delta positive method provided by the present invention. The test system may be calibrated in relation to a particular device being tested to take into account characteristics of the device that may affect the operation of the test system. Preferably, the test system '' is filled with a built-in calibration device according to the present invention. Specifically, the calibration device can be incorporated into the tester test head. " " Another aspect of the present invention is a method for testing a semiconductor device, which includes a step of transmitting a signal pattern to access a memory element in the device, and a step of receiving a response number to detect the number of memory elements in the memory element. The missing step, and a step of processing the test result, the method includes the steps of using the correction device provided by the present invention to perform automatic offset correction. Preferably, the offset correction g includes a step that determines the minimum feasible time delay between the edge of the reference clock and the time point of the register latch input data. , And another: there is still a phase state-a program for implementing, simulating, or emulating the hardware function of a private device, or using a computer to implement according to this -11-this paper Qindu thorn tguan-I ----- I I ----- '------- Order --I ^ ----- I 1 (Please read the precautions on the back before writing this page) Ministry of Economy Intellectual Property Printed by the Bureau ’s Consumer Cooperatives (210: 452906 B: V. Invention Description (9)), printed by the Consumers ’Cooperatives of the Ministry of Economic Affairs’ intellectual property bureau. Ling Ling has a better understanding of the invention and its implementation; Attached hearts: π loss and its general understanding, in the drawings: ㈣ million type circuit diagram without a specific embodiment according to the present invention; a fragment of the device = 2a shows the guide according to the previous technology-common section; 2b shows the transmission of the common time base according to the present invention = FIG. 2C shows the transmission of the common time base according to the present invention and the spring: the transmission line of the switch;-', there is a series of ^ according to the present invention The operation flow chart of the offset correction device. Fig. 4 (a) shows the step diagram of performing the register correction for # 应 在 suspend; Figure 4 (b) shows a traversable + ϊ1; the correction chart of the first step of the invention's correction and an example according to the party: Department-time history circle, used to illustrate according to the invention The offset correction diagram shows that according to the present invention will now be aided by -examples and = 10,000 block diagrams. Inventions. Examples are described without compromising their generality. The invention is sincere: 1 ... A specific example of the invention is a tester for a positive-moving device. It has a block diagram of a built-in partial phase fragment. Some display is -12-297 mm. (Please read the precautions on the back before writing this page)

'Installation -------- Order ---- I ----' II. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 452906 ------------ B7___ V. Invention Explanation (10) The remaining circuits in FIG. 5 include the conventional circuits used by different components such as the formatter's master clock, programmable delayer, and switch to generate test signals. The calibration device of the present invention can be adapted to provide calibration of the test data between the actual transmission and reception register and the DUT. Generally used registers include traditional flip-flops and latches. Shown in Figure 1 are a number of input registers 2_3 and a number of output registers, deducting 6, the input register is used to transfer data, address and control signals from the register to the device under test (DUT ) 1 test signal, the output register is used to receive the response signal from the DUT. The clock signal is transmitted from the main clock driver in sequence through the programmable delay device 丨 〇 and the logic conversion device 26 DUT 〇-the output of the input register 2, 3 is connected to the input of the DUT and the output register anus 6. The clocks of the input registers 2 and 3 are connected to the output of the secondary clock driver 36 via the logic conversion devices 29, 32 and the delay devices 13, 15 to maintain the data placement time of the input registers and DUT. To achieve this, the input of the secondary clock driver 36 is connected to the primary clock driver 9 via a programmable delayer 17. The clocks of the output registers 4, 5, and 6 are connected to the secondary clock driver via the logic conversion devices 27, 30, and 33 and the retarders 12 '14, and I6. The secondary clock driver 37 The input is connected to the main clock driver 9 via a programmable delayer 18 to align the false strobe clock to the dut clock. There is another set of registers 7-8 which is suitable for allowing the signals entering the input register to Affected by the length of the path from the substrate; "The input of register 7_8 is connected to the substrate, and its output is connected to the input of input register 2_3. Register 7 ^ -13- This paper & degree applies Chinese national standards ( CNS) Al specifications (210 χ? 97) -------------- installation -------- order · --- \ ------- line (please first Read the notes on the back and rewrite this page) 45290 6 ΑZ «· Β7 V. Description of the invention (11) The clock of 8 is connected to the main clock driver 9 through logic conversion devices 28 and 31. Please also note the register The number is not limited and may be, for example, one hundred or more. A main clock driver 9 is provided to generate a timing signal of the tester. Preferably, the main clock driver 9 may Clock signals are generated at different frequencies. To perform calibration of the tester, programmable delayers 12, 14, 6 are provided to compensate for the difference in channel number from the DUT, and delayers I and 15 are provided to compensate the DUT. The difference in path number k. Generally speaking, a phase shifting device group (such as a coherent delay device) may include, for example, one or more phase shifting devices to align the timing of each register in a plurality of registers. . That is, the number of delayers may be less than or greater than the number of registers in each of the plurality of registers. Preferably, at least one correction phase shifting device is used to delay each of the individual registers in the plurality of registers. The timing of the device is as shown in the figure! That is, the delays 13, 15 are used to correct the timing of the input registers 2, 3, and the delays] 2, 4, 4, 16 are used to correct the output, respectively. Temporarily stored ^, Bu ... Preface. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -------- I ------ (Please read the note on the back first # ί 食 食)-line. In this case, another set of phase-shifting devices' including the retarders 10, 17 and i 8 are retained to shift the ambiguity to the main The individual fan-out phase-shifting devices that are clock-moved to provide registers are also used to relatively align the timing of these many registers = registers. Preferably, from the second At least one of the group of delayers has been delayed in Yangzhijiuai Ai 4 # „,, " and various temples have been closed. As shown in =, a number of input registers and a number of output registers are expected to be connected by this second set of phase shifting devices, so that any suitable device can be used for phase shifting, as described above Biography -14- 'The paper size applies the Chinese National Standard (CNS) A4lii7 ^ · 297mm] 452906 B7 V. Description of the invention (12) A programmable delay device. Delayers can be implemented, for example, by Synergy Semiconductor Corp. (United States), or by

SY100E195 manufactured by Edge Semiconductor Devices. In order to maintain a timing offset within a predetermined accuracy range during the test and in the event of testing a new type of memory device, it is necessary to be able to periodically calibrate the test system to determine if it is caused by temperature changes, aging, or any other factor What happened. To perform the calibration operation, a reference clock driver 24 for supplying a reference clock signal of the register is incorporated into the circuit and connected to the register via reference clock switching switches 25a, 25b and 25c. During normal operation mode, the switch 25 is open and the reference clock is not connected to the data line. -One Please also note that according to the present invention, the common time base-that is, the main clock-is introduced into the correction circuit by a "spread common node". In a typical offset correction circuit such as described in U.S. Patent No. 4,827,437, a common node is introduced by multiple electrical environment lines arranged between the node and each test terminal. The length and internal impedance of each cable are completely The same (see Figure 2a). According to the present invention, a common transmission line with known waveform characteristics is used to generate a common time base, which can be obtained at different locations in the circuit, as shown in Figure 2b. In this way, the points connected to the transmission line can be obtained-a common time base ', which can be easily known from the calculation of the signal advance rate in the transmission line. As a result, there is no need to use the same length of cable to provide a common time base. The transmission line can be equipped with a series of changeover switches to switch the registers as needed, as shown in Figure 2c. For those skilled in the art, it is easy to produce different switch styles. -15- This paper size is applicable to China National Standard (CyS) A4 (2) 0 X 297 mm. I. Packing -------- Order --------- Line (Please read first (Notes on the back are written on this page again) 4) Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 452906 Α B. B7 Printed by the Employees’ Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (13 Refer to Figure 1 'Reference clock signal via -The common transmission line is diffused from the reference clock driver 24 to the registers 4, 5, 6. Each output register 4, 5, 6 is connected in series to the transmission line 'allows the use of the shortest transmission line and thus the signal along the transmission line Minimize changes. If necessary, as shown in Figure i, a number of pECL t〇_ TTL local logic conversion devices 26_33 such as SY100〇ELT23 manufactured by Semiconductor Co. The pEcl signal used in the clock circuit is converted into the TTL signal used in the DUT circuit. However, in special applications, these converters may not be needed and will be omitted. The operation of the offset correction device will now be described in more detail. Calibration procedure According to the four operations, the mulberry: (1) each correction is possible To determine its actual delay characteristics; (2) correct a number of output registers relative to the reference clock edge; (3) use the corrected output register to correct the transmission delay of the input register; (4) ) Provides alignment of the measured delay relative to the main clock edge. The first three of these four calibration jobs are performed using a special calibration technique according to the present invention. This technique includes the use of a system sequencer (not shown) to cover The entire delay range is used to change the probabilistic delay of the programmable delayer and each of the registers. The probability that it is determined to be two possible states, namely "0, 'or" 丨 ,, state_of ". The execution of the correction will correspond to the delay. From zero to the maximum 値, the result of i_determining 某一 in a certain bit of a register is calculated R times under certain conditions, and each decision is repeated until a statistically meaningful number is obtained R. The flow chart of this calibration operation is shown in Figure 3, where Σ⑴ claw is -16- This paper size is applicable to the national standard (CNS) A4 specification (21〇χ297297) -I .----- ------- install -------- order ---------- line (Please read the precautions on the back before you write this page) B7 B7 Member of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 Printed by a consumer cooperative V. Invention description (14) The average result of the above judgments. According to the information obtained, a graph can be drawn Shows the point where the probability is equal to 50%. The graph of this correction is shown in Figure 4 (a). Any appropriate language such as C, C ++, combined language, etc. can be used to easily generate a computer program based on Figure 3 The flowchart shown implements the above-mentioned calibration operation. L. Programmable device, the first operation of the main program can be omitted under certain conditions, and it is preferably performed before the register calibration. This operation includes preparatory calibration of the programmable delayer used to correct the register and ensures high-accuracy correction. The characteristic of the programmable delayer is that it is linearly dependent on the delay on the code sent to the delayer ( A typical graph of this dependence of retarders A and b is shown in Figure 4 (b)). As shown in the figure, the slope of this line graph varies from one retarder to another within the same batch. It is also known that the correction frequency affects the point in time when the transition from one of the two possible states to the other state occurs. Errors due to this effect are counted at this step. In order to properly define the delay ft, each of the private delays is corrected in the original position after being installed into the correction circuit and before the register is directly positioned. The delays are corrected by changing the correction frequency while keeping other variables constant. This fixes the time difference between the two switching points, which may determine the threshold of the variable delay. Also note that during this procedure, a positive k-graph with χ, y coordinates is obtained, where τχ ′ is the clock period and y is the estimated delay unit (^ is the delayer count). In order to define the linear dependence of _unit (Td) along the ^ coordinates, the time unit of this estimated unit is determined by the standard linear regression method. 17 · This paper is a standard for financial rewards (CNS) Ad specifications (2 ] Q x 29? Public love) 1-. I ------------: ---- (Please read the precautions on the back to write this page) 452906 V. Description of the invention (π) X $ · τ 4 is assigned to each variable delay—a conversion function Ftr showing the dependence of the delay 値 on the encoding of the k-side variable delay. 1IA_ by register 4r The second job is to correct each or to the output register relative to the reference clock edge (although in this case, Figure t shows the register bucket, $ and 6 'Please note the actual The number of upper registers may be one hundred or more. During the calibration operation, one of the switch 25 is turned on according to the bit of the register to be calibrated. For example, to calibrate the register Register 6, the middle switch 25b is to be turned on and the input register is set to three states, and the corresponding programmable delay ^ 6 is changed to cover the entire delay range as in the above-mentioned calibration procedure. In this case, The program is executed on different bits of the scratchpad with the same frequency. 'If it is a new generation of high-precision scratchpads, or if a scratchpad specially made for this purpose is configured, or a pre-calibrated one is used This register can be omitted. The traditional register can also be used without adjustment ', but there will be a certain degree of reduction in the overall system accuracy. Figure 5 shows the time of this calibration operation Figure. As shown in Figure 5, can It is observed that there is some time difference between the time when the register actually latches the input data and the edge of the reference clock. At the end of the calibration procedure, the corresponding delay—that is, a bit in the register—Td- It is introduced into the input channel and the output channel to compensate for these time differences. T d is defined by the following formula ...

Td = Ding U + Tr,-where Td is the actual delay of the signal delay; the exact time of the data latch in the register; -18- in use _ home standard (CNS) A4 specifications (2) QX 297 public love ----- ^ --------- install --- {Please read the precautions on the back before copying this page) Order · --line · Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 4 5 290 6

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (16, I is the time required for the reference clock signal to reach a certain bit of a certain register via a transmission line. This time can be printed by a printed circuit board (pcB ) Is calculated and / or measured by an oscilloscope and checked and corrected. However, the uncertainty of determining the delay length is zero limits the accuracy of the calibration operation, so this uncertainty should be minimized. It means that the data in the temporary register flashes. The parameter T | a of the lock and cut time is defined by the average value of the actual register setting and maintenance time under a certain power supply and temperature conditions. However, this parameter may be different from the parameters shown in the data sheet because the parameters in the data sheet Generally refers to the worst situation under various temperature and power conditions. Judging the actual time of temporarily locking the input data and the actual delay between the time point and the reference clock edge. The edge can improve the accuracy of the test system operation. One break can be performed on the falling edge of the reference clock, or on the rising edge of the reference clock, or • twice, once on the falling edge, and then on the rising edge The edge is executed once to ensure the accuracy. Judging the correctness of Td (delay time) and D ^ and '(refer to the time of the clock edge) is a function of two ：: the pulse pulsation of the register and the incorrect latch time. In itself. Because of the difficulty in achieving the correct calculation of the tremor and latch time Fan Yuan, the sum of these two values is determined experimentally. It has been found that the rising and falling edges of the data at the input of a typical TTL register can be 25%. Td is judged by picosecond accuracy. For some CMO gallium arsenide and ECL registers, higher accuracy can be obtained. The correction accuracy of the output register can now be determined based on experimental data. This accuracy is subject to temporary The uncertain limit of the actual time of register latch data is calculated by the following formula: △ Tsk (out) -out 丁 叫.) + 厶 丁 ⑽. , -19- This paper is in accordance with the national standard (CNS) A4 specification (210 X 297 public love) 'ip I ί III i 1 1 κ I m I PI 1 RI 1 · Order --- il! Line (please First read the notes on the back? Write this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 452906 B7 V. Description of the invention (17) Where △ Tsk (.;) is the output offset of the reference clock driver. The typical clock driver syiooe 111 manufactured by Synergy Semiconductor Corp. of the United States and T, the offset is approximately equal to 0.3 nanoseconds. This offset can be reduced 'during the manufacturing process' but for the purposes of this description, it can be assumed that a standard device without trimming is used. Alternatively, a single line with predetermined signal advance parameters can also be used. In this case, ΔΤα (〇) can be determined by the layout of the printed circuit board and its value will be less than 0.3 microseconds; △ Tune 疋 judges the time difference between the time when the register actually latches the input data and the edge of the reference clock Uncertainties, and in this case judged as positive and negative 0-25 nanoseconds. This can also be measured as described above. Although this accuracy can be assumed to be sufficient for a specific example of the present invention, in general, the correction device proposed by the present invention provides a scalable system that can be adjusted to use a time with higher inherent accuracy. Memory to improve accuracy to the desired level. As for the main clock driver flutter, that is negligible, because the main clock driver is usually implemented in a positive emitter coupled logic circuit (pECL). Commercially available hybrid oscillators can achieve 3 picosecond rms jitter. Please also note that the output offset of the main clock driver is in any case compensated by the averaging of the data during the calibration operation of the invention. So, in general, △ TSk (〇ut) = 0.30 + 0.25 = 0.55 nanoseconds. Therefore, the output register is set to at least 0 55 nanoseconds-preferably less than 0.55 nanoseconds- Correction. III. Calibration of the input register; the third offset correction operation is a temporary storage of many input registers 2, 3 _ -20- scale Gu t⑽) A4 ^ T1T0X297 ^ 57 ---- „- --r ---- install ------ order ------ line (谙 read the precautions on the back first and then reduce this page) 452906 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 V. Invention Explanation (18) Calibration of the transmission delay of the device. To perform the third calibration operation, all the switches 25 are opened to disconnect the reference clock driver 24 from the calibration device. Then 'input buffers 2, 3 are timed The generator has a strong edge to produce a low-to-high or high-to-low transition at its output. Measurements can be performed on individual bits of each piece of data transmitted from the output register, by changing the corresponding delays 13 or 15 to find and input The best match of the latch time of register 2 · 3. A similar procedure is executed to find the best match of the data transmitted from output register 4 and the lock time of clock driver 26. The result can be obtained by Td⑴ Chuanguang delayed the clock of the entire register, but for each output of the data from the input register The unit can monitor individual bits and obtain individual transmission delays. The accuracy of this measurement is limited by the delay accuracy that has been determined in the previous steps and can be calculated using the following formula: ATsk (in)-ΔΤ3, (〇ϋΐ) + ATunc , Where △ Ding 4 (. Is called the correction accuracy of the output register and calculated as above is about 0.55 nanoseconds: △ Tunc is the time between the point at which the register actually latches the input data and the edge of the reference clock Uncertain factors of time difference, in this case, 値 is plus or minus 0.25 nanoseconds. △ Tsk (in) = 0.55 + 0.25 = 0.80 nanoseconds so the 'input register can be at least 〇0〇. Femto-seconds-preferably less than 0.80 nanoseconds. Correction. Ly _ Measured lack of delay, Bai Duansu's last calibration operation is to align the measured delay with respect to the main clock . After the right procedure is completed, the DUT clock is selected as the reference clock to replace -21-This paper size applies to Chinese national standard specifications (210 X 297 mm S) i. Installation -------- Order- --1 -----— Line (Jing first read the precautions on the back and then write this page) B7 45290 Description of the invention (19) Table weights the positive result. The corresponding delay compensation 値 Tcomp is input into the programmable delayer by the central control device. This can compensate the main part of the offset. However, there are still some remaining internal register offsets. , That is, the offset between the pins of the same register (the number of pins can be, for example, from 4 to 18), this offset cannot be compensated during the calibration process. In order for the user to estimate this offset and For convenience, 'this offset is measured in order to report it to the user along with the calculated compensation'. The offset of each signal is calculated relative to the DUT clock which is assumed to be zero thereafter. The following procedure is executed to determine the delay compensation, where k is the number of bits in some registers, and all the bits in this register are sequentially numbered from i to two registers. The first bit to the last bit of the last register; 'η is the number of input registers-the number of input registers, the total number of input registers is N; m is the number of an output register in a certain number of output registers. The total number of output registers is N + 1. The total number of output registers is greater than the total number of input registers. The pulse driver 24 and the output of the clock driver 24 are connected to the inputs of the output registers. Step I: The following information is input to determine the compensation of the retarder: • A correction pattern in digital form, which is performed from each of the first output register and each k-bit of the output register. ηobtained ,, • Individual reference delays measured for each k-th bit of the output register Tr,:, -22- J- binding --- fJ ---- line (Please read the note on the back first Matters are written on this page) Printed on the paper by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _ Family Group (CNS) A4 ^ ~ ^ · 297 mm> Printed by the Employee Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 452906 --- ---- B7__ .. 5. Description of the invention (2) Step 2: • Determine Tdk for each bit k, Tdk = dkXFtr, l is the conversion function determined in operation j, and temporarily output the first claw output. The nth bit of each register in the register is defined as the 50% level; • For each kth bit of the output register, T 丨 ak = Tdk_Trk is determined; Step 3: • Define the mth output register The average of all bits in the register 値 ΐ < Tla > m iTht / d-kJ, where is the second bit number of the output register m: • Judging min < Tla > m: • Compensation for the delay count

Tc〇mpm (〇ut) = < Tla > m-min < Tla >; step service "-to determine the advancement time of each input register): • For each nth input register obtained in operation m Tdk (in) of the decision; • For each η input register, obtain Tlak (out) of each ⑺ output register determined in step 2, and the input of the plus output register is connected to the nth Input the output of the register; • 4 Calculate TC〇k (in) = Tdk (in)-Tlak (0lu); $ towel Tc〇 is "clock to output", which is the advancement time; I shape clothes --- ----- tr—-I --- Ί '^. (Guess to read the precautions on the back before writing this page) Use the following I * formula to calculate all bits in the mth output register. c〇k average

452906 B7 V. Description of the invention (21 < Tco > = Σ Tc〇k / (k η + 1 ^ kn); k flavor, • Judging min < Tco >n; • Calculate a set of compensation for each input register Delay Tcompn (in) = < Tcon >-min < Tcon >; Step 5: Late for • Get when the reference clock is cut off and the device under test (DUT) clock is connected to the output register. Td (DUTclk) k determined in the clock driver operation Iπ; • Get Tla (DUTclk) k whose input is connected to the output register of the DUT clock driver: • Calculate Tc〇 (DUTclk) = Tdk (DUTClk )-Tla JDUTclk); where Tco is "clock to output", that is, the advance time; • Calculate the average Tco (DUTclk) of each k-th bit of the clock driver according to the following formula:

k〇ur + L < Tco (DUTclk) > = Σ, kr

, DUT--------------- install -------- 1τ ---- ^ ---! Line (please read the note on the back first and then ^^ (This page) The employee of the Intellectual Property Bureau of the Ministry of Economic Affairs, the vice president of the cooperative, took the first bit number of the output register to which kDUT is the DUT clock; L is the number of the DUT clock; DUTclk) = Tco (DUTclk) — ηιη < Τυυ > η Calculates the compensation delay for each DUT clock driver. Any suitable language, such as C, C ++, combinatorial languages, etc. can be used to easily generate a computer program to implement the sequence of steps described above. -24-This paper size applies the Chinese national standard (CNS > A4 size (210x 297 mm) Λ -'- B7 452906 V. Description of invention (22) The following errors will cause incorrect register calibration. Different temporary The threshold level of the register may be different, causing the uncertainty of its electrical parameters. Using the correction method described above may prevent or at least mitigate this problem. Generally, the register has a threshold voltage of about 1.5-1.6V, And the threshold of SDRAM is about 1.4 V. This will also cause "0," and "1," the judgment of the state transition error. In this case, it is possible to calculate the actual latch data of the register The difference in time between the time point and the edge of the reference clock is incorrect. The difference can be expressed by the following formula: △ ttrh = △ U / r, where one— △ ttrh is the actual latch of the register caused by the threshold voltage difference The extra time difference between the point in time of the data and the edge of the reference clock; ATI = Τ Τ ττ. Actual ^ standard where Γ is the conversion rate of a signal. For the register threshold voltage of about 1.5-1.6 V and SDRAM threshold voltage of about '4V and Let's say △ UH.SV-ljVHV; the slew rate r of the signal is about 2V / ns; so it is uncertain △ ttrh is about 0.05 nanoseconds. If U is actually 1.6V, then the uncertainty will be greater-ie It is about 〇lns_ & and constitutes a considerable part of the correctness of correction. This is a tether error that can be corrected by the following formula: 'TC〇mP, < TC〇n > -min < Tc〇n >-~. In this step Another possible error that must be considered when calibrating the register is the source of the bushold circuit of the register. The previous state of the register will be left. -25- This paper applies the Chinese national standard (CN, S) A4. Specifications (210 X 297 public love) I .--- Γ I ----------- ---- Order-I ------- Green.-% (Please read the (Notes on this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 452906 B7 V. Description of the invention (23) Recall that due to the existence of this residual memory, the threshold for high-to-low transition and low-to-high transition will not change. Same. This phenomenon results in the graph; the hysteresis loop in 3a. By measuring the loop t degree Δ thys, it is possible to estimate the minimum threshold uncertainty of the register according to the following formula:

△ T AT, printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Inc.eff. — ° 1 unc, soil △ [hys,] ° Figure 6 shows an exemplary specific example of the memory test system according to the present invention. The system shown in the figure is used to test semiconductor memory 1 (DUT) such as SdraM DIMM module. The system includes a timing device for generating a delay time of No.5, at least one of a plurality of drivers3, a temporary register, a group of phase-shifting devices cooperating with the drivers4, and a plurality of receivers5 At least one of the receivers 5 is a register, a group of phase-shifting devices 7, an error logic device 6, and a central control unit 8 connected to a computer interface 9. The time device 2 provides an appropriate sequence of addresses, data, and control signals to access the memory element of the first step of the test according to the test proposed by the present invention. Some data are fed to the input register 3, and the function of the child input register is included in the memory test system according to the example of the present invention to maintain the address and control letter 2 including writing data. The predetermined standard level of the logic signal is a set of pin drivers (not shown) that can be used to adjust the logic level to determine the bits required for a particular dut :. : Group phase shift device 4 (such as programmable delay device) is used to calibrate == input timing to match multiple test signal patterns. Get from P ... Zhuang (output register) and receive with "〇, and" in error logic device 6! ，， 浐 定 浐 ，. 佳 ^ Xing (t, 准 only quasi-comparison to test -26 I .------------install *-I ---- order ---- ----- (Please read the precautions on the back before V write this page) Mizuna Scale Hajj 297g g) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 452906 ΑZ ------- Β7 V. Description of the invention (24) The subsequent steps of the method detect a loss in a memory element. The ratio comparison state (not shown) can also be used at a predetermined level before the output register. The digital form data of the self-output register 5 is input into the error logic device 6, and the error logic device compares the actual data with the expected data from the time device 2. Another group of phase shifting devices 7 (such as a delayable delay device) is used to receive the data before / delaying the receiver group 5 (such as an output register) to compensate for the delay in the loop. The error data from the faulty Wu logic device 6 is sent to the central control unit 8 in parallel—step up j = computer interface 9 of the control computer (not shown) in order to process the test results according to the second step of the test method. The "empty" computer should keep accumulated data in coded format. Wrong information too. Bit image format performance to look at the wrong ® The system shown in Figure 6 does not use pin electronic circuits to do υυτ to locate the address as traditionally, but uses two sets of registers, which are used for group registers 'Enter data' Another set of registers is used to receive test data from the DUT. To achieve the rigorous accuracy required to test high-speed semiconductor devices, traditional methods include correcting the timing of each pin structure. The present invention avoids the use of a time-consuming pin-based correction, and instead uses a correction device to correct the register, thereby achieving a fast register-based correction mode. According to the current month, the calibration operation can be performed when the DUT is not connected to the system, or it can be better connected to the DUT; then the test system is performed at the same time. Because the electrical crying characteristics of Ding itself will greatly affect the operation of the register, it is very important to make the actual DUT of the material test to calibrate the test system, instead of simulating the characteristics like traditional -27. This paper scale is applicable to China National Standard (CNS) A4 Specification ⑵ ^ χ Norwegian I. Equipment -------- Order --------- Line (Please read the precautions on the back before writing this page) 452906 AL ., B7 V. Description of the invention (25) In addition, after the calibration operation is performed relative to the test system, the Dut register can also be calibrated. ^ In this case, the order in which the DUT register is calibrated is not critical. The present invention can also perform analysis of DUT characteristics, or any other integrated circuit device test. For example, different DUT characteristics such as electrical characteristics can be detected in the test procedure provided by the present invention. Therefore, in order to determine the DUT pin capacitance, the calibration system first calibrates according to the above method. Then, a series of capacitors' having a predetermined capacitance 値 are tested using the same calibration system and measurement system parameters. 2. The obtained results are plotted in the form of a calibration curve to determine the dependence of the system number and the device capacitance, f (C „e). The next step is to use the DUT under test instead of the valley tester to measure the same. System parameters. The required pin capacitance can be easily calculated from the calibration curve. One of the alternatives is to use a register in the memory test system or any other receiver connected to the transmitter. Please note the above. The description and drawings are only an exemplary specific example, and many modifications are made to the specific examples described above within the scope of the present invention. — — — — — — — — — — — 11 !! (11 11111! 11.. 1 (please read the back of the page first; I will write this page first) The Ministry of Economic Affairs Intellectual Property Bureau Staff Consumption Cooperative Printed Clothes-28 This paper scales China (CNS) A4 size ⑵Gx 297 male ^ >

Claims (1)

ABCD 45290 6 Patent application No. 8δ110660 Turkish application Bilishuwei JJ Zhengtaidai 0 car 4 6. Patent application scope 1. A correction device for automatic offset correction of a transceiver, including a number of input temporary Registers; many output registers for receiving signals; a main clock device for generating a main clock signal; a reference clock device for generating a reference signal for a correction register; the reference time The pulse device is associated with the main clock device; and a first plurality of phase shift devices, including at least one group of phase shift devices associated with each of the plurality of registers, for The relative alignment of the timing of the registers in each register. 2_ The correction device according to item 1 of the scope of patent application, further comprising a transmission line having a predetermined waveform characteristic to supply the reference signal. 3. The correction device according to item 2 of the patent application range, wherein the output registers are connected to the reference clock device through the transmission line. 4 · The correction device according to item 1 of the patent application, wherein the plurality of output registers are operable to correct the plurality of input registers. 5. The correction device according to the scope of the patent application, wherein the first plurality of phase shift devices include at least one mobile device associated with each individual register to delay its timing. 6. If the correction device of the first scope of the patent application, further includes a second group of phase shifting devices, the second group of phase shifting devices is associated with the plurality of registers and is used for the plurality of registers. The timings of the registers are relatively aligned. The plurality of registers are connected to the main clock device via the second set of phase shift devices. 7. If the correction device for item 6 of the scope of patent application, the second set of phase-shifted paper is used in Chinese standard (CNS U4 standard (210 X 297 mm)) (Please read the precautions on the back before Fill out this page} Order 1 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives 452908 Α8 BS C8 D8 Six applications for patents Scope of the Ministry of Economic Affairs Central #Associate Bureau of the Consumers Cooperatives of Printing «. The device includes at least-Associated #each many Mobile device of the register. 8. If the correction device of the patent application am item, including the many, enter the register 'the many output registers, the reference clock device, etc. at least one μ or All components are part of the tester's M head. 9. A method for automatic offset correction of a transceiver, including: Relative to a reference clock edge correction transceiver's many output registers; using a corrected output register Register corrects the transmission delay of the input register of the transceiver; aligns the measured delay with respect to the main clock edge __ 10. If the method of item 9 of the patent application scope further includes- Steps of correcting each programmable delay # before the step of register calibration. Α The method of item 9 in the patent scope is adopted, in which the correctness of the calibration is determined by judging the reference clock edges and V registers with V registers. The minimum feasible time delay between the time point at which the register locks the data is improved. 12 • The method of the patent scope item No.! 丨 where the judgment is performed twice, once for the falling edge and then for the rising edge. Another. 13. The method of item 9 in the scope of patent application, wherein the transmission delay of the input register is corrected by changing the delay to best match the output transition with the output register lock time. 14 . For the method of applying for the scope of the patent, the transmission delay correction is performed on each independent bit of the output register data. 15. For the method of the scope of the applying for the patent, please read Λ first. Note for further reordering 1 -2- Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs Λ8 Β8 C8 D8 夂, the steps of applying for patent scope are partly or completely implemented by computer. 16.-A memory test system for testing semiconductor devices, including a timing device; an error logic device;-a central control unit; and a tester test head including a plurality of drivers' including at least-for Input registers for transmitting signals; many receivers' include at least one output register for receiving signals; and a reference clock device; wherein the reference clock device is operable to use the set of associations with the A plurality of receivers 'phase shifting devices to correct the receivers to phase-align the receivers' timing; and the plurality of receivers are operable to use a set of phase shifting devices associated with the plurality of drivers to Calibrate the drivers to relatively align the timing of the drivers. 17- The memory test system according to item 16 of the application, wherein each of the output registers is connected to the reference clock device through a transmission line having a predetermined waveform characteristic. 18. A computer capable of capturing memory, which can be operated in a memory testing system for testing semiconductor devices. The memory includes a computer for performing offset correction of the test system. The calibration includes: aligning the output registers of the transceiver with respect to a reference clock edge. -3- This paper standard uses the Chinese National Standard (CNS) A4 specification (210 > < 297 mm) (please (Please read the notes on the back before filling in this page)-Order 452906 A8 B8 C8 D8 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs Printed by Shelley Consumer Cooperatives 6. Apply for patent park correction; use the corrected output register to correct the transceiver Input the transmission delay of the register; D align the measured delay with respect to the main clock edge. 19. A method for testing a semiconductor device, including the following steps: transmitting a signal pattern to access a memory element in the device, receiving a response signal to detect a defect in the memory element, and processing a test result, wherein the method further includes : Use the correction device as described in the scope of patent application for offset correction. 20. The test method of item i 9 of the scope of patent application, wherein the calibration of the test system is performed using the method of item 9 of patent application park. 21_ The test method according to item 19 of the patent application scope, wherein the calibration is performed when the test system is connected to a device under test. 22. The test method according to item 19 of the scope of patent application, wherein the method further includes judging the electrical characteristics of the device under test using a calibration device such as item 丨 of the scope of patent application. .23 'Electrical program' when the computer program is stored in an electrically readable medium 'is used to implement or simulate or imitate the hardware function of a calibration device such as the one in the scope of patent application' where the calibration device is Including many input registers for transmitting signals; many output registers for receiving signals; a main clock device for generating a main clock signal; a reference for generating a correction register The reference clock device of the signal; the reference clock device is associated with the main clock device; and -4- this paper_Zhang Youdu applies the Chinese Gujiazheng standard (〇 八) 8 4 rules / grid (2 丨 0 乂297 public funds) '(Please read the notes on the back before filling out this page) Order ABICD 4 5 2 9 0 6 VI. Patent application scope The first plurality of phase shift devices, including at least one group related to these many temporary The phase shift device of each register of the register is used to perform relative alignment of the timing of the register in each of the plurality of registers. (Please read the precautions on the back before filling out this page.) Order Staff Printing Cooperative Cooperative Plow of the Ministry of Economic Affairs, Central Standard Bureau This paper applies the Chinese National Standard (CNS) A4 standard (2I0X297 mm)