TW451480B - Fabrication method of split-gate flash memory - Google Patents

Abstract

The present invention provides a fabrication method of split-gate flash memory with self-alignment and high coupling ratio on a semiconductor substrate. The semiconductor substrate comprises a substrate, at least two selection gates are disposed on the substrate, and a dielectric layer is disposed on each selection gate. The method is to form a polysilicon spacer each on the inner wall between these two selection gates as the floating gate, then form a drain each on the substrate neighboring the outer side wall of these two selection gates, then form a source on the substrate between these two polysilicon spacers. Then form a silica layer on the surface of the semiconductor chip, and remove the silica layer with a predetermined thickness by dry etching, and remove the dielectric layer located on each selection gate till a predetermined thickness. Finally, form an ONO dielectric layer on the surface of the floating gate, and form a control gate between these two selection gates and on top of the floating gate.

Description

A514B〇 5. Description of the invention (i) Field of invention ^ The present invention provides a method for manufacturing a split gate flash memory cell, especially a method having self alignment and self-alignment. Manufacturing method of flash memory unit with high value (high C0Upiing rati〇). Background Description Electrically erasable programmable read only memory (EEPROM) has the advantages of being writable, electrically erasable plus written data that can be stored for more than ten years. It has become one of the most commonly used and rapidly developing memory products. However, it has the disadvantage of slower access speed. In order to solve this shortcoming, a product called flash memory was developed by Intel Corporation. The structure of flash memory is the same as that of EEPROM, but the data erasing action of flash memory It is performed in a block by block manner, instead of the traditional EE PROM in a bit by byte manner, so it can significantly save the time of data erasure. In addition, depending on the structure of the gate, flash memory can be roughly divided into two types: stacked gate (stacked gat e) flash memory and split gate (sp 1 i t gat e) flash memory. The stacked gate flash memory cell includes a floating gate for storing charge, and a 0N0 (〇xi de-nitride-oxide) structure.

Page 4 4-51 ^^ 0-~~~ ___________---- 5. Description of the invention (2) Dielectric layer, and (and a control gate for controlling data access. Memory The principle of similar capacitance can be used to store the induced charge in the stacked gate, so that the memory can store the signal "1" If you need to replace the data in the memory, you only need to supply a little extra energy to restart it. The work of data storage. Please refer to the figure. The figure is a schematic diagram of the cross-sectional structure of the conventional heap flash flash early morning 疋. As shown in Figure 1, the conventional stacked gate flash memory unit 10 includes a Stacked gate 11, one gate 22, and source 24. Stacked gate 11 is composed of a gated layer 1, 2, a floating gate 14, an insulating layer 16, and a control gate 18 from below. The top surface of the silicon substrate 20 stacked between the drain 22 and the source 24. The hot electrons generated near the drain 2 2 can be injected into the floating gate 1 through the gate oxide layer 12 by using the channel thermal electron effect. 4, and raise the threshold voltage (threshold voltage) of the floating gate 14 to achieve the purpose of storing data. Stack Although the gate flash memory unit 10 occupies less area, it has the disadvantage of over erase. Excessive erasure can easily cause data to be written incorrectly or cannot be written. This disadvantage can be avoided. Please refer to FIG. 2 'FIG. 2 is a schematic cross-sectional structure diagram of a conventional separation gate flash memory unit 30. As shown in FIG. 2' the conventional separation gate flash memory unit 30 includes a gate The oxide layer 32, a floating gate 34, a control gate 38, a gate 42 and a source 44. The control gate 38 extends toward the source 44 and is provided at the floating gate 3 4 and the source 4 4 On the base of Shi Xi, formed—

Page 5 45 1 48 〇 _________ '---------—________ _____- —___ V. Description of the invention (3) Select channel 31. An additional insulating layer 36 is formed between the control gate 38 and the floating gate 34. Although the split gate flash memory can solve the problem of excessive erasure of the stacked gate flash memory, the conventional coupling gate flash memory (CR) is low, resulting in erasure. The speed cannot be further improved, and there are disadvantages such as incomplete erasure or unstable performance. In addition, 'the overlapping area of the control gate 38 and the floating gate 3 4 will be affected by the misalignment of the exposure alignment machine', and an unstable channel current will be generated when reading the data 0 :: β Please refer to Figure 3, Figure 3 shows a schematic diagram of the equivalent circuit 46 of the conventional split-gate flash memory unit 30 in FIG. 2. As shown in Figure 3, the capacitance between the floating gate 34 and the control gate 38 is C1, and the capacitance between the floating gate 34 and the source 44 is C2 'between the floating gate 34 and the surface channel of the silicon substrate 40. The capacitance is C3 'and the capacitance between the floating gate 34 and the drain 42 is C4. Therefore, the coupling value (CR value) of the split gate flash memory unit 30 can be defined as: CR = C1 / (C1 + C2 + C3 + C4)

The CR value is an index for determining the performance of the split-gate flash memory unit 30. A higher value {^ indicates that the lower the operating voltage required by the flash memory for writing or erasing operation, the better the performance. According to the above relationship, the method of increasing CR ^ can increase C1 or decrease C2, C3, and C4. Since the size of the capacitor is directly proportional to the area of the capacitor, increasing the capacitance area of the floating gate 3 and carefully controlling the gate area of the gate 38 can increase C1. On the other hand, 'reducing the capacitance area of the floating gate electrode 34 and the surface channel of the substrate 40 can also effectively reduce C3 "'

4514B〇 5. Description of the invention (4) Please refer to FIG. 4 to FIG. 7. FIG. 4 to FIG. 7 are schematic circles of a method for making a separate gate flash memory unit 8 0 on a semiconductor wafer 50. As shown in FIG. 4, the semiconductor wafer 50 includes a silicon substrate 52, and a silicon oxide layer 54 is formed on the surface of the silicon substrate 52. As shown in FIG. 5, a conventional method is to form a photoresist layer 56 which is defined by η thography before the surface of the dream oxygen layer 54 and used as a hard leather curtain for the subsequent ion implantation process. (hard mask). Next, the ion implantation process is performed, and a hard mask formed by a photoresist layer is used to form a doped region (not shown) on the surface of the silicon substrate 5 2. A rapid thermal processing (RTP) is then used to cause the dopants in the doped region to descend into the silicon substrate 52 to form a second diffusion region 6 2 ′ for the drain and source of the memory cell 80. The silicon substrate between the diffusion regions 62 is a channel 60 ° for separating the gate electrodes, and then the photoresist layer 56 is completely removed as shown in FIG. 6. Subsequently, a low pressure chemical vapor deposition (LPCVD) process is performed to form a polycrystalline silicon layer (not shown) on the surface of the silicon oxide layer 54. Then, a photoresist layer 66 'defined by a yellow light process is formed on the surface of the polycrystalline silicon layer, and an anisotropic truncation process is performed using the photoresist layer 66 as a hard mask. The polycrystalline dream layer is removed vertically down to the dream oxygen. The surface of the layer 54 forms a floating gate 64 which separates the gates. Finally, as shown in FIG. 7, the photoresist layer 66 is completely removed. Then, a low pressure chemical vapor deposition process is used to uniformly deposit the semiconductor wafer 50 surface.

Page 7 45 1 48 Ο ___----- ~ --- 5. Description of the invention (5)…, ,, A stone oxide layer 68 is used as a tunnel oxide layer (tunnel oxide Uyer). Next, another low-pressure chemical vapor deposition process is performed to form a polycrystalline stone layer (not shown) on the surface of the silicon oxide layer 68, and then a photoresist layer (not explicitly supported) is formed on the surface of the polycrystalline silicon layer, and is used. The photoresist layer is a hard mask—anisotropic etching process. The polycrystalline wheat layer is removed vertically down to the surface of the dream oxygen layer 68 to form a control gate 7 0 β for the separation gate. SUMMARY OF THE INVENTION The main purpose is to provide a method for manufacturing a split gate flash memory unit with self-alignment characteristics, so as to increase the CR value of the memory unit, thereby improving the performance of the memory unit. The invention provides a method for fabricating a split gate flash memory unit on a semiconductor wafer. The semiconductor wafer includes a substrate, at least two selection gates are disposed on the substrate, and a dielectric layer is disposed on each selection gate. In the method of the present invention, two polycrystalline silicon sidewalls are formed on the inner side wall between the two selection gates to serve as the floating gate of the split gate flash memory unit, and then adjacent to the outside of the two selection gates. A drain is formed in each of the substrates of the wall, and a source is formed in the substrate between the two polycrystalline silicon sidewalls. Then a silicon oxide layer is formed on the surface of the semiconductor wafer 'covering the surface of the dielectric layer, the two selection gates and the two polycrystalline silicon sidewalls', and a dry etching is used to remove the silicon oxide of a predetermined thickness. Layer and removing the dielectric layer above each selected gate to a predetermined thickness. Finally, a 0N0 (oxidized-silicon 4 5 1 48 05) dielectric layer is formed on the surface of the floating gate, and between the two selected gates and above the western gate. Forming a control gate 'to complete a separate gate flash memory unit with a high CR value' Because the method of the present invention forms a polycrystalline sidewall on each of the side walls between the two selected gates to serve as the Floating gate of split gate flash memory unit. Since the floating gate is formed by an anisotropic dry etching, an exposure alignment machine is not required, so the purpose of self-alignment can be achieved. In addition, as the contact area between the control gate and the floating gate is increased, the separation gate flash memory unit ’s zero-point invention is also described in detail with reference to FIGS. 8 to 17 and FIGS. 8 to FIG. 17 is a schematic diagram of a method for fabricating a separate gate flash memory cell 150 on a semiconductor wafer 100 according to the present invention. As shown in FIG. 8, the semiconductor wafer 100 includes a stone substrate 〇〇2, a gate oxide layer 104 is formed on the surface of the hair substrate 102, and a polycrystalline dream layer 106 is provided on the gate oxide layer 104 On the surface of the polycrystalline silicon oxide layer, a dielectric layer 108 composed of SiO2 is disposed on the surface of the polycrystalline layer 106. The thickness of the dielectric layer iq § is about 4,000 to 50,000 angstroms. As shown in FIG. 9, the present invention is performed before the surface of the semiconductor wafer 100-a lithography process and an anisotropic dry etching process, and the dielectric layer 108 and the polycrystalline dream are etched downward. The layer 106 reaches the surface of the gate oxide layer 104 to form a selective gate 11 2, 11 4, 11 6 and 118. Use it later.

ab d 5. Description of the invention (7) A silicon dioxide layer 122 having a thickness of about 150 to 200 A. The thermal oxidation process forms oxygen on the exposed surfaces of the selected gate electrodes 11 2, 11 4, 11, 6, and 11 8 and adds 丄, e ----------- Then, as shown in Figure 10, a A chemical vapor deposition (CVD) process to form a polycrystalline silicon layer 124 on the surface of a semiconductor wafer with a thickness of about 2500 to 4000 angstroms, uniformly covering the silicon substrate 102, the dielectric layer 108, and the selection gate 112. , 114, 116, 118 surface. Subsequently, an etching process is performed to remove the polycrystalline silicon layer 124 up to the surface of the silicon substrate 102, and to leave the polycrystalline silicon layers on the sidewalls on both sides of the selection gate 11 2, 1 1 4, 11 6, 11 8 1 24 forms a polycrystalline silicon sidewall 1 2 6. ~ As shown in Figure 10—'a photoresist layer 130 is then formed on the surface of the semiconductor wafer 100. The photoresist layer 130 covers the selection gate 114 and the selection electrode 116 and the polycrystalline silicon side. Above the surface of the wall 1 2 6 is used as a hard cover for the subsequent etching process and ion implantation process. Then, as shown in FIG. 11, a dry etching process is performed to remove the selection gate and the selection gate 114 and The polysilicon sidewall 12 between the selection gate 116 and the selection gate 118 that is not covered by the photoresist layer 130 is then subjected to an ion implantation process to select between the selection gate Π2 and the selection gate 114 and the selection gate A doping region 131 is formed on the surface of the silicon substrate 102 between the silicon substrate 11 and the selection gate 118. Note that, as shown in FIG. 12, the photoresist layer 13 is completely removed, and then the selection gate 112 is formed. And select gate 114 and select gate 116 and

451480 V. Description of the invention (8) A photoresist layer 1 3 6 is formed between the selection gate 11 8 to cover the selection gate 1 1 2 and the selection gate 1 1 4 and the selection gate i 1 6 and the selection Above the gate i 丨 8. Subsequently, a self-aligned ion implantation process is performed, using the selective closed electrodes 114, 116 and the polycrystalline silicon sidewalls 126 therebetween as a hard mask, and the polycrystalline silicon sidewalls 1 2 6 between the selection gates 11 4 and 1 1 6 A source doped region 133 is formed on the surface of the silicon substrate i 0 2, and the photoresist layer 136 is completely removed. Then, as shown in FIG. 14, after the photoresist layer 136 is completely removed, a rapid thermal process (RTP) is then used to bring down the dopants in the drain doped regions 131 and the source doped regions 133. It goes into the silicon substrate 102 to form a drain 132 and a source 134. Then a chemical vapor deposition process is performed to form a silicon oxide layer 138 with a thickness of about 1.5 to 2 μm on the surface of the semiconductor wafer 100, and cover the dielectric layer 108, the selection gate} i 2, U4, ii 6, ii 8 and the surface of the polycrystalline silicon wall 126. As shown in FIG. 15, an anisotropic dry etching process is then performed to remove a silicon oxide layer 1 38 having a thickness of about 1.7 to 2. m and a thickness of about 2 5 0 to 2 8 0. A dielectric layer of 0 angstrom 〇0 ′ makes the thickness of the remaining dielectric layer 〇8 about 500 to 800 angstroms. Then, an insulating layer 142 'is formed on the surface of the semiconductor wafer ιo and covers the exposed surface of the silicon oxide layer 138, the dielectric layer ι 08, and the side wall 126. The insulating layer 1 * 2 is a thickness of about 9 5 to 175 Angstroms (N 0 0 × ldlzed-Sllicon nitride-silicon oxide) dielectric. shape

Page 11 45 1 48 〇__ 一 -----------.......................... 5. Description of the invention (9) Insulation layer 1 The method of 42 is to first form a native oxide layer (not shown) with a thickness of about 10 to 50 angstroms on the surface of the polycrystalline silicon sidewalls 1 2 6. Next, a plasma-enhanced CVD (PECVD) process or an LPCVD process is performed with dichlorosilane (SiH2C12) and ammonia (ammonia, nh3) as a reaction gas. A silicon nitride layer (not shown) having a thickness of about 45 Angstroms is deposited on the surface of the native oxide layer. Finally, the semiconductor wafer 100 is subjected to a high-temperature healing process for about 30 minutes in a high-temperature oxygen-containing environment at about 8000 degrees Celsius to form a thickness of about 40 to 80 angstroms on the surface of the silicon nitride layer. Contains a silicon oxy-nitride layer (not shown). As shown in FIG. 16, a polycrystalline silicon layer 144 having a thickness of about 3000 to 3500 angstroms is then deposited on the semiconductor wafer 100 surface by a chemical vapor deposition method. Finally, as shown in FIG. 17, a yellow light process and a dry etching process are used to etch the polycrystalline silicon layer 1 44 downward to form a polysilicon sidewall 1 2 6 between the selective gate 114 and the selective gate 116. One control gate 1 4 5 completes the production of the flash memory unit 150. Because the method of the present invention uses the polysilicon sidewall spacers 1 2 6 as floating poles to achieve self-alignment. In addition, the method of the present invention is to form a silicon oxide layer ι38 with a thickness of about I 5 to m on the surface of the semiconductor wafer 100, and then use an anisotropic dry etching process to remove the thickness of about 1.7 to 2 2 A. m of silicon oxide layer 138 and a dielectric layer 1 08 ′ having a thickness of about 2500 to 2800 angstroms, thereby effectively increasing the thickness of the polycrystalline silicon sidewall 126 and the control gate i45.

Page 12 4 5 1 48 〇 V. Capacitive area between inventions, increase CR value, reduce operating voltage of flash memory unit 150 writing or erasing. Compared with the conventional lack of CR value of the separation gate flash memory unit, the present invention provides a method for manufacturing a separation gate flash memory unit with a high CR value, so as to effectively improve the separation gate flash memory unit. The capacitance area between the floating gate and the control gate increases the CR value, thereby improving the performance of the flash memory cell. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 13 at 51 Brief description of the diagram Brief description of the diagram Figure 1 is a schematic diagram of the cross-sectional structure of a conventional stacked gate flash memory unit. Fig. 2 is a schematic sectional view of a conventional split gate flash memory unit. FIG. 3 is a schematic diagram of the equivalent circuit of the split gate flash memory in FIG. 2. Figures 4 to 7 are schematic diagrams of conventional methods for making a separate gate flash memory unit. FIG. 8 to FIG. 17 are schematic diagrams of a method for manufacturing a split gate flash memory unit according to the present invention. Symbol description in the figure 10 stacked gate flash memory; cell 11 stacked gate 12 gate oxide layer 14 floating gate 16 insulation layer 18 control gate 20 silicon substrate 22 drain 24 source 30 separated gate flash memory unit 31 Select channel 32 Gate oxide layer 34 Floating gate 36 Insulating layer 38 Control gate 40 Silicon substrate 42 Drain 44 Source 46 Equivalent capacitance 50 Semiconductor chip 52 Silicon substrate 54 Gate oxide layer 56 Photoresistance layer 60 channels

Page U 4 51 48 〇 Simple illustration

Page 15 62 Diffusion region 64 Polycrystalline silicon layer 66 Photoresistive layer 68 Silicon oxide layer 70 Polycrystalline silicon layer 80 Split gate flash memory cell 100 Polycrystalline silicon layer 102 Silicon substrate 104 Gate oxide layer 106 Polycrystalline silicon layer 108 Dielectric layer 112, 1 L14 , 116 '118 Select gate 122 Silicon dioxide layer 124 Polycrystalline silicon layer 126 Polycrystalline silicon sidewall 130 Photoresistive layer 132 Drain 134 Source 136 Photoresistive layer 138 Silicon oxide layer 142 Insulating layer 144 Polycrystalline silicon layer 145 Control gate

Claims (1)

45148〇 6. Application patent scope 1. A method for fabricating a self-aligned (se 1 f-a 1 igned) discrete inter-flash memory cell (sp 1 i ΐ gate flash memory cell) on a semiconductor wafer, which The semiconductor wafer includes a substrate, at least two select gates are disposed on the substrate, and a dielectric layer is disposed on each of the select gates. The method includes the following steps: On the two select gates Two polycrystalline silicon sidewalls are formed on the inner sidewalls between the electrodes; a drain is formed in each of the substrates adjacent to the outer sidewalls of the two selection gates; a source is formed in the substrate between the two polycrystalline silicon sidewalls; A silicon oxide layer is formed on the wafer surface and covers the surfaces of the dielectric layer, the two selective gates, and the two polycrystalline silicon sidewalls; a dry etch process is performed to Removing a silicon oxide layer of a predetermined thickness and removing the dielectric layer above each selection gate to a predetermined thickness; forming an insulating layer on a surface of the two polycrystalline silicon sidewalls; and A control gate is formed above the sidewall of the crystal; wherein the two polycrystalline silicon sidewall subsystems are used as self-aligning floating gates of the flash memory cell of the separation gate to The coupling ratio of the two fast memory cells of the separation gate is provided. 2. For the method of applying for the first item of the patent scope, wherein the two selection gate systems are Page 16 45148ο 6. The scope of patent application is composed of a first polycrystalline dream layer (p〇〗 ysilicOn layer) and a gate oxide layer (gate oxide) stacked on top of each other, and the two select gate on the side wall With a dream layer of dioxide. 3. The method according to item 1 of the patent application scope, wherein the dielectric layer is composed of silicon dioxide. 4. If applying for the inner side wall step between the substrates: perform a back surface on the surface of the semiconductor substrate, and form a crystalline silicon layer on each of the two first photoresist layers to perform a crystalline silicon side wall. , Child. The method of the first item of the scope of interest is the method of forming the two polycrystalline silicon sidewalls on the printed substrate. The method includes forming a silicon layer on the surface of the body wafer as follows: And covering the surface of each selection gate and the dielectric layer; in the manufacturing process to remove the second polycrystalline silicon == the third night crystal side wall on the surrounding side wall of the selection center; the inner side wall of the selection electrode Polycrystalline between; and the process of forming j above the Ming / Tiaozi to remove the non-first to form between the two selection gates: more 5. If the method of the scope of patent application No. 4, 1 by After the production process, the etching process is further included to form the drain electrode and the source electrode. The ion implantation process is adjacent to the second selection electrode. Page 17 4 5M806. A drain-doped region is formed in each of the substrates of the side walls of the patent application. 1 The first photoresist layer is completely removed. A second photoresist layer is formed on the surface of the semiconductor wafer. Two photoresist layers are not covered between the two selection gates; a second ion implantation process is performed to form a source doped region on the surface of the substrate between the polycrystalline silicon sidewalls between the two selection gates; completely Removing the second photoresist layer; and performing an annealing process to complete the fabrication of the anode and the source. 6. The method according to item 1 of the patent application, wherein the insulating layer is an ONO (oxidized-silicon nitride-silicon oxide) dielectric mill. 7. The method according to item 1 of the patent application, wherein the control gate It is composed of doped polycrystalline stone. 8. A method for manufacturing a split gate flash memory unit with a high coupling ratio. The split gate flash memory unit is fabricated on a semiconductor wafer. The semiconductor wafer includes a silicon substrate. The method includes the following steps: A gate oxide layer, a first polycrystalline silicon layer, and a dielectric layer are sequentially formed on the surface of the substrate; a lithography process and a dry rice engraving process are performed to etch the dielectric layer, the first The crystalline silicon layer reaches the surface of the gate oxide layer in a shape of Page 18 45 1 48 ο-6. The scope of patent application is a first selection gate, a second selection gate and a third selection gate; on the side walls on both sides of the first, second and third selection gates Forming a polycrystalline silicon sidewall each; removing the polycrystalline silicon sidewall on the sidewall between the second and third selection gates; forming a drain electrode on the surface of the silicon substrate between the second and third selection gates; A source is formed on the surface of the silicon substrate between the polysilicon sidewalls on the first and second selection gate sidewalls; a silicon oxide layer is formed on the surface of the semiconductor wafer and covers the first, second, and third layers Select the gate and the surface of the polycrystalline silicon sidewall; perform a dry etching process to remove the silicon oxide layer of a predetermined thickness and remove the dielectric layer above each selected gate to a predetermined thickness; on the polycrystalline silicon sidewall An insulating layer is formed on the surface; and a control gate is formed above the polycrystalline silicon sidewall between the first and second selection gates; wherein the polycrystalline silicon sidewall is used as the separation gate fast The floating gate of the flash memory unit to increase the coupling value of the split gate flash memory unit. 9. The method according to item 8 of the patent application, wherein the method for forming the polycrystalline silicon sidewall comprises the following steps: forming a second polycrystalline silicon layer on the surface of the semiconductor wafer and covering the silicon substrate; First, second and third selection gate surfaces; and Page 19, 45148 ο 6. The scope of the patent application is to perform an etching process to remove the second polycrystalline silicon layer up to the surface of the substrate and leave it on the sidewalls of the first, second and third selection gates. The second polycrystalline silicon layer forms the polycrystalline silicon sidewall. 10. The method according to item 8 of the patent application, wherein the method for removing the polysilicon sidewall between the second and third selection gates includes the following steps: forming a first between the first and second selection gates A first photoresist covers the polycrystalline silicon sidewall sub-surfaces above the first and second selection gates and between the first and second gates; and an etching process is performed to remove the second and third selection gates. Crystal dreams. 11. If the method of claim 10 is applied, after removing the polysilicon sidewall between the first and third selection gates, the method still includes the following steps: An ion implantation process is performed for the second and third selection gates. A drain is formed on the surface of the silicon substrate between the third selection; the first photoresist layer is completely removed; a second photoresist layer is formed between the second and third selection gates to cover the second and third selections Above the gate; perform a self-aligned ion implantation process, using the first and selected polycrystalline silicon sidewalls between the gates as a hard mask, so that the polycrystalline silicon sidewalls between the first and second selected gates The surface of the silicon substrate is formed with two silicon electrodes (and a step layer, and the inter-electrode two is selected to contain a gate electrode, and the second and the first electrode are formed into one). Page 20 4 5 1 48 〇 6. Patent application source; and 'The second photoresist layer is completely removed. 12 2. The method according to item 11 of the scope of patent application, wherein the first and second photoresist layers are used as hard masks for the ion implantation process and the self-aligned ion implantation process, respectively. ). 1 3. The method according to item 8 of the patent application, wherein after forming the first, second and third selection gates, the method further includes a thermal oxidation process for exposing the first polycrystalline layer The surface is oxidized to form a layer of dioxide. 14. The method according to item 8 of the patent application, wherein the insulating layer is a 100N dielectric layer. 15. The method according to item 8 of the patent application, wherein the control gate is composed of doped polycrystalline silicon. Page 21