4513 94 五、發明說明（i) 發明之領域 本發明係提供一種於一半導體晶片表面形成一擴散阻 障層的方法，尤指一種於半導體晶片表面形成一由氮化鈦 與鎢金屬所構成之堆疊式金屬阻障層的方法。 背景說明 由於氮化鈦（"titanium nitride，ΤίΝ)具有高的熱穩 定性、抗腐蝕性及良好的阻障特性，所以在目前的半導體 製程中，氮化鈦已經被廣泛地用來當作積體電路之金屬化 製程中的擴散阻障層（diffusion barrier layer)或黏著 層(glue layer)。 然而，利用物理氣相沈積（physica 1 vapor deposition, PVD)的方式所形成之氮化欽薄膜具有不良的 覆蓋性（non-conformal step coverage)，使其在應用上 受到报大的限制。因此隨著半導體元件的設計尺寸微縮至 深次微米的領域時，以化學氣相沈積（chemi cal vapor deposition, CVD)所形成的氮化鈦薄膜便不斷地發展，並 大量地被應用於形成金屬阻障層的技術中，其具有相當優 異的覆蓋性（step coverage)以及均句性（conformity)。 請參考圖一至圖三，圖一至圖三為習知於一半導體晶 片10上形成一擴散阻障層2 2的方法示意圖。如圖一所示， 半導體晶片1 〇包含有一單晶矽層1 2，一閘極1 3設於單晶矽4513 94 V. Description of the Invention (i) Field of the Invention The present invention provides a method for forming a diffusion barrier layer on the surface of a semiconductor wafer, especially a method for forming a semiconductor wafer surface composed of titanium nitride and tungsten metal. Method for stacking metal barrier layers. Background: Titanium nitride (Titanium) has high thermal stability, corrosion resistance, and good barrier properties. Therefore, in the current semiconductor manufacturing process, titanium nitride has been widely used as Diffusion barrier layer or glue layer in metallization process of integrated circuit. However, the nitride film formed by physical vapor deposition (PVD) has a poor non-conformal step coverage, which limits its application. Therefore, as the design size of semiconductor devices is reduced to the sub-micron field, titanium nitride films formed by chemical vapor deposition (CVD) have been continuously developed and are widely used to form metals. In the technology of the barrier layer, it has quite excellent step coverage and conformity. Please refer to FIGS. 1 to 3, which are schematic diagrams of a conventional method for forming a diffusion barrier layer 22 on a semiconductor wafer 10. As shown in FIG. 1, the semiconductor wafer 10 includes a single crystal silicon layer 12 and a gate electrode 13 is disposed on the single crystal silicon.
451394 五、發明說明（2) 層1 2的表面’一由氮化矽構成的侧壁子1 5設於閘極丨3之周 圍側壁上，一摻雜區1 8設於接觸洞1 6内之單晶矽層1 2的表 面’一矽氧層1 4設於單晶矽層1 2之上並覆蓋住閘極1 3及摻 雜區1 8，一接觸洞1 6貫穿矽氧層1 4直到單晶矽層1 2表面之 摻雜區 18，以及一矽化鈦（titanium silicide, TiSi2)層 2 0設於摻雜區1 8的表面。 如圖二所示，習知技術是將先通入四氯化鈦 (titanium tetrachloride，TiCl4)與氨氣（ammonia, ΝΗ3) 做為反應氣體，且將反應溫度控制於大約6 5 ，進行一 電漿增強化學亂沈積（plasma enhanced chemical vapor deposition, PECVD)製程，以於半導體晶片10表面形成— 氮化鈦（titanium nitride，TiN)層22。如圖三所示，接 著於半導體晶片10表面上形成一铭金屬層24。其中化鈦 層2 2主要用來作為鋁金屬層24之擴散阻障層（(11“1131〇11 barrier layer)，以避免鋁金屬原子向下擴散，並提昇鋁 金屬與半導體晶片]_ 〇的附著能力。 然而*由於利用CVD所形成之氮化鈦層22的晶粒為柱 狀結構’而且鋁金屬的熔點僅約在3 8 0°C左右，因此鋁金 屬層2 4的原子在後續的高溫製程中將沿著氮化鈦層2 2之柱 狀結構的邊界（grain boundary)向下擴散至單晶梦層12 中’導致接面發生尖峰（spiking)現象，造成接面的漏電 流’進而嚴重影響元件的可靠性。 451394 五、發明說明（3) 發明概述 本發明之主要目的在提供一種於一半導體晶片表面形 成一擴散阻障層的方法，以解決上述習知技術之問題。 本發明係提供一種於一半導體晶片表面形成一堆疊式 擴散阻障層的方法。該方法是先利用一化學氣相沈積製 程於該半導體郎片上形成一氮化欽（titanium nitride, TiN)層。接著進行一電漿增強化學氣相沈積（plasma enhanced chemical vapor deposition, PECVD)製程，於 該氮化鈦層表面形成一非晶；s夕（affl〇rph〇us siiicon，α -Si)層’然後通入一六氣化鶴（tungsten hexafluoride, WF6)氣體來與該非晶矽層相作用，進行一矽還原（s丨丨icon reduction)反應’生成鎢並沈積於該氮化鈇層表面，以於 該氮化鈦層表面形成一鎢金屬（tungsten, W)層。最後於 該鎢金屬層表面形成一金屬層，作為金屬導線。其中該氮 化鈦層與該鶴金屬層係用來作為一维疊式金屬阻障層，以 避免該金屬層中的原子擴散進入該半導體晶片表面》 本發明係以低溫（低於4 0 0°C )反應生成的鎢金屬來沈 積於該氮化鈦層表面’填塞入該氮化鈦層之柱狀結構的邊 界，以避免該金屬層的原子擴散進入該半導體晶片的表 面。因此本發明可以有效地避免尖峰現象的發生，進而提 高製程的可靠性以及元件的可靠度。此外，由於鎢金屬的451394 V. Description of the invention (2) The surface of the layer 12 is a side wall made of silicon nitride 15 is provided on the side wall surrounding the gate 3, and a doped region 18 is provided in the contact hole 16 The surface of the single crystal silicon layer 12 is a silicon oxide layer 1 4 which is disposed on the single crystal silicon layer 12 and covers the gate electrode 13 and the doped region 18. A contact hole 16 penetrates the silicon oxide layer 1. The doped region 18 up to the surface of the single crystal silicon layer 12 and a titanium silicide (TiSi2) layer 20 are disposed on the surface of the doped region 18. As shown in Figure 2, the conventional technique is to first pass titanium tetrachloride (TiCl4) and ammonia (ammonia, ΝΗ3) as the reaction gas, and control the reaction temperature to about 6 5 to perform an electric A plasma enhanced chemical vapor deposition (PECVD) process is used to form a titanium nitride (TiN) layer 22 on the surface of the semiconductor wafer 10. As shown in FIG. 3, a metal layer 24 is formed on the surface of the semiconductor wafer 10. Among them, the titaniumized layer 22 is mainly used as a diffusion barrier layer ((11 "1131〇11 barrier layer) of the aluminum metal layer 24 to prevent the aluminum metal atoms from diffusing downward and to promote aluminum metal and semiconductor wafers] _ 〇 Adhesion ability. However * Because the grains of the titanium nitride layer 22 formed by CVD are columnar structures' and the melting point of the aluminum metal is only about 38 ° C, the atoms of the aluminum metal layer 24 are in the subsequent During the high-temperature process, the grain boundary of the columnar structure along the titanium nitride layer 22 will diffuse down into the single crystal dream layer 12 'resulting in spiking of the junction and cause leakage current of the junction' This further severely affects the reliability of the device. 451394 V. Description of the invention (3) Summary of the invention The main purpose of the present invention is to provide a method for forming a diffusion barrier layer on the surface of a semiconductor wafer to solve the problems of the conventional technology. The invention provides a method for forming a stacked diffusion barrier layer on the surface of a semiconductor wafer. The method first uses a chemical vapor deposition process to form a titanium nitride on the semiconductor wafer. TiN) layer. Then a plasma enhanced chemical vapor deposition (PECVD) process is performed to form an amorphous on the surface of the titanium nitride layer; afflórph〇us siiicon, α-Si ) Layer, and then a tungsten hexafluoride (WF6) gas is introduced to interact with the amorphous silicon layer to perform a silicon reduction (icon reduction) reaction to generate tungsten and deposit it on the hafnium nitride layer On the surface, a tungsten metal (tungsten, W) layer is formed on the surface of the titanium nitride layer. Finally, a metal layer is formed on the surface of the tungsten metal layer as a metal wire. The titanium nitride layer is used for the crane metal layer. As a one-dimensional stacked metal barrier layer to prevent the atoms in the metal layer from diffusing into the surface of the semiconductor wafer. The present invention is a method of depositing tungsten metal at a low temperature (less than 400 ° C) on the nitrogen. The surface of the titaniumized layer is filled into the boundary of the columnar structure of the titanium nitride layer to prevent the atoms of the metal layer from diffusing into the surface of the semiconductor wafer. Therefore, the present invention can effectively avoid the occurrence of spikes, thereby improving the manufacturing process. Process reliability and component reliability. In addition, due to the
1513 9 4 五、發明說明（4) 電阻係數較低，因此可以降低該擴散阻障層的電阻係數。 發明之詳細說明 請參考圖四直圖六’圖四至圖六為本發明於一半導體 晶片40上形成一擴散阻障層5 8的方法示意圖。如圖四所 示，半導體晶片40包含有一單晶矽層42，一閘極43設於單 晶石夕層4 2表面，一由氮化石夕構成之侧壁子4 5設於閘極4 3之 侧壁上，一導電層44設於單晶碎層42表面’一介電唐46設 於單晶矽層4 2表面並覆蓋於導電層44之上，以及一接觸洞 (contact hole)48貫穿介電層46直到導電層44的表面。其 中導電層4 4係用來做為一祕08(1116士81-〇又1(^ semiconductor)電晶體的没極或源極，其包含有一摻雜 區，以及一由硬化鈦（titanium silicide，TiSi 2)構成的 金屬矽化物層設於該摻雜區之上。此外。導電層44亦可由 一單晶矽摻雜區與一摻雜之多晶矽層構成。 如圖五所示，本發明是先通入四氯化鈦（titanium tetrachloride，TiCl 4)與氨氣（ammonia, NH3)做為反應氣 體，並將反應溫度控制於6 5 0°C左右，以進行一電漿增強 化學氣沈積（plasma enhanced chemical vapor depos i ΐ i on, PECVD)製程，於半導體晶片40表面形成一氮 化鈦（titanium nitride，TiN)層50。接著將溫度控制於 3 0 0°C至3 5 0°C之間，進行另一電漿增強化學氣沈積製程， 於氮化鈦層50表面形成一厚度約為10奈米（nanometer,1513 9 4 V. Description of the invention (4) The resistivity is low, so the resistivity of the diffusion barrier layer can be reduced. Detailed description of the invention Please refer to FIG. 4, FIG. 6, and FIG. 4 to FIG. 6 are schematic diagrams of a method for forming a diffusion barrier layer 58 on a semiconductor wafer 40 according to the present invention. As shown in FIG. 4, the semiconductor wafer 40 includes a single-crystal silicon layer 42, a gate electrode 43 is provided on the surface of the single-crystal stone layer 4 2, and a side wall 4 5 composed of a nitride stone is provided on the gate electrode 4 3 On the side wall, a conductive layer 44 is provided on the surface of the single crystal chip layer 42. A dielectric layer 46 is provided on the surface of the single crystal silicon layer 42 and covers the conductive layer 44 and a contact hole 48. The dielectric layer 46 is penetrated to the surface of the conductive layer 44. The conductive layer 44 is used as the anode or source of a 08 (1116 ± 81-〇 and 1 (^ semiconductor) transistor. It includes a doped region and a titanium silicide, A metal silicide layer composed of TiSi 2) is disposed on the doped region. In addition, the conductive layer 44 may also be composed of a single crystal silicon doped region and a doped polycrystalline silicon layer. As shown in FIG. 5, the present invention is First, titanium tetrachloride (TiCl 4) and ammonia (ammonia, NH3) were introduced as the reaction gases, and the reaction temperature was controlled at about 650 ° C to perform a plasma enhanced chemical gas deposition ( plasma enhanced chemical vapor depos i ΐ i on (PECVD) process, a titanium nitride (TiN) layer 50 is formed on the surface of the semiconductor wafer 40. The temperature is then controlled between 300 ° C and 350 ° C. In the meantime, another plasma enhanced chemical gas deposition process is performed to form a thickness of about 10 nanometers (nanometer,
451 3 94 五、發明說明（5) - nm)的非晶石夕(amorphous silicon, a ~si)層52，伯支為曰 種層(seed layer) ° 如圖六所示，接著通入一六氟化鶴（tungSten h e X a f 1 u 〇 r i d e，W F s)氣體，以與該非晶石夕層5 2相作用進行 一梦還原(silicon reduction)反應。由於非晶石夕層52中 的矽會還原該六氟化鎢氣體中的鎢，所以還原後的鎢會沈 積於氮化鈦層5 0表面，形成一厚度約為10奈米的鎢金屬層 54。而氮化鈦層5 0與鎢金屬層5 4即構成一堆疊式的擴散阻 障層56。最後在於半導體晶片40表面上形成一鋁金屬 (alumimim, A1)詹58β紹金属層58是用來做為金屬導線’ 亦可以銅或鋁銅合金構成。 由於利用低溫CVD所沈積之鎢金屬層54中部分的鶴原 子會填塞入氮化鈦層5 0之柱狀結構的邊界裡’使氣化欽層 5 0更加緻密，因此可避免鋁金屬層5 6的銘原子在後續高溫 製程中穿過氮化鈦層5 0之枉狀結構的邊界’而與下層的單 晶矽層42發生相互擴散的現象。故本發明可有效地避免尖 峰現象的發生，進而提高製程的穩定性以及元件的可靠 度。此外，由於具有低電阻係數（約5以Ω 的鶴金属播 入電阻係數較高之氮化鈦層中（約丨1" Ω -CIU) ’因此又可 降低擴散阻障層5 6的電阻係數° 請參考圖七至圖九，圖七至圖為本發明於一半導體晶 451 3 94 五、發明說明（6) 片6 0上形成一擴散阻障層7 6之另一實施例的方法示意圖，。 如圖七所示，半導體晶片60包含一基底62，一鋁 (aluminum, A1)金屬層64設於基底6 2之上’ 一具低介電常 數之介電層6 6設於銘金屬層6 4之上’以及一介層洞6 8貫穿 介電層6 6直到鋁金屬層6 4的表面。 如圖八所示，本發明是先通入四氣化鈦（T i C 1 4)與氨 氣（N Η 3)做為反應氣體，並將反應溫度控制低於4 0 0°C， 來進行一電漿增強化學氣沈積製程’以於半導體晶片60表 面形成一氮化鈦層7 0。接著將溫度控制於3 0 (TC至3 5 (TC之 間，進行另一電漿增強化學氣沈積製程，於氮化鈦層70表 面形成一厚度約為1 0奈米的非晶矽層72。 如圖九所示，接著通入一六氟化鎢（WF 6)氣體，以與 該非晶石夕層72相作用進行一石夕還原（silicon reduction) 反應。非晶矽層7 2中的矽會還原該六氟化鎢氣體中的鎢， 而且還原後的鎢會沈積於氮化鈦層70表面以形成一厚度約 為10奈米的鎢金屬層74。最後再半導體晶片60表面上形成 一鋁金屬層78，當做金屬導線。其中氮化鈦層70與鎢金屬 層7 4即構成一堆疊式的擴散阻障層76，而鋁金屬層6 4和鋁 金屬層7 8可以利用銅或鋁銅合金來構成。 由於低溫沈積之鎢金屬層74中的鎢會填塞入氮化鈦層 7 0之柱狀結構的邊界’因此可避免鋁金屬層7 8和6 4的鋁原451 3 94 V. Description of the invention (5)-nm) Amorphous silicon (a ~ si) layer 52, the primary branch is the seed layer ° As shown in Figure 6, then a TungSten he X af 1 u ride (WF s) gas interacts with the amorphous stone layer 52 to perform a silicon reduction reaction. Since the silicon in the amorphous stone layer 52 will reduce the tungsten in the tungsten hexafluoride gas, the reduced tungsten will be deposited on the surface of the titanium nitride layer 50 to form a tungsten metal layer with a thickness of about 10 nm. 54. The titanium nitride layer 50 and the tungsten metal layer 54 constitute a stacked diffusion barrier layer 56. Finally, an aluminum metal (alumimim, A1) Zhan 58β metal layer 58 is formed on the surface of the semiconductor wafer 40. The metal layer 58 is used as a metal wire ', and can also be made of copper or aluminum-copper alloy. Since part of the crane atoms in the tungsten metal layer 54 deposited by low-temperature CVD will be packed into the boundary of the columnar structure of the titanium nitride layer 50, which makes the gasification layer 50 more dense, the aluminum metal layer 5 can be avoided. In the subsequent high-temperature process, the atom of 6 passes through the boundary of the 枉 -shaped structure of the titanium nitride layer 50 and inter-diffuses with the underlying single-crystal silicon layer 42. Therefore, the present invention can effectively avoid the occurrence of spikes, thereby improving the stability of the process and the reliability of the device. In addition, because of its low resistivity (about 5 ohms of the crane metal is planted into the titanium nitride layer with a higher resistivity (about 丨 1 " Ω -CIU) ', the resistivity of the diffusion barrier layer 56 can be reduced. ° Please refer to FIGS. 7 to 9, which are schematic diagrams of another embodiment of a method for forming a diffusion barrier layer 7 6 on a semiconductor crystal 451 3 94 5. Description of the invention (6) A sheet 60 As shown in FIG. 7, the semiconductor wafer 60 includes a substrate 62, and an aluminum (A1) metal layer 64 is provided on the substrate 62. A dielectric layer 66 with a low dielectric constant is provided on the metal. Above layer 6 4 'and a dielectric hole 6 8 penetrates the dielectric layer 66 to the surface of the aluminum metal layer 64. As shown in FIG. 8, the present invention is first passed through titanium tetraoxide (T i C 1 4) And ammonia gas (N Η 3) as a reaction gas, and the reaction temperature is controlled below 400 ° C, to perform a plasma enhanced chemical gas deposition process' to form a titanium nitride layer on the surface of the semiconductor wafer 60 7 0. Then control the temperature between 30 (TC to 3 5 (TC), and perform another plasma enhanced chemical gas deposition process on the surface of the titanium nitride layer 70 An amorphous silicon layer 72 having a thickness of about 10 nanometers is formed. As shown in FIG. 9, a tungsten hexafluoride (WF 6) gas is then introduced to interact with the amorphous stone layer 72 to perform a stone reduction ( silicon reduction) reaction. The silicon in the amorphous silicon layer 72 will reduce the tungsten in the tungsten hexafluoride gas, and the reduced tungsten will be deposited on the surface of the titanium nitride layer 70 to form a thickness of about 10 nm. The tungsten metal layer 74. Finally, an aluminum metal layer 78 is formed on the surface of the semiconductor wafer 60 as a metal wire. The titanium nitride layer 70 and the tungsten metal layer 74 constitute a stacked diffusion barrier layer 76, and the aluminum metal The layer 64 and the aluminum metal layer 78 can be made of copper or aluminum-copper alloy. Since the tungsten in the tungsten metal layer 74 deposited at a low temperature will fill the boundary of the columnar structure of the titanium nitride layer 70, aluminum can be avoided. Aluminum layers with metal layers 7 8 and 6 4
第9頁 451394 五、發明說明（7) 子在後續高溫製程中’擴散進入氮化鈦層7 0之中。姑士 * 琢本發明 可以有效地減少銘金屬原子的擴散路徑，進而桓古制 风内製程的Page 9 451394 V. Description of the invention (7) The particles diffuse into the titanium nitride layer 70 in the subsequent high temperature process. Guru * This invention can effectively reduce the diffusion path of metal atoms, and thus the ancient process
可靠性以及元件的可靠度。此外由於具有低電阻係數 J 5//〇-<3〇1)的鶴金屬摻入氮化敏層中，因此可以谁___1^''‘' ^ 疋一·步地 降低擴散阻障層6 8的電阻係數。而且由於氮化鍊層？ 〇與 屬鎢層74都是低溫（小於400eC )下形成，不會對低介電常4 數之材料層的特性造成熱傷害，因此可以應用於以低介 常數之材料為介電層的多層導線之連接結構的半導體 中。 相較於習知形成擴散阻障層的方法，本發明是利用低 溫沈積的金屬鎢填塞入氮化鈦層之柱狀結構的邊界，形成 一堆疊式的擴散阻障層。此外，由於具有低電阻係數的瑪 金屬摻入氮化鈦層中，因此可以降低擴散阻障層的電阻係 數。而且由於氮化鈦層與金屬鎢層都是在低溫下形成，因 此可以應用於以低介電常數之材料為介電層的高效能多層 導線連接結構製程中，而不會影響對製程溫度有高敏感性 之低介電常數材料的介電特性。 以上所述僅本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修皆應屬本發明專利之涵蓋 範圍》Reliability and component reliability. In addition, since the crane metal with a low resistivity J 5 // 〇- < 3〇1) is incorporated into the nitride-sensitive layer, who can ___ 1 ^ '' '' ^ reduce the diffusion barrier layer step by step 6 8 Resistivity. And because of the nitride chain layer? Both the tungsten layer 74 and the tungsten layer 74 are formed at a low temperature (less than 400eC), and will not cause thermal damage to the characteristics of the material layer with a low dielectric constant. Therefore, it can be applied to a multilayer with a low dielectric constant material as a dielectric layer. In the semiconductor of the connection structure of the wires. Compared with the conventional method for forming a diffusion barrier layer, the present invention uses low-temperature deposited metal tungsten to fill the boundary of the columnar structure of the titanium nitride layer to form a stacked diffusion barrier layer. In addition, since a metal having a low resistivity is incorporated into the titanium nitride layer, the resistance coefficient of the diffusion barrier layer can be reduced. And because the titanium nitride layer and the metal tungsten layer are both formed at a low temperature, it can be applied to the process of a high-performance multilayer wire connection structure using a low dielectric constant material as a dielectric layer without affecting the process temperature. Dielectric properties of highly sensitive low dielectric constant materials. The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the present invention patent "
第10頁 451 3β 4 圖式簡單說明 圖示之簡單說明 圖一至圖三為習知形成擴散阻障層的方法示意圖。 圖四至圖六為本發明形成擴散阻障層的方法示意圖。 圖七至圖九為本發明另一實施例形成擴散阻障層的方 法示意圖。 圖示之符號說明 10 半 導 體 晶 片 12 單 晶 矽 層 13 閘 極 14 矽 氧 層 15 側 壁 子 16 接 觸 洞 18 摻 雜 區 20 矽 化 鈦 層 22 氮 化 鈦 層 24 鋁 金 屬 層 40 半 導 體 晶 片 42 單 晶 矽 層 43 閘 極 44 導 電 層 45 側 壁 子 46 介 電 層 48 接 觸 洞 50 氮 化 鈦 層 52 非 晶 矽 層 54 鶴 金 屬 層 56 擴 散 阻 障 層 58 鋁 金 屬 層 60 半 導 體 晶 片 62 基 底 64 鋁 金 屬 層 66 介 電 層 68 介 層 洞 70 氮 化 鈦 層 72 非 晶 矽 層 74 鎢 金 屬 層 76 擴 散 阻 障 層 78 鋁 金 屬 層Page 10 451 3β 4 Brief description of the diagrams Brief description of the diagrams Figures 1-3 are schematic diagrams of conventional methods for forming a diffusion barrier layer. 4 to 6 are schematic diagrams of a method for forming a diffusion barrier layer according to the present invention. 7 to 9 are schematic diagrams of a method for forming a diffusion barrier layer according to another embodiment of the present invention. Explanation of symbols in the diagram 10 Semiconductor wafer 12 Monocrystalline silicon layer 13 Gate 14 Silicon oxide layer 15 Side wall 16 Contact hole 18 Doped region 20 Titanium silicide layer 22 Titanium nitride layer 24 Aluminum metal layer 40 Semiconductor wafer 42 Monocrystalline silicon Layer 43 gate 44 conductive layer 45 sidewall 46 dielectric layer 48 contact hole 50 titanium nitride layer 52 amorphous silicon layer 54 crane metal layer 56 diffusion barrier layer 58 aluminum metal layer 60 semiconductor wafer 62 substrate 64 aluminum metal layer 66 Dielectric layer 68 Via hole 70 Titanium nitride layer 72 Amorphous silicon layer 74 Tungsten metal layer 76 Diffusion barrier layer 78 Aluminum metal layer