451 3 95 5014twi'.d〇c/0 02 五、發明說明（f ) 本發明是有關於一種積體電路的製造方法，且特別 是有關於一種淺溝渠隔離的製造方法。 在積體電路蓬勃發展的今日，元件縮小化與積集化 是必然之趨勢，也是各界積極發展的重要課題。當元件尺 寸逐漸縮小，積集度（Integrat1〇n)逐漸提高，元件間的隔離 結構也必須縮小，因此元件隔離技術困難度也逐漸增高。 元件隔離有利用區域氧化法（Local Oxidation，LOCOS)來 形成的場氧化層(Field Oxide)，由於場氧化層受限於其外 型之鳥嘴（Bird’s Beak)特性，要縮小其尺寸實有困難。有 鑒於此，已有其他元件隔離方法持續被發展出來，其中以 淺溝渠隔離（Shallow Trench Isolation，STI)最被廣泛應用\ 尤其應用於次半微米（Sub-half Micron)的積體電路製程 中。 淺溝渠隔離的製造中，一般使用氮化矽作爲硬罩幕， 以非等向性（anisotropy)蝕刻法在半導體基底上定義陡峭的 溝渠。之後再將溝渠塡滿氧化物形成氧化物插塞，以作爲 元件淺溝渠隔離結構。但習知的溝渠隔離結構之底面積通 ................................ 養.渠的麗..5____小，在製程積集度逐漸提升的情況下，若 依舊使用習知的溝渠隔離結構，即表示由溝渠隔離結構所 隔開的兩主動區間的距離越來越小。換言之，由溝渠隔離 結構所隔開的兩主動區間的元件會產生橋接現象，而造成 電性的錯誤或元件損毀，特別在〇.18μιη以下的製程中， 此種現象會更形明顯。 本發明提出一種淺溝渠隔離的製造方法，首先形成 3 1ΙΙΙ1Ι— — — — |( ^ I I I (請先閱讀背面之注意事項再填寫本頁) 訂： 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 451331 A7 B7 五、發明說明（2 ) (請先閲讀背面之注意事項再填窝本頁) 一層墊氧化層於基底上，形成一層罩幕層於墊氧化層上， 定義罩幕層、墊氧化層和基底以形成溝渠及主動區，進行 熱氧化步驟使罩幕層所暴露出之側壁連同溝渠中沿著曝露 的基底表面氧化成一層襯氧化層，於溝渠與罩幕層之側壁 形成一層間隙壁，再進行氧化步驟，形成一層絕緣層於基 底上並塡滿溝渠，進行平坦化製程以去除部份絕緣層與部 份罩幕層，僅留下溝渠中的絕緣插塞，然後去除罩幕層、 墊氧化層。 V; 乂 本發明提出一種淺溝渠隔離的製造方法，適用於一 基底，基底具有溝渠與主動區，主動區之基底上依序爲一 層墊氧化層與一層罩幕層，溝渠所暴露出之基底表面具有 一層襯氧化層，先於溝渠與罩幕層之側壁形成一層間隙 壁，再進行氧化步驟，形成一層絕緣層於基底上並塡滿溝 渠，進行平坦化製程以去除部份絕緣層與部份該罩幕層， 僅留下溝渠中的絕緣插塞，然後去除該罩幕層、該墊氧化 層。 經濟部智慧財產局貝工消費合作社印製 本發明提出一種淺溝渠隔離的製造方法，適用於已 完成淺溝渠製造之基底，本方法先於溝渠所暴露之基底表 面形成一層襯氧化層，再於溝渠之側壁形成一層間隙壁， 進行氧化步驟，然後形成一層絕緣層於基底上並塡滿溝 渠，再去除溝渠外之絕緣層。 由於本發明兩相鄰主動區之元件間若欲像習知一般 產生導通，則電流行進路線係由矽基底中繞越過溝渠中的 絕緣插塞與絕緣插塞下方的規則遞.想麗魇^.，比傳統不具 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 451 3 9¾ 5〇Ulw r.d〇c/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（，） 不規則形絕緣層之溝渠所產生的電流導通路徑還要長很 多，因此不會產生兩相鄰主動區間的橋接現象。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1H圖係依照本發明之一種淺溝渠隔離 區之製造流程剖面圖。 圖式之標記說明： 100 :基底 102 :墊氧化層 104 :罩幕層 106 :溝渠 108、109 :主動區 1 10 :襯氧化層 Π2 :氮化矽層 112a :間隙壁 1 14、1 16 :絕緣層 1 16a :絕緣插塞 實施例 第IA圖至第1H圖係依照本發明之一種淺溝渠隔離 區之製造流程剖面圖。 請參照第1A圖，在矽基底100上形成一層墊氧化層 102，用於保護基底100的表面，此一墊氧化層102將於 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁> -裝451 3 95 5014twi'.doc / 0 02 V. Description of the invention (f) The present invention relates to a method for manufacturing an integrated circuit, and more particularly to a method for manufacturing a shallow trench isolation. In today's booming development of integrated circuits, component downsizing and integration are an inevitable trend and an important issue for the active development of all sectors. When the component size is gradually reduced, the integration degree (Integrat10n) is gradually increased, and the isolation structure between components must also be reduced. Therefore, the difficulty of component isolation technology is gradually increasing. Element isolation uses a field oxide (LOCOS) to form a field oxide (Field Oxide). Because the field oxide is limited by its bird's beak characteristics, it is difficult to reduce its size. . In view of this, other component isolation methods have been continuously developed. Among them, Shallow Trench Isolation (STI) is the most widely used method, especially in the sub-half micron integrated circuit manufacturing process. . In the manufacture of shallow trench isolation, silicon nitride is generally used as a hard mask, and an anisotropy etching method is used to define steep trenches on a semiconductor substrate. The trench is then filled with oxide to form an oxide plug, which serves as a shallow trench isolation structure for the device. However, the area of the bottom of the conventional trench isolation structure is ... 5____ Small, if the process accumulation is gradually increasing, if the conventional trench isolation structure is still used, it means that the distance between the two active sections separated by the trench isolation structure is getting smaller and smaller. In other words, the components of the two active sections separated by the trench isolation structure will cause a bridging phenomenon, which will cause electrical errors or component damage, especially in processes below 0.18 μm, this phenomenon will be more obvious. The present invention proposes a manufacturing method for shallow trench isolation, first forming 3 1ΙΙΙ1Ι — — — — | (^ III (please read the precautions on the back before filling this page) Order: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The dimensions are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) 451331 A7 B7 V. Description of the invention (2) (Please read the precautions on the back before filling this page) A layer of oxide layer is formed on the substrate to form A mask layer is formed on the pad oxide layer. The mask layer, the pad oxide layer and the substrate are defined to form a trench and an active area. A thermal oxidation step is performed to oxidize the exposed sidewalls of the mask layer along with the trench along the exposed substrate surface. Form a layer of lining oxide layer, form a gap on the side wall of the trench and the cover layer, and then perform an oxidation step to form an insulating layer on the substrate and fill the trench, and perform a planarization process to remove part of the insulating layer and part of the cover. Curtain layer, leaving only the insulation plugs in the trench, and then removing the cover curtain layer and the pad oxide layer. V; 乂 The present invention provides a manufacturing method for shallow trench isolation, which is suitable for A substrate with a trench and an active area. The substrate in the active area is sequentially a pad oxide layer and a mask layer. The surface of the substrate exposed by the trench has a layer of lining oxide layer, which precedes the sidewalls of the trench and the mask layer. A layer of gap is formed, and then an oxidation step is performed to form an insulating layer on the substrate and fill the trench, and a planarization process is performed to remove part of the insulating layer and part of the cover layer, leaving only the insulating plugs in the trench. The cover layer and the pad oxide layer are then removed. Printed by the Shell and Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention proposes a manufacturing method for shallow trench isolation, which is suitable for the substrate for which shallow trench manufacturing has been completed. An oxide layer is formed on the exposed surface of the substrate, a gap is formed on the side wall of the trench, and an oxidation step is performed, and then an insulating layer is formed on the substrate and fills the trench, and then the insulating layer outside the trench is removed. If the conduction between the components in the adjacent active area is known as usual, the current travel path is bypassed by the insulating plug in the trench in the silicon substrate. The rules underneath the plug and the insulating plug are handed in. Want to be beautiful ^., Than the traditional 4 paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 451 3 9¾ 5〇Ulw rd〇c / 002 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (,) The current conduction path generated by the trench of the irregular insulation layer is much longer, so there will not be a bridge between two adjacent active sections. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A to Figure 1H is a cross-sectional view of the manufacturing process of a shallow trench isolation area according to the present invention. The marks of the drawings explain: 100: substrate 102: pad oxide layer 104: cover layer 106: trench 108, 109: active area 1 10: Oxide-lined layer Π2: Silicon nitride layer 112a: Spacer 1 14, 1 16: Insulating layer 1 16a: Insulating plug embodiment Figures IA to 1H are cross-sections of the manufacturing process of a shallow trench isolation area according to the present invention Illustration. Referring to FIG. 1A, a pad oxide layer 102 is formed on the silicon substrate 100 to protect the surface of the substrate 100. This pad oxide layer 102 will be applied to the Chinese paper standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling in this page > -install
1· n 1 fl I 0 451391 501 4iwr.d〇c/002 A7 B7 五、發明說明（w) 後續製程中，欲形成閘氧化層之前移去。通常，形成墊氧 化層102的方法可採用化學氣相沈積法。然後沈積一層罩 幕層1〇4以覆蓋住墊氧化層102，罩幕層104例如爲氮化 矽，罩幕層1〇4的形成方法可採用化學氣相沈積法。經微 影蝕刻製程形成定義此罩幕層102，以曝露出部分的墊氧 化層102，再依序蝕刻曝露之墊氧化層1〇2以及矽基底 1〇〇，以定義出溝渠106與主動區108、109。 請參照第1B圖，進行熱氧化步驟，使同溝渠106.中 沿著曝露的砂基底表面形成一層襯氧化層U0(Liner Oxide) 〇 請參照第1C圖，於基底100上形成一層共形的氮化 矽層112，例如使用化學氣相沈積法。 請參照第1D圖，再進行回蝕刻，例如使用非等向性 乾蝕刻以去除罩幕層102上的氮化矽層112(第1C圖）與溝 渠106底部的氮化矽層112(第1C圖），而於溝渠106之側 壁形成氮化矽材質的間隙壁112a。_ . 請參照第1E圖，進行一氧化法步驟，例如進行區域 氧化法，使溝渠106底部氧化成一類似塊狀的不規則形絕 緣層114,此絕緣層114即爲後續所形成溝渠隔離結構的 下半部份，由於受到絕緣層114的阻隔，後續完成元件之 製造後，主動區108之元件與主動區109之元件間若欲產 生導通，則電流行進路線係由主動區108於矽基底100中 繞越過絕緣層1 Μ而達到主動區109,比傳統不具不規則 形絕緣層114之溝渠所產生的電流導通路徑還要長，因此 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^—-—.—f裝------！訂------- {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4513 9¾ 50 ] 41 w I'.doc/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f) 不會產生主動區108、109間的橋接現象。 請參照第1F圖，去除間隙壁112a(第1E圖），在罩 幕層104之上形成一層絕緣層116，此絕緣層116並塡滿 溝渠106，常見的絕緣層材料爲氧化物，其可利用常壓化 學氣相沈積法（Atmospheric Pressure Chemical Vapor Deposition, APCVD)形成。經過密實化（Densification)步 驟，得以形成一結構較爲細密的絕緣層116。 請參照第1G圖，在密實化之後，進行平坦化製程， 例如使用化學機械硏磨法（Chemical Mechanical Polishing, CMP)，去除罩幕層104上之絕緣層116(第IF圖），而留 下溝渠區中的絕緣插塞116a。 請參照第1H圖，再去除罩幕層104(第1G圖）與墊氧 化層1〇2(第IG圖），例如使用濕蝕刻，而此步驟會同時去 除絕緣插塞116a之表面部位與絕緣插塞116a靠近主動區 表面之部位，而完成起溝渠隔離結構之製造。後續再進行 其他製程來完成各元件。 由上述本發明較佳實施例可知，本發明兩相鄰主動 區之元件間若欲像習知一般產生導通，則電流行進路線係 由矽基底中繞越過溝渠中的絕緣插塞與絕緣插塞下方的不 規則狀絕緣層，比傳統不具此不規則形絕緣層之溝渠所產 生的電流導通路徑還要長很多，因此不會產生兩相鄰主動 區間的橋接現象。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 7 (請先閱讀背面之注意事項再填寫本頁) '裝----I! — 訂----1 · n 1 fl I 0 451391 501 4iwr.doc / 002 A7 B7 V. Description of the invention (w) In the subsequent process, it is removed before the gate oxide layer is to be formed. In general, the method for forming the pad oxidation layer 102 can be a chemical vapor deposition method. Then, a mask layer 104 is deposited to cover the pad oxide layer 102. The mask layer 104 is, for example, silicon nitride. The mask layer 104 may be formed by a chemical vapor deposition method. The lithographic etching process is used to define the mask layer 102 to expose a part of the pad oxide layer 102, and then the exposed pad oxide layer 102 and the silicon substrate 100 are sequentially etched to define the trench 106 and the active area. 108, 109. Referring to FIG. 1B, a thermal oxidation step is performed to form a liner oxide layer U0 (Liner Oxide) along the exposed sand substrate surface in the same trench 106. 〇 Referring to FIG. 1C, a conformal layer is formed on the substrate 100. The silicon nitride layer 112 is, for example, a chemical vapor deposition method. Please refer to FIG. 1D, and then perform etch-back. For example, use anisotropic dry etching to remove the silicon nitride layer 112 (FIG. 1C) on the mask layer 102 and the silicon nitride layer 112 (FIG. 1C) at the bottom of the trench 106. (Figure), and a sidewall 112a made of silicon nitride is formed on the sidewall of the trench 106. _. Please refer to FIG. 1E to perform an oxidation method step, such as area oxidation, to oxidize the bottom of the trench 106 into a block-like irregular insulating layer 114. This insulating layer 114 is the subsequent isolation structure of the trench. In the lower part, due to the blocking by the insulating layer 114, after the subsequent manufacturing of the components, if the conduction between the components of the active area 108 and the components of the active area 109 is to be conducted, the current travel route is from the active area 108 to the silicon substrate 100. The medium bypassed the insulation layer 1M to reach the active area 109, which is longer than the current conduction path generated by the traditional trench without the irregular insulation layer 114. Therefore, this paper standard applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^ —-—.— f installed ------! Order ------- {Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4513 9¾ 50] 41 w I'.doc / 002 A7 B7 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Employee Consumer Cooperatives V. Invention Description (f) There will be no bridging between active areas 108 and 109. Referring to FIG. 1F, the spacer wall 112a (FIG. 1E) is removed, and an insulating layer 116 is formed on the cover layer 104. This insulating layer 116 also fills the trench 106. A common insulating layer material is an oxide. It is formed by using Atmospheric Pressure Chemical Vapor Deposition (APCVD). After the densification step, an insulating layer 116 having a relatively fine structure can be formed. Please refer to FIG. 1G. After compaction, a planarization process is performed. For example, chemical mechanical polishing (CMP) is used to remove the insulating layer 116 (FIG. IF) on the mask layer 104 and leave it. Insulating plug 116a in the trench area. Please refer to Figure 1H, and then remove the mask layer 104 (Figure 1G) and the pad oxide layer 102 (Figure IG), for example, using wet etching, and this step will simultaneously remove the surface portion of the insulating plug 116a and the insulation. The portion of the plug 116a near the surface of the active area completes the manufacture of the trench isolation structure. Subsequent other processes are performed to complete the components. It can be known from the above-mentioned preferred embodiments of the present invention that if the conduction between two adjacent active areas of the present invention is conventional, the current travel route is to bypass the insulating plug and the insulating plug in the trench from the silicon substrate. The irregular insulation layer below is much longer than the current conduction path generated by the traditional trench without this irregular insulation layer, so there is no bridging phenomenon between two adjacent active sections. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in this art will not depart from the essence of the present invention 7 (please read the precautions on the back before filling this page). ---- I! — Order ----
CY 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） A7 451 3 3¾ M.H 4lw i'.doc/〇〇2 ___B7______ 五、發明說明（& ) 神和範圍內，當可作各種之更動與潤飾’因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) '-.裝·-------訂------々CY This paper size applies to China National Standard (CNS) A4 specification (210 X 297 Gongchu) A7 451 3 3¾ MH 4lw i'.doc / 〇〇2 ___B7______ 5. Description of the invention (&) Make various changes and retouching 'Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. (Please read the precautions on the back before filling out this page) '-.install · ------- order ----------
經濟部智慧財產局員工消費合作社印M 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公爱^ " ~~ ---Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 public love ^ " ~~ ---