Λ513^5 6152twf.d〇c/008 A7 B7 經濟部智慧財產局員工消f合作社印數 4 五、發明說明（I ) 本發明是有關於一種半導體記憶體元件以及半導體記 憶體元件之製造方法，且特別是有關於一種高密度罩幕式 可程式唯讀記憶體以及利用自行對準金屬矽化物製程’以 製造高密度罩幕式可程式唯讀記憶體的方法 唯讀記憶體元件係一種半導體積體電路’而此半導體 積體電路廣泛應用於以微處理器爲主之系統中。此唯讀記 憶體元件係用來永久儲存資料，甚至在電源中斷時’資料 亦不被刪除β唯讀記憶體元件特別適合於許多需要相同資 料之元件或儲存需要重複使用的資料。其中一個應用範例 即爲個人電腦之基本輸入輸出系統。唯讀記憶體元件是以 主動元件之陣列方式來儲存二位元訊號，而在製造過程中 積體電路製造商係依顧客要求之規格來程序化此主動元件 之陣列。 傳統的罩幕式唯讀記憶體包括反或閘式與反及閘式。 反或閘式唯讀記憶體是將複數個記憶體電晶體之源極與汲 極，分別以平行的方式連接。然而反及閘式唯讀記憶體是 將複數個記憶體電晶體之源極與汲極，以串聯的方式連 接。 請參照第〗圖至第3圖，其所繪示爲習知一種平記憶 胞（flat-cell)之罩幕式唯讀記憶體之示意圖。首先提供 一具有P型摻質之半導體矽基底。埋入式位元線11係以 N型摻質植入具有複數個互相平行之細長條區域之基底中 而形成之，而此埋入式位元線U構成源極/汲極區域。其 次，在基底10上形成一層閘極氧化層〗2，而此閘極氧化 本紙張尺度適用中國钃家標準（CNS>A4现格（210 X 297公釐> --------------------^訂 j-------線'V (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 451325 A7 6152twf.doc/008 37 五、發明說明（>) 層12例如是以熱氧化法形成之氧化矽層。然後閘極π係 以垂直的方向橫跨在埋入式位元線11之上，而此閘極13 構成字元線，以用於罩幕式唯讀記憶體元件之記憶陣列 中。習知編碼之製程係在基底〗〇上覆蓋一層圖案化之光 阻層14，並暴露出複數個編碼區開口（coding openings) 15。然後在選擇之記憶胞所暴露出之通道區域中植入摻 質，藉以進行程式化步驟。 記憶胞電晶體之通道區域位於每二條相鄰位元線之間 且位於字元線之下的基底中。記憶胞電晶體是以阻斷 (blocking)或導通（conducting)的方式來編碼。「1」 或「〇」資料位元可視爲二種狀態之一。若以P型摻質植 入記憶胞，則記憶胞具有高的啓始電壓，而使得記憶胞永 遠處於「關」的狀態，例如爲存入二位元數字「〇」。若 未將摻質植入記憶胞，則記憶胞具有低的啓始電壓，而使 得記憶胞處於「開」的狀態，例如爲存入二位元數字「1」。 因此，當半導體元件製造廠商力求改進性能與降低成 本時，唯讀記憶體元件的尺寸越來越小，而唯讀記憶體元 件的密度也隨著越來越高。然而由於元件尺寸縮小，線寬 隨著減少，使得習知唯讀記憶體元件中之字元線與位元線 的電阻增高。因而不利於唯讀記憶體元件之操作速度。 解決上述問題的方法爲利用耐高溫之金屬矽化物薄膜 來降低字元線與位元線的電阻。相較於非金屬矽化物結 構，在自行對準金屬矽化物（SALICIDE)之製程中，形 成低阻値的源極接觸、閘極接觸以及汲極接觸，因而能降 5 本纸張尺度適用中a國家糅準<CNS>A4规格（210 * 297公釐） ------------ic-------h 訂---------線> (請先閲讀背面之注$項再填寫本頁) ；4 513 2 5 6152twf.doc/〇〇8 五、發明說明（A) 低位元線與字元線之電阻。然而自行對準金屬矽化物之製 程需要將額外的步驟倂入製程中。 在美國專利第5633187號專利案中，蘇揭露自行對準 金屬矽化物之製程’以降低唯讀記憶體中之位元線與字元 線的電阻。然而蘇所掲露之製程需要形成二層矽化金屬 層。蘇揭露在字元線上沉積一層矽化鎢層，然後在位元線 上沉積矽化鈦層° 在美國專利第51 212203號專利案中，蘇揭露另一種自 行對準金屬矽化物之製程，以降低唯讀記憶體中之位元線 的電阻。雖然此製程僅需形成一層金屬矽化層，但亦僅降 低了位元線之電阻。 根據上述，半導體業者需要提供一種自行對準金屬矽 化物之製程，使得此製程能容易地倂入唯讀記憶體元件之 製程中，並能同時降低位元線與字元線之電阻。 因此本發明提供一種罩幕式可程式唯讀記憶體之製造 方法，包括在半導體基底上形成一層厚度大於約1000埃 之氧化層β接著在此氧化層上形成一層第一罩幕層，且圖 案化此第一罩幕層，以形成位元線。其次去除位元線區域 之氧化層，以暴露出半導體基底。接著將導電摻質以離子 植入法摻入暴露出之基底，而形成埋入式位元線區域。然 後去除第一罩幕層，再形成第二罩幕層，隨後在第二罩幕 層上形成編碼圖案，以形成編碼區開口，而此編碼區開口 暴露出位元線之間的基底部分。接者去除第二罩幕層，並 在編碼區開口內形成一層閘極氧化層。隨後在餘留之氧化 (請先Η讀背面之注意事項再鱗寫本頁) --------訂!*! — ——線· 經濟部智慧財產局貝工消费合作杜印製 1 2 本紙張尺度適用中國圉家標準（CNS>A4規格（21〇 X 297公釐) 451325 A7 經濟部智慧財產局員工消费合作社印製 6152twf.d〇c/008 五、發明說明（4 ) 層、埋入式位元線區域以及閘極氧化層上沉積一層導電 層，以形成複數個導電閘極結構，而這些導電閘極結構構 成罩幕式唯讀記憶體之字元線。隨後在基底上沉積一層耐 高溫金屬，以在埋入式位元線與字元線上形成一層自行對 準矽化金屬層。 另一較佳實施例，本發明提供一種唯讀記憶體元件， 此唯讀記憶體元件包括複數個互相平行的位元線，其位於 基底中：複數個字元線，其垂直於上述複數個位元線上； 複數個記憶體胞，位於二相鄰位元線與部分字元線之交會 處。一層矽化金屬層覆蓋著二相鄰字元線之間的位元線部 分。 上述一般性描述與隨後之詳細描述僅作爲範例而加以 說明，以對本發明之申請專利範圍提供更進一步之說明。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉數個較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖所繪示爲習知一種唯讀記憶體之上視示意圖； 第2圖所繪示爲第1圖中沿π-ll線之製造流程剖面 圖： 第3圖所繪示爲第1圖中沿III-III線之剖面示意圖； 第4圖所繪示爲依照本發明之較佳實施例，一種罩幕 式唯讀記憶體的記憶胞之上視示意圖： 第5A圖所繪示爲第4圖中沿A-A線之剖面示意圖’ 7 本纸張尺度適用中B國家揉準<CNS>A4規格（21〇 x 297公爱） ------—--------1 —---'-訂 ----------. <請先閏讀背面之注意事項再磷寫本頁> 513 25 A7 6 152twf.doc/008 所 五、發明說明（t ) 其所繪示爲依照本發明在記憶胞區上形成一層厚氧化層與 形成位元線圖案之步驟。第5B圖所繪示爲第4圖中沿B-B線之剖面示意圖，可更說明此步驟； 第6A圖所繪示爲第4圖中沿A-A線之剖面示意圖， 其所繪示爲蝕刻位元線區上之氧化層，並植入N+摻質，以 形成埋入式位元線之步驟。第6B圖至第6D圖所繪示爲 第4圖中分別沿B-B線、C-C線以及D-D線之剖面示意圖， 可更說明此步驟： 第7A圖所繪示爲第4圖中沿A-A線之剖面示意圖， 其所繪示爲形成編碼區圖案與蝕刻編碼區內之氧化層的步 驟。第7B圖至第7D圖所繪示爲第4圖中分別沿B-B線、 C-C線以及D-D線之剖面示意圖，可更說明此步驟： 第8A圖所繪示爲第4圖中沿A-A線之剖面示意圖， 其所繪示爲形成閘極氧化層的步驟。第8B圖至第8D圖 所繪示爲第4圖中分別沿B-B線、C-C線以及D-D線之剖 面示意圖，可更說明此步驟； 第9A圖所繪示爲第4圖中沿A-A線之剖面示意圖， 其所繪示爲沉積且圖案化多晶矽閘極的步驟6第9B圖至 第9D圖所繪示爲第4圖中分別沿B-B線、C-C線以及D-D線之剖面示意圖，可更說明此步驟； 第10A圖所繪示爲第4圖中沿A-A線之剖面示意圖， 其所繪示爲形成間隙壁的步驟。第圖至第10D圖所 繪示爲第4圖中分別沿B-B線、C-C線以及D-D線之剖面 示意圖，可更說明此步驟；以及 8 本紙張尺度適用中困國家標準（CNS)A4規格（210 X 297公釐） {請先Μ讀背面之注意事項再填寫本頁) 訂· 線ο 經濟部智慧財產局員工消f合作社印裂 經濟部智慧財產局具工消费合作社印製 513 25 A7 6152twf.doc/008 „ _ _ — __U7 五、發明說明（& ) 第ΠΑ圖所繪示爲第4圖中沿A-A線之剖面示意圖， 其所繪示爲形成自行對準金屬矽化物層的步驟。第11B圖 至第11D圖所繪示爲第4圖中分別沿B-B線、C-C線以及 D-D線之剖面示意圖，可更說明此步驟。 圖式之標記說明： 10 :矽基底 11 :埋入式位元線 12 :閛極氧化層 13 :閘極 14 :光阻層 15 :編碼區開口 21 :厚氧化層： 23 : P型矽半導體基底 25 :第一光阻層 27 :細長條形開口 29 :位元線 31 :第二光阻層 33 :閘極氧化層 35 :多晶矽 37 :圖案化之厚氧化層 39 :編碼區之閘極氧化層 41 :編碼區開口 43 :間極 45 ·‘記憶胞 9 — — — — — — —--— — - ------^訂_!!線\3^ (請先"讀背面之注$項再填窝本頁) 本紙張尺度適用中國B家標準（CNS)A4规格（210 X 297公釐） Λα 51325 A7 6152twf.doc/008 五、發明說明（1 ) 47 :間隙壁 5】：矽化金屬層 實施例 請詳細參照本發明之實施例，並配合所附之圖式。 請參照第5A圖與第5B圖，在P型矽半導體基底23 上沉積一層厚度約至少1000埃之厚氧化層（TOX) 21。 厚氧化層之厚度約爲厚度約1〇〇埃之閘極氧化層之十倍。 若厚氧化層之厚度與閘極氧化層之厚度相差不大，則不易 區分被程式化爲「1」或「〇」之資料位元。形成厚氧化層 的方法’例如爲熱生長或習知低壓氣相沉積法。依上述方 法來形成厚氧化層，可避免橫向生長氧化層以及其後之 “鳥嘴”外觀的形成。例如，在整個記憶體區上生長氧化 層’因此“鳥嘴”僅生長在記憶體之邊緣。因此在記憶體 區場氧化層可避免有“鳥嘴”之外觀。相似地，形成連續 厚氧化層之方法，例如爲低壓化學氣相沉積法，可完全避 免“鳥嘴”外觀之形成。 經濟部智慧財產局貝工消费合作社印製 闓讀背面之注意事項再填寫本頁> 接者’在厚氧化層21上塗佈光阻25，隨後利用習知 微影製程圖案化光阻層25，以形成複數個互相平行的細長 條形開口 27 ’以定義位元線29，而此位元線可作爲記憶 胞電晶體之源極/汲極區。 接者，請參照第6A圖至第6D圖以及第7A圖至第7D 圖’進行蝕刻步驟，以去除在位元線區內之氧化層’並暴 露出氧化層下之基底。其較佳的方法包括習知非等向性触 刻法，例如爲反應性離子蝕刻法。然後以光阻層爲罩幕’ 本紙張尺度適用t Β Β家標準（CNS>A4规格—X 297公» ) j'451325 6152twf.doc/008 經濟部1r慧財產局貝工消费合作社印* 五、發明說明（p) 進行N+摻質之離子植入步驟，而此N+型摻質例如爲砷或 磷。砷摻質之植入能量大約爲60至120KeV，而所使用的 劑量約爲5 xlO14至5 xlO15 i〇nS/Cin2。磷摻質之植入能量 大約爲30至70KeV，而所使用的劑量約爲5E14至5E15 icms/cmh請參照第6A圖至第6C圖，以離子植入法在暴 露出之基底中形成N+區域29，以作爲唯讀記憶體元件之 埋入式位元線。 在去除第一光阻層之步驟後，形成圖案化之第二光阻 層31，並暴露出基底，而此暴露出之基底係作爲記憶胞之 通道區域。當字元線爲髙電壓時，電晶體是處於“開”的 狀態。利用微影製程，以在光阻層中定義出編碼區開口 41， 如第7A圖至第7D圖所示。編碼區開口可選擇性的暴露 出基底之表面，而於後續製程中在暴露出之基底上形成薄 閘極氧化層33。然後去除第二光阻層。去除第一與第二光 阻層之方法，例如爲使用習知之溶劑來去除光阻層。然後 利用習知之技術，以生長閘極氧化層，而其厚度由所使用 的製程來決定。請參照第8Α圖至第8D圖，其所繪示爲 形成閘極氧化層之剖面示意圖。請參照第8Α圖，由於摻 雜之矽層具有較快的氧化速率，而使得矽層具有較高的摻 質密度。因此在位元線Ν+之閘極氧化層的厚度高於在通道 上之閘極氧化層的厚度。 請參照第9Α圖至第9D圖，在餘留之厚氧化層上與 閘極氧化層上沉積一層毯覆式多晶矽層35，以形成字元線 結構β沉積多晶矽層之方法例如爲低壓化學氣相沉積法或 (請先《讀背面之注f項典填寫本頁> I n I n I ^1^.1 1Λ513 ^ 5 6152twf.d〇c / 008 A7 B7 Employees of the Intellectual Property Office of the Ministry of Economic Affairs, Cooperative Cooperative Press 4 V. Description of the Invention (I) The present invention relates to a semiconductor memory element and a method for manufacturing a semiconductor memory element. In particular, it relates to a high-density mask-type programmable read-only memory and a method for manufacturing a high-density mask-type programmable read-only memory by using a self-aligned metal silicide process. Integrated circuit 'And this semiconductor integrated circuit is widely used in microprocessor-based systems. This read-only memory element is used to store data permanently, and the data is not deleted even when the power is interrupted. The β read-only memory element is particularly suitable for many components that require the same data or to store data that needs to be reused. One application example is the basic input and output system of a personal computer. The read-only memory device stores the two-bit signals in an array of active devices. During the manufacturing process, the integrated circuit manufacturer programs the array of active devices according to the specifications required by the customer. Traditional mask-type read-only memory includes reverse OR gate and reverse gate. The NOR-gate read-only memory connects the source and drain of a plurality of memory transistors in parallel. However, the anti-gate read-only memory connects the source and drain of a plurality of memory transistors in series. Please refer to Fig. 3 to Fig. 3, which are schematic diagrams of a veil-type read-only memory of a flat-cell. First, a semiconductor silicon substrate with a P-type dopant is provided. The buried bit line 11 is formed by implanting an N-type dopant into a substrate having a plurality of elongated regions parallel to each other, and the buried bit line U constitutes a source / drain region. Secondly, a gate oxide layer is formed on the substrate 10, and the gate oxide paper size is in accordance with the Chinese standard (CNS > A4 now (210 X 297 mm >) -------- ------------ ^ Order j ------- line 'V (Please read the notes on the back before filling in this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 451325 A7 6152twf.doc / 008 37 V. Description of the invention The layer 12 is, for example, a silicon oxide layer formed by a thermal oxidation method. Then the gate π crosses the buried bit line 11 in a vertical direction. The gate 13 constitutes a word line for use in a memory array of a mask-type read-only memory device. The conventional coding process is covered with a patterned photoresist layer 14 on the substrate and exposed. A plurality of coding openings 15. A dopant is then implanted in the channel area exposed by the selected memory cell to perform the programming step. The channel area of the memory cell crystal is located on every two adjacent bit lines In the base between the word lines. The memory cell transistor is blocking or conducting The "1" or "0" data bit can be regarded as one of the two states. If the memory cell is implanted with a P-type dopant, the memory cell has a high starting voltage, so that the memory cell is always in the " The state of “off” is, for example, storing the two-digit number “0.” If the dopant is not implanted into the memory cell, the memory cell has a low starting voltage, and the memory cell is in the “on” state, for example, Store the two-digit number "1". Therefore, as semiconductor device manufacturers strive to improve performance and reduce costs, the size of read-only memory devices is getting smaller and smaller, and the density of read-only memory devices is increasing Higher. However, as the size of the device shrinks and the line width decreases, the resistance of the word line and bit line in the conventional read-only memory device increases. This is not conducive to the operation speed of the read-only memory device. The method of the problem is to reduce the resistance of the word line and the bit line by using a high temperature resistant metal silicide film. Compared with non-metal silicide structures, low resistance is formed in the process of self-aligning metal silicide (SALICIDE). value Source contact, gate contact, and drain contact, so it can be reduced by 5 paper standards Applicable to the standard of a country < CNS > A4 (210 * 297 mm) ----------- -ic ------- h order --------- line > (Please read the note on the back before filling in this page); 4 513 2 5 6152twf.doc / 〇〇8 5 Explanation of the invention (A) Resistance of low bit line and word line. However, the process of self-aligning metal silicide requires additional steps to be incorporated into the process. In US Patent No. 5,633,187, Su discloses self-alignment. The metal silicide process is used to reduce the resistance of bit lines and word lines in the read-only memory. However, the process of Su Sululu requires the formation of two silicided metal layers. Su Jielu deposits a tungsten silicide layer on the character lines, and then deposits a titanium silicide layer on the bit lines. In US Patent No. 51 212203, Su reveals another self-aligned metal silicide process to reduce read-only The resistance of the bit line in memory. Although this process only needs to form a metal silicide layer, it also only reduces the resistance of the bit line. According to the above, the semiconductor industry needs to provide a process for self-aligning metal silicide, so that the process can be easily incorporated into the process of the read-only memory device, and the resistance of the bit line and the word line can be reduced at the same time. Therefore, the present invention provides a method for manufacturing a mask-type programmable read-only memory, which includes forming an oxide layer β having a thickness greater than about 1000 angstroms on a semiconductor substrate, and then forming a first mask layer on the oxide layer, and the pattern is This first mask layer is formed to form bit lines. Next, the oxide layer in the bit line region is removed to expose the semiconductor substrate. A conductive dopant is then implanted into the exposed substrate by ion implantation to form a buried bit line region. Then, the first mask layer is removed, and then a second mask layer is formed, and then a coding pattern is formed on the second mask layer to form a coding region opening, and the coding region opening exposes a base portion between the bit lines. Then, the second mask layer is removed, and a gate oxide layer is formed in the opening of the coding area. Later in the remaining oxidation (please read the precautions on the back before writing this page) -------- Order! *! — ——Printed by the shellfish consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 2 This paper size is in accordance with Chinese standards (CNS > A4 specification (21〇X 297 mm) 451325 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6152twf.d〇c / 008 V. Description of the invention (4) layer A layer of conductive layer is deposited on the buried bit line area and the gate oxide layer to form a plurality of conductive gate structures, and these conductive gate structures form the word lines of the mask-type read-only memory. Then on the substrate A layer of high-temperature-resistant metal is deposited thereon to form a self-aligned silicide metal layer on the buried bit lines and word lines. In another preferred embodiment, the present invention provides a read-only memory element, which is a read-only memory The device includes a plurality of bit lines that are parallel to each other and are located in the base: a plurality of word lines that are perpendicular to the above plurality of bit lines; a plurality of memory cells that are located on two adjacent bit lines and part of the word lines Intersection. Covered by a layer of silicided metal The bit line portion between two adjacent word lines is described above. The above general description and the subsequent detailed description are only used as examples to provide a further explanation of the scope of the patent application of the present invention. And other purposes, features, and advantages can be more obvious and easy to understand, a few preferred embodiments are given below, in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: The first picture is shown as a custom Know the top view of a read-only memory; Figure 2 shows the cross-sectional view of the manufacturing process along line π-ll in Figure 1: Figure 3 shows the line along line III-III in Figure 1 Sectional schematic diagram; FIG. 4 illustrates a top view of a memory cell of a veil-type read-only memory according to a preferred embodiment of the present invention: FIG. 5A illustrates a line along AA in FIG. 4 Schematic diagram of the section '7 This paper size is applicable to the B country's standard < CNS > A4 (21〇x 297 public love) ---------------- 1 -----'- Order ----------. ≪ Please read the notes on the back before writing this page > 513 25 A7 6 152twf.doc / 008 (T) It shows the steps of forming a thick oxide layer and forming a bit line pattern on the memory cell area according to the present invention. FIG. 5B shows a schematic cross-sectional view along the BB line in FIG. Explain this step; Figure 6A is a schematic cross-sectional view taken along line AA in Figure 4, which is shown as etching the oxide layer on the bit line area and implanting N + dopants to form a buried bit The steps of the element line. Figures 6B to 6D show the schematic cross-sections along the BB, CC, and DD lines in Figure 4, which can further explain this step: Figure 7A is shown in Figure 4 A schematic cross-sectional view along the AA line in the middle shows the steps of forming the pattern of the coding region and etching the oxide layer in the coding region. Figures 7B to 7D are schematic cross-sectional views taken along lines BB, CC, and DD in Figure 4, respectively, which can further illustrate this step: Figure 8A is shown in Figure 4 along AA A schematic cross-sectional view showing the steps of forming a gate oxide layer. Figures 8B to 8D are schematic cross-sections along lines BB, CC, and DD in Figure 4, respectively, which can further illustrate this step; Figure 9A is shown in Figure 4 along AA. A schematic cross-sectional view, which is shown in step 6 of depositing and patterning a polysilicon gate. Figures 9B to 9D are shown in Figure 4 along the BB, CC, and DD lines, respectively. This step; FIG. 10A is a schematic cross-sectional view taken along line AA in FIG. 4, and it is illustrated as a step of forming a partition wall. Figures 10 to 10D are schematic cross-sectional views taken along lines BB, CC, and DD in Figure 4, respectively, to further illustrate this step; and 8 paper standards are applicable to the National Standard for Difficulties (CNS) A4 ( 210 X 297 mm) {Please read the notes on the back before filling out this page) Order · Line ο Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs f Cooperatives Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Industrial Workers Cooperatives 513 25 A7 6152twf .doc / 008 „_ _ — __U7 5. Description of the Invention (&) Figure ΠA shows the schematic cross-section along line AA in Figure 4, which shows the steps of forming a self-aligned metal silicide layer Figures 11B to 11D are schematic cross-sectional views taken along lines BB, CC, and DD in Figure 4, respectively, which can further illustrate this step. Marking description of the figure: 10: Silicon substrate 11: Embedded Bit line 12: Homopolar oxide layer 13: Gate 14: Photoresist layer 15: Coding area opening 21: Thick oxide layer: 23: P-type silicon semiconductor substrate 25: First photoresist layer 27: Slim strip opening 29: bit line 31: second photoresist layer 33: gate oxide layer 35: polycrystalline silicon 37: patterned Oxide layer 39: gate oxide layer 41 of the coding region: opening of the coding region 43: pole 45 · 'memory cell 9 — — — — — — — — — — — — ^ Order_ !! line \ 3 ^ (Please read the "$" on the back of the page before filling in this page) This paper size is applicable to China B family standard (CNS) A4 specification (210 X 297 mm) Λα 51325 A7 6152twf.doc / 008 V. Description of the invention (1) 47: Spacer wall 5]: For an example of a silicided metal layer, please refer to the embodiment of the present invention in detail, and cooperate with the accompanying drawings. Please refer to FIG. 5A and FIG. 5B on a P-type silicon semiconductor substrate A thick oxide layer (TOX) with a thickness of at least 1000 angstroms is deposited on 23. 21. The thickness of the thick oxide layer is about ten times that of the gate oxide layer with a thickness of about 100 angstroms. If the thickness of the thick oxide layer and the gate oxide are The thicknesses of the layers are not much different, so it is not easy to distinguish the data bits that are programmed as "1" or "0". The method of forming a thick oxide layer is, for example, thermal growth or a conventional low-pressure vapor deposition method. Forming a thick oxide layer as described above can prevent the lateral growth of the oxide layer and subsequent formation of a "bird's beak" appearance. For example, an oxide layer ' is grown over the entire memory region so the "bird's beak" grows only on the edges of the memory. Therefore, the field oxide layer in the memory region can avoid the appearance of a "bird's beak". Similarly, a method of forming a continuous thick oxide layer, such as a low pressure chemical vapor deposition method, can completely avoid the formation of a "bird's beak" appearance. Note on the back of the printed work of the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and then fill out this page > Receiver 'coat the photoresist 25 on the thick oxide layer 21, and then pattern the photoresist layer using the conventional lithography process 25 to form a plurality of parallel elongated strip-shaped openings 27 'to define a bit line 29, and this bit line can be used as a source / drain region of a memory cell transistor. Then, please refer to FIGS. 6A to 6D and FIGS. 7A to 7D to perform an etching step to remove the oxide layer in the bit line region and expose the substrate under the oxide layer. The preferred method includes a conventional anisotropic etching method, such as a reactive ion etching method. Then use the photoresist layer as the cover. This paper standard is applicable to the standard of Β Β (CNS > A4 size-X 297 male ») j'451325 6152twf.doc / 008 Printed by the Shell Industry Consumer Cooperative of the 1r Hui Property Bureau of the Ministry of Economic Affairs * 5 2. Description of the invention (p) An N + dopant ion implantation step is performed, and the N + type dopant is, for example, arsenic or phosphorus. The implantation energy of the arsenic dopant is approximately 60 to 120 KeV, and the dose used is approximately 5 x 1014 to 5 x 10 15 inS / Cin2. The implantation energy of the phosphorus dopant is about 30 to 70 KeV, and the dose used is about 5E14 to 5E15 icms / cmh. Please refer to Figures 6A to 6C. Ion implantation is used to form N + regions in the exposed substrate. 29. Use embedded bit lines as read-only memory elements. After the step of removing the first photoresist layer, a patterned second photoresist layer 31 is formed and the substrate is exposed, and the exposed substrate serves as a channel region of the memory cell. When the word line is at a high voltage, the transistor is in the "on" state. The photolithography process is used to define the coding region opening 41 in the photoresist layer, as shown in FIGS. 7A to 7D. The opening of the coding region can selectively expose the surface of the substrate, and a thin gate oxide layer 33 is formed on the exposed substrate in a subsequent process. The second photoresist layer is then removed. The method of removing the first and second photoresist layers is, for example, using a conventional solvent to remove the photoresist layer. The gate oxide layer is then grown using conventional techniques, and its thickness is determined by the process used. Please refer to FIGS. 8A to 8D, which are schematic cross-sectional views of forming a gate oxide layer. Please refer to Fig. 8A. Because the doped silicon layer has a faster oxidation rate, the silicon layer has a higher doping density. Therefore, the thickness of the gate oxide layer on the bit line N + is higher than the thickness of the gate oxide layer on the channel. Please refer to FIGS. 9A to 9D. A blanket polycrystalline silicon layer 35 is deposited on the remaining thick oxide layer and the gate oxide layer to form a character line structure. The method of depositing the polycrystalline silicon layer is, for example, a low-pressure chemical gas Facies deposition method or (please read "Note f on the back page to fill in this page"> I n I n I ^ 1 ^ .1 1
1— I 1· I 線丨 -ϋ - 本紙張尺度適用中國國家標準（CNS)A4规格<21〇 χ 297公釐） A7 451325 6152twf.doc/008 五、發明說明（1 ) 其他習知之方法，而沉積之厚度約爲2000埃至4000埃。 利用微影與蝕刻製程，以形成複數個閘極43，而此複數個 閘極電極43構成字元線，其中字元線用於罩幕式唯讀記 憶體元件之記憶體陣列中。 請參照第10A圖至第10D圖，形成間隙壁47，以保 護閘極側壁，避免在閘極側壁上形成矽化金屬層。首先沉 積一層絕緣層（圖中未示出），再進行非等向性蝕刻步驟， 以形成間隙壁47。絕緣層之材質，例如爲二氧化矽，其沉 積之厚度約爲1000埃至2000埃。然後對絕緣層進行回蝕 刻步驟，而回蝕刻法，例如爲反應性離子蝕刻法。 接者，請參照第11A圖至第11D圖，進行自行對準 金屬矽化物製程，一層薄的耐高溫金屬層，例如爲鈦，其 沉積之厚度約爲300埃置400埃。隨後在氮氣之環境下， 在溫度攝氏600度至900度之間進行熱處理製程。鈦與位 元線、多晶矽層直接接觸的部分，形成金屬矽化物51。以 鈦層爲例，形成矽化鈦（TiSi2)層。在其餘之區域，鈦與 其反應生成氮化鈦（TiN)或氮氧化鈦（TiOxNy)。然後 以熱硫酸溶液來進行選擇性蝕刻，熱硫酸溶液對未參與反 應的金屬鈦、氮化鈦（TiN)以及氮氧化鈦（ΉΟχΝγ)的 蝕刻速率快於矽化鈦（TiSi2)之蝕刻速率。利用上述自行 對準金屬矽化物製程，在唯讀記憶體之字元線上與部分埋 入式位元線上形成矽化金屬層51，而且僅需沉積一層耐高 溫之金屬層。 請參照第4圖與第11D圖，唯讀記憶體元件中之記憶 本紙張尺度適用中困國家標準（CNS)A4规格（210 X 297公釐） ------------------- ' 訂·！ _ _ 1 — — (請先W讀背面之注意事項再填寫本頁) 經濟部智慧財產局貝工消费合作社印製 A7 B7 451325 6152twf.d〇c/008 五、發明說明（（ϋ) 胞45位於字元線與二條相鄰位元線之交會處。由於在通 道區域上形成有圖案化之厚氧化層37，因此關閉狀態之記 憶胞具有高的啓始電壓。不論字元線電壓高或低，記憶胞 一直維持在關閉狀態。然而具有編碼區開口之記憶胞，由 於編碼區開口內之閘極氧化層39具有正常厚度（normal thickness)，當字元線處於高電壓狀態時，具有正常厚度 之閘極氧化層的記憶胞能設定在導通的狀態。依照本發明 之原則，唯讀記憶體元件在字元線與部分位元線上形成有 矽化金屬層。由於只需單一步驟來沉積矽化金屬層，因此 可容易地將此沉積步驟倂入製程中》而矽化金屬層能降低 字元線與位元線之電阻，以致能加快記憶胞的操作速度。 雖然本發明已以較佳實施例掲露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可在唯讀記憶體元件之製造方法中作各種之 更動與潤飾，因此本發明之保護範圍當視後附之申請專利 範圍所界定者爲準。 ------------------- l·訂 --------線·) (諳先閲讀背面之注f項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 本紙張尺度適用中a Β家#準（CNSJA4规格<210 X 297公釐）1— I 1 · I Line 丨 -ϋ-This paper size applies to China National Standard (CNS) A4 specifications < 21〇χ 297 mm) A7 451325 6152twf.doc / 008 5. Description of the invention (1) Other conventional methods And the thickness of the deposit is about 2000 Angstroms to 4000 Angstroms. The lithography and etching processes are used to form a plurality of gate electrodes 43, and the plurality of gate electrodes 43 constitute word lines, wherein the word lines are used in a memory array of a mask-type read-only memory device. Referring to FIG. 10A to FIG. 10D, a gap wall 47 is formed to protect the gate sidewall and prevent the formation of a silicide metal layer on the gate sidewall. An insulating layer (not shown) is deposited first, and then an anisotropic etching step is performed to form the spacer 47. The material of the insulating layer is, for example, silicon dioxide, and the deposited thickness thereof is about 1000 angstroms to 2000 angstroms. Then, the insulating layer is subjected to an etch-back etching step, and the etch-back method is, for example, a reactive ion etching method. Then, please refer to FIGS. 11A to 11D for the self-aligned metal silicide process. A thin, high-temperature-resistant metal layer, such as titanium, is deposited at a thickness of about 300 angstroms and 400 angstroms. The heat treatment process is then performed in a nitrogen atmosphere at a temperature between 600 ° C and 900 ° C. The portion where titanium directly contacts the bit line and the polycrystalline silicon layer forms metal silicide 51. Taking the titanium layer as an example, a titanium silicide (TiSi2) layer is formed. In the remaining areas, titanium reacts with it to form titanium nitride (TiN) or titanium oxynitride (TiOxNy). Then, the hot sulfuric acid solution is used for selective etching. The hot sulfuric acid solution etches the metal titanium, titanium nitride (TiN) and titanium oxynitride (Ήχχγ) which are not involved in the reaction faster than the titanium silicide (TiSi2). Using the self-aligned metal silicide process described above, a silicided metal layer 51 is formed on the word lines of the read-only memory and part of the embedded bit lines, and only a high temperature resistant metal layer needs to be deposited. Please refer to Figure 4 and Figure 11D. The paper size of the read-only memory element is applicable to the National Standard (CNS) A4 specification (210 X 297 mm). ------------ ------- 'Order! _ _ 1 — — (Please read the precautions on the back before filling out this page) Printed by the Shellfish Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 451325 6152twf.d〇c / 008 5. Description of the invention ((（) Cell 45 It is located at the intersection of the word line and two adjacent bit lines. Because the patterned thick oxide layer 37 is formed on the channel area, the memory cell in the closed state has a high starting voltage. Whether the word line voltage is high or Low, the memory cell has been kept closed. However, the memory cell with the coding region opening, because the gate oxide layer 39 in the coding region opening has a normal thickness, when the word line is in a high voltage state, it has normal The thickness of the memory cell of the gate oxide layer can be set to a conducting state. According to the principle of the present invention, the read-only memory element has a silicide metal layer formed on the word lines and some bit lines. Since only a single step is required to deposit silicide Metal layer, so this deposition step can be easily incorporated into the manufacturing process "while the silicided metal layer can reduce the resistance of word lines and bit lines, so as to speed up the operation of memory cells. The present invention has been disclosed as above with preferred embodiments, but it is not intended to limit the present invention. Any person skilled in the art can be used in the manufacturing method of a read-only memory element without departing from the spirit and scope of the present invention. Various modifications and retouchings are made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. ------------------- l · 定- ------- line ·) (谙 Please read the note f on the back before filling out this page) Member of the Intellectual Property Bureau of the Ministry of Economic AffairsΗConsumer Co-operative Society Printed this paper Standard Applicable a Β 家 # 准 （CNSJA4Specifications < 210 X 297 mm)