451319 五、發明說明（1) 本發明係有關於一種半導體積體電路（integrated circuits ;ICs)製程技術’特別是有關於一種自我對準金 屬石夕化物（self-aligned metal silicide，簡稱metal sal icide)的製造方法，能夠有效地降低0. 18微米以下設 計尺寸之源極/汲極（source/drain)，亦即窄幅（narrow width)N + 0D 或P + 0D 的片阻值（sheet resistance)。 以下利用第1A〜第1C圖所示在金氧半電晶體（metai oxide semiconductor transistor ； MOS transistor)^ 成自我對準金屬矽化物的製程剖面圖，以說明習知技術。 上述習知技術的源極/汲極設計寬度大約小於2痠。 首先，請參照第1A囫，該圖之符號1〇表示矽基底，而 梦基底表面形成有複晶妙閘極13 '與源極/ί及極12，此源 極/汲極12亦即熟習該技藝者所稱之窄幅「N + 0D」區域。 另外，符號11表示閘極氧化層，而符號14表示間隙壁 (spacer) β 其次’請參照第1Β圖，利用濺鍍方式全面性地形成鈦 金屬層15，其覆蓋於上述複晶矽閘極13與上述源極/汲極 12表面。接著’為了更進一步地降低阻值，最好利用矽離 子混合植入方式（silicon ion mixing implantation)在 上述複晶石夕閘極13與源極/¾極12的表面摻入石夕，藉由此 步驟可增加額外的矽而促進後續鈦與矽的反應。 然後’請參照第1C圖，在800〜1000 t的溫度下，進 行第1 次快速熱製程（rapid thermal processing ;RTP)， 使鈦與矽反應’而形成一自我對準鈦金屬矽化物 第4頁 45131 a 五、發明說明（2) 17(TiSi2)。 然而’隨著電路積集度的增加，閘極與源極/汲極的 尺寸曰益縮小’以習知技術形成自我對準矽化物後的窄幅 N + OD的片電阻仍然高達19. 7 ohm/cV。 有鐘於此’本發明的目的在於提供一種自我對準金屬 矽化物的製造方法’能夠更進一步地降低窄幅N + 〇D的片電 阻’而符合元件尺寸漸縮的需求β 根據上述目的’本發明提供一種自我對準金屬矽化物 的製造方法，包括下列步驟：（a)提供一矽基底，該矽基 底表面形成有一複晶矽閘極與一源極/汲極；（b)形成一鈦 金屬層，以覆蓋該複晶矽閘極與該源極/汲極表面；（c)在 上述鈦金屬層表面形成一氮化鈦（TiN)層；（d)施行熱製 程’以在該複晶矽閘極與該源極/汲極表面形成一鈦金屬 <6夕化物。 本發明之製造方法藉由增加一道形成氮化鈦層的步 驟’能夠更進一步降低窄幅N + 〇D的片電阻。 再者’上述自我對準金屬矽化物的製造方法，其中該 複晶矽閘極可摻有p型離子或是N型離子。 接著’上述自我對準金屬矽化物的製造方法，其中該 源極/汲極可由該矽基底表面的N或p型離子摻雜區域構人 成。 其次’上述自我對準金屬矽化物的製造方法，其中步 驟（b)可利用濺鍍法形成該鈦金屬層。而步驟（〇)可利用化 學氣相沈積法形成該氮化鈦層。451319 V. Description of the invention (1) The present invention relates to a semiconductor integrated circuit (ICs) process technology, particularly to a self-aligned metal silicide (metal salicide) ) Manufacturing method, which can effectively reduce the source / drain of the design size below 0. 18 microns, that is, the sheet resistance of narrow width N + 0D or P + 0D (sheet resistance ). In the following, a cross-sectional view of a process for forming a self-aligned metal silicide in a metal oxide semiconductor (MOS transistor) ^ shown in FIGS. 1A to 1C is used to explain the conventional technology. The source / drain design widths of the above-mentioned conventional techniques are less than about 2 acids. First, please refer to Section 1A 囫. The symbol 10 in the figure represents a silicon substrate, and the surface of the dream substrate is formed with a complex crystal gate 13 ′ and a source electrode 12 and the source electrode 12. This source / drain electrode 12 is familiar. What the artist calls a narrow "N + 0D" area. In addition, reference numeral 11 indicates a gate oxide layer, and reference numeral 14 indicates a spacer β. Next, please refer to FIG. 1B, and comprehensively form a titanium metal layer 15 by sputtering, which covers the above-mentioned polycrystalline silicon gate electrode. 13 and the source / drain 12 surface described above. Then, in order to further reduce the resistance value, it is best to use silicon ion mixing implantation to inject the stone Xi on the surface of the polycrystalline stone gate 13 and the source / ¾ electrode 12 by This step can add additional silicon to promote subsequent reaction between titanium and silicon. Then 'refer to Figure 1C, perform the first rapid thermal processing (RTP) at a temperature of 800 ~ 1000 t to react titanium with silicon' to form a self-aligned titanium metal silicide. Page 45131 a V. Description of the invention (2) 17 (TiSi2). However, as the circuit accumulation increases, the size of the gate and source / drain electrodes shrinks, and the sheet resistance of the narrow N + OD after the self-aligned silicide is formed by conventional techniques is still as high as 19.7. ohm / cV. It is here that the purpose of the present invention is to provide a method for manufacturing a self-aligned metal silicide, which can further reduce the chip resistance of a narrow N + OD, and meet the demand for a gradual reduction in device size. Β According to the above purpose. The invention provides a method for manufacturing a self-aligned metal silicide, which includes the following steps: (a) providing a silicon substrate, the surface of the silicon substrate is formed with a polycrystalline silicon gate and a source / drain; (b) forming a A titanium metal layer to cover the surface of the polycrystalline silicon gate and the source / drain; (c) forming a titanium nitride (TiN) layer on the surface of the titanium metal layer; (d) performing a thermal process to The polycrystalline silicon gate and the source / drain surface form a titanium metal oxide. The manufacturing method of the present invention can further reduce the sheet resistance of the narrow N + 0D by adding a step of forming a titanium nitride layer '. Furthermore, the method for manufacturing a self-aligned metal silicide as described above, wherein the polycrystalline silicon gate may be doped with p-type ions or N-type ions. Then, the method of manufacturing a self-aligned metal silicide as described above, wherein the source / drain can be composed of N or p-type ion doped regions on the surface of the silicon substrate. Next, the method of manufacturing a self-aligned metal silicide as described above, wherein the step (b) can form the titanium metal layer by a sputtering method. In step (0), the titanium nitride layer can be formed by a chemical vapor deposition method.
第5頁 * 4513 19 五、發明說明¢3) 再者，上述自我對準金屬矽化物的製造方法，其中步 驟（d)形成該鈦金屬矽化物最好更包括下列步驟施行 第1次快速熱製程’使欽與矽反應，而形成一鈦金屬矽化 物’該鈦金屬矽化物具有第1相；（ii)去除未參予反應的 欽金屬層；（iii)施行第2次快速熱製程，以達到該鈦金屬 矽化物相轉移，而成為第2相。 再者’上述自我對準金屬矽化物的製造方法，其中步 驟（a)與（b)之間最好更包括一利用例如稀釋氫氟酸進行的 氧化物清除步驟。 再者’上述自我對準金屬矽化物的製造方法，其中步 驟（d)之前最好更包括下列步驟：利用矽離子混合植入方 式在該複晶矽閘極與該源極/汲極表面摻入矽。 為了讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第1A〜第1C圖係習知技術之自我對準金屬矽化物的製 程剖面圖。 第2A〜第2C圈係根據本發明較佳實施例之自我對準金 屬矽化物的製程剖面圖。 符號之說明 1 0、1 0 0〜單晶矽基底；11、11 〇〜閘極氧化層； 12、120〜源極/汲極；u、130 -複晶矽閘極；14、140〜間 隙壁（spacer ) ;15、150〜鈦金屬層；160〜氮化鈦層；Page 5 * 4513 19 V. Description of the invention ¢ 3) Furthermore, in the method for manufacturing the self-aligned metal silicide described above, the step (d) forming the titanium metal silicide preferably further includes the following steps for the first rapid heating The process 'makes Chin react with silicon to form a titanium metal silicide'. The titanium metal silicide has a first phase; (ii) removes the uninvolved Chin metal layer; (iii) performs the second rapid thermal process, In order to achieve the titanium metal silicide phase transition, it becomes the second phase. Furthermore, the method for producing a self-aligned metal silicide as described above, wherein steps (a) and (b) preferably further include an oxide removing step using, for example, dilute hydrofluoric acid. Furthermore, the above-mentioned method for manufacturing self-aligned metal silicide, wherein before step (d), it is preferable to further include the following steps: doping the complex silicon gate with the source / drain surface by a silicon ion hybrid implantation method Into silicon. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: 1A to 1C The figure is a cross-sectional view of a conventional self-aligned metal silicide process. Circles 2A to 2C are cross-sectional views of a self-aligned metal silicide process according to a preferred embodiment of the present invention. Explanation of symbols 10, 1 0 ~ single crystal silicon substrate; 11, 11 0 ~ gate oxide layer; 12, 120 ~ source / drain; u, 130-compound silicon gate; 14, 140 ~ gap Wall (spacer); 15, 150 ~ titanium metal layer; 160 ~ titanium nitride layer;
451319 五、發明說明（4) 17、170~自我對準鈦金屬矽化物層。 實施例 以下利用第2人~第2(：圖所示在金氧半電晶體（M0S transistor)形成自我對準金屬矽化物的製程剖面圖，以 說明本發明較佳實施例。 首先’請參照第2A圖’該圖之符號1〇〇表示單晶矽基 底，而矽基底表面形成有摻入離子的複晶矽閘極13〇、與p 型或N型離子摻雜區域構成的源極/汲極12〇，此源極/汲極 120亦即熟習該技藝者所稱之「n + 〇d」區域。另外，符號 110表示閘極氧化層，而符號14〇表示例如二氧化矽（Si〇2) 或氮化矽（SiaN4)材料構成的間隙壁（spacer) ««為了確保後 續金屬梦化物能夠反應’最好利用稀釋氫氟酸進行氧化物 的清除步驟，以去除形成於上述複晶矽閘極13〇與源極/汲 極120表面的原始氧化層（natiVe 〇xide圖未顯示）。 其次’請參照第2 B圖，利用濺鍍方式全面性地形成厚 度約為200〜500埃的鈦金屬層15〇 ’其覆蓋於上述複晶矽閘 極130與上述源極/汲極120表面。再以化學氣相沈積法等 (chemical vapor deposition ;CVD)方式形成厚度約為 500〜1 000埃的氮化鈦層（TiN)160，當然，形成氮化鈦層的 方式不限於CVD的方式，亦可在氮氣（n2)或氨氣（Nh3)的存 在下利用氮化反應（Nitri da ti on)與鈦金屬層150反應而形 成氮化鈦160。接著，為了更進一步地降低阻值，最好利 用碎離子混合植入方式（silicon ion mixing implantation)在上述複晶矽閘極1 30與源極/汲極120的表451319 V. Description of the invention (4) 17, 170 ~ Self-aligned titanium silicide layer. EXAMPLES The following section uses a second person to a second (:) process cross-sectional view of forming a self-aligned metal silicide on a MOS transistor to illustrate a preferred embodiment of the present invention. First, 'Please refer to FIG. 2A 'The symbol 100 in this figure indicates a single crystal silicon substrate, and a surface of the silicon substrate is formed with a doped polycrystalline silicon gate 13 and a source electrode formed with a p-type or N-type ion doped region / The drain / drain 120 is the "n + 0d" area known to those skilled in the art. In addition, the symbol 110 indicates the gate oxide layer, and the symbol 14 indicates, for example, silicon dioxide (Si 〇2) or a spacer made of silicon nitride (SiaN4) material «« In order to ensure that subsequent metal dreams can react 'it is best to use diluted hydrofluoric acid to remove the oxide in order to remove the complex crystals formed above The original oxide layer on the surface of the silicon gate 13 and the source / drain 120 (not shown in the natiVe oxide diagram). Secondly, please refer to FIG. 2B to form a comprehensive thickness of about 200 to 500 angstroms by sputtering. 15 'of titanium metal layer which covers the above-mentioned polycrystalline silicon gate 130 and The source / drain 120 surface is described. Then, a titanium nitride layer (TiN) 160 having a thickness of about 500 to 1,000 angstroms is formed by chemical vapor deposition (CVD), and of course, titanium nitride is formed. The method of the layer is not limited to the CVD method, and titanium nitride 160 may be formed by reacting with the titanium metal layer 150 by a nitriding reaction (Nitri da ti on) in the presence of nitrogen (n2) or ammonia (Nh3). Then, In order to further reduce the resistance value, it is better to use the silicon ion mixing implantation method on the above-mentioned table of the polycrystalline silicon gate 130 and the source / drain 120.
第7頁 451319 玉、發明說明（5) 面摻入矽，藉由此步驟可增加額外的矽而促進後續鈦與矽 的反應。 然後，請參照第2C圖，在800〜1000 °C的溫度下’進 行第1 次快速熱製程（rapid thermal processing ;RTP)， 使欽與碎反應’而形成一自我對準欽金屬碎化物 l70(TiSi2)，上述鈦金屬矽化物具有第1相（phase 1 ) ’然 後例如利用濕蝕刻的方式去除未參予反應的鈦金屬層，接 著，進行第2次快速熱製程，以達到鈦金屬矽化物相轉移 (phase transfer)，而成為第2相（phase 2)，在此相轉移 的目的在於降低自我對準矽化物的阻值。 本實施例如以鈦金屬層為例，另外，钽、鈷、鉑、鎢 金屬廣亦可取代欽金屬層。 發明特徵與效果 本發明的特徵之一在於，在鈦金屬層150表面形成氮 化鈦層160，再配合矽離子混合植入法與熱製程以形成自 我對準鈦金屬矽化物。 根據本發明的製造方法，能夠大幅地降低窄幅N + 0D的 片電阻至8. 9ohm/cm2，而符合半導體元件漸縮的需求。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。Page 7 451319 Jade and description of invention (5) The surface is doped with silicon. By this step, additional silicon can be added to promote the subsequent reaction between titanium and silicon. Then, referring to Figure 2C, at the temperature of 800 ~ 1000 ° C, 'the first rapid thermal processing (RTP) is performed, so that the reaction between Chin and fragmentation' forms a self-aligned Chin metal fragment l70 (TiSi2), the titanium metal silicide has a first phase (phase 1) ', and then, for example, wet etching is used to remove the unreacted titanium metal layer, and then a second rapid thermal process is performed to achieve titanium metal silicidation. The phase transfer (phase transfer) becomes the second phase (phase 2). The purpose of the phase transfer here is to reduce the resistance of the self-aligned silicide. In this embodiment, a titanium metal layer is taken as an example. In addition, tantalum, cobalt, platinum, and tungsten metal can also replace the metal layer. Features and Effects of the Invention One of the features of the present invention is that a titanium nitride layer 160 is formed on the surface of the titanium metal layer 150, which is then combined with a silicon ion hybrid implantation method and a thermal process to form a self-aligned titanium metal silicide. According to the manufacturing method of the present invention, the sheet resistance of the narrow N + 0D can be greatly reduced to 8.9 ohm / cm2, which meets the demand for shrinking semiconductor devices. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.