TW449891B - IC vacuum capping process - Google Patents

IC vacuum capping process Download PDF

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Publication number
TW449891B
TW449891B TW89110312A TW89110312A TW449891B TW 449891 B TW449891 B TW 449891B TW 89110312 A TW89110312 A TW 89110312A TW 89110312 A TW89110312 A TW 89110312A TW 449891 B TW449891 B TW 449891B
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TW
Taiwan
Prior art keywords
substrate
vacuum
castle
capping process
glue
Prior art date
Application number
TW89110312A
Other languages
Chinese (zh)
Inventor
Jian-Cheng Huang
Original Assignee
Pan Pacific Semiconductor Co L
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Pan Pacific Semiconductor Co L filed Critical Pan Pacific Semiconductor Co L
Priority to TW89110312A priority Critical patent/TW449891B/en
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Publication of TW449891B publication Critical patent/TW449891B/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

An IC vacuum capping process comprises the following steps: (1) preparing a transparent upper cap; (2) preparing a substrate in which the substrate has castles on the periphery and configuring the ICs on the substrate, wire bonding, spraying UV glue on the castles and configuring the transparent caps on the castles with UV glue at the periphery of the substrate; (3) allocating said resulting structure in a vacuum environment; (4) applying UV lamp irradiation to solidify the UV glue so that the transparent upper cap can be fixed on the castle. The process can speed up the IC capping process and increase the production yield.

Description

• 44989 1 五、發明說明(1) 本發明係有關於一種I C製程,尤其是有關於一種I c真 空封蓋製程’可以加快I C封蓋製程,並且提高良率。 參見第一圖,為一種習知之1C封裝製程,其中封裝的1C為 一種CMOS影像感測器IC1 1 0。參見此圖,此習知之CM〇s$ 像感測器I C 1 1 0封裝製程包含下列步驟:(1)置備一透明 上蓋(B-stage玻璃)2 0 0; (2)置備一基板100,此基板 1 0 0四周具有城堡1 0 2,將CMOS影像感測器I C 11 0安置在此 基板10 0上的晶片座(未圖示)上,打上接線104,在透明 上蓋2 0 0下側塗上封膠2 0 2,將此帶有封膠2 0 2之透明上蓋 2 0 0安置在基板1 0 0四周的城堡1 〇 2上;(3 )用夾具3 0 0將此 帶有透明上蓋2 0 0之CMOS影像感測器1C封裝夾住;(4)置於 烤箱40 0内烘烤2-3小時》 然而在上述製程具有下列缺點 (1 )由於係對於單顆CMOS影像感測器I 0進行封裝,製 程控制不易,且產能不高,亦難以自動化。 (2) 對於B-stage玻璃之透明上蓋2〇〇而§ ,塗膠品 質難以控制,製程複雜且人工放置玻璃,有極大偏差。 (3) 使用夹子30 2夾住封蓋,失子容易刮傷玻璃表 面。 (4) 烤箱烘烤需要2 -3小時,耗時甚久,生產速度緩 慢,且溫度分布不均,承受環境衝擊低。 因此本發明之目的即在提供一種可以改善習知缺點之 I C真空封蓋製程,以加快IC封蓋製程,並且提高良率。 為達成上述目的,本發明之1C真空封蓋製程包含下列• 44989 1 V. Description of the invention (1) The present invention relates to an I C process, and particularly to an I c vacuum capping process, which can speed up the I C capping process and improve the yield. Referring to the first figure, it is a conventional 1C packaging process, wherein the packaged 1C is a CMOS image sensor IC1 1 0. Referring to this figure, the conventional CMOS image sensor IC 1 10 packaging process includes the following steps: (1) provision of a transparent cover (B-stage glass) 2 0; (2) provision of a substrate 100, This substrate 100 has castles 102 around it. A CMOS image sensor IC 110 is placed on a wafer holder (not shown) on this substrate 100. The wiring 104 is attached, and the transparent upper cover 200 is on the lower side. Apply sealant 2 0 2 and place this transparent cover 2 with sealant 2 0 2 on the castle 1 0 2 around the substrate 1 0 0; (3) use a clamp 3 0 0 to make this transparent The CMOS image sensor 1C of the cover 200 is clamped; (4) It is baked in the oven 400 for 2-3 hours. However, the above process has the following disadvantages (1) because it is for a single CMOS image sensor The device I 0 is packaged, the process control is not easy, the production capacity is not high, and it is difficult to automate. (2) As for the transparent top cover of B-stage glass, §2, the coating quality is difficult to control, the manufacturing process is complicated and the glass is placed manually, which has great deviation. (3) Use the clip 30 2 to clamp the cover, and the lost surface can easily scratch the glass surface. (4) Oven baking takes 2-3 hours, which takes a long time, slow production speed, uneven temperature distribution, and low environmental impact. Therefore, the purpose of the present invention is to provide an IC vacuum capping process which can improve the conventional disadvantages, so as to speed up the IC capping process and improve the yield. To achieve the above object, the 1C vacuum capping process of the present invention includes the following

Λ 49 89 1 五、發明說明(2) 步驟 (1 )置備一透明上蓋; (2 )置備一基板,此基板四周具有城堡,將I C安置 在此基板上,打上接線,在城堡上側塗上UV膠,將此透明 上蓋安置在基板四周的具有UV膠的城堡上; (3 )將上述所得結構置於一真空環境中; (4)使用紫外光燈照射,使UV膠固化,因此透明上蓋 可以固定在城堡上。 為使本發明之精神及目的使人更清楚了解,茲舉附圖 並配合實例說明本發明。 【較佳具體實例詳細說明】 參見第二圖為本發明1C真空封裝製程之流程圖。本發 明之製程包含下列步驟: (1) 置備一透明上蓋(B-stage破璃)200; (2) 置備一基板100,此基板10 0四周具有城堡102, 將CMOS影像感測器I C 1 1 0安置在此基板1 0 0上的晶片座 (未圖示)上,打上接線1 0 4,在城堡1 0 2上側塗上UV膠 2 0 4,將此透明上蓋2 0 0安置在基板1 0 0四周的具有UV膠 2 0 4的城堡1 0 2上; (3) 將上述所得結果置於一真空環境中; (4 )使用紫外光燈5 0 0照射,使U V膠 2 0 4固化,因此 透明上蓋2 0 0可以固定在城堡1 0 2上。 如上所述,本發明之I C真空封蓋製程具有下列優點 (1 )由於不須使用夾具夾住,可以將陣列形式之基板Λ 49 89 1 V. Description of the invention (2) Step (1) Prepare a transparent cover; (2) Prepare a substrate with a castle around it. Place the IC on this substrate, wire it, and apply UV to the upper side of the castle. This transparent upper cover is placed on the castle with UV glue around the substrate; (3) the structure obtained above is placed in a vacuum environment; (4) the UV glue is cured by irradiation with an ultraviolet light, so the transparent upper cover can Fixed on the castle. In order to make the spirit and purpose of the present invention clearer, the accompanying drawings and examples are used to explain the present invention. [Detailed description of a preferred specific example] Refer to the second figure for a flowchart of the 1C vacuum packaging process of the present invention. The manufacturing process of the present invention includes the following steps: (1) preparing a transparent top cover (B-stage breaking glass) 200; (2) preparing a substrate 100 having a castle 102 around the substrate 100, and placing a CMOS image sensor IC 1 1 0 is placed on a wafer holder (not shown) on the substrate 1 0 0, wiring 1 0 4 is applied, and UV adhesive 2 0 4 is coated on the upper side of the castle 1 0 2, and this transparent cover 2 0 0 is placed on the substrate 1 On the castle 1 0 2 with UV glue 2 0 4 around 0 0; (3) Put the result obtained above in a vacuum environment; (4) Use UV lamp 5 0 to irradiate to cure the UV glue 2 0 4 Therefore, the transparent upper cover 200 can be fixed on the castle 102. As mentioned above, the IC vacuum capping process of the present invention has the following advantages (1) Since it is not necessary to use a clamp to clamp, the substrate in the form of an array can be

厶 4989 1 五、發明說明(3) 1 0 0配合多數CMOS影像感測器I C 11 0進行封裝,可以自動 化生產,製程容易控制; (2 ) U V膠塗在城堡上方,塗膠較易控制,塗膠容易且 不須排氣孔,且可用機台模具自動放置玻璃,誤差小。 (3) 在真空環境裡先抽真空再封蓋,且可使用橡皮軟 墊吸取玻璃,因此玻璃表面不會被刮傷,且可使用真空壓 差固定玻璃。 (4) 使用紫外光照射,能量均勻且只需數秒即可固化 UV膠,製程迅速。 綜上所述,藉由本發明"IC真空封蓋製程11,可以加快 1C封蓋製程,並且提高良率,乃一不可多得之發明,爰依 法提出申請之,請詳查並准于本案專利,以保障該發明者 之權益,若鈞局貴審查委員有任何稽疑,請不吝來函指 示0厶 4989 1 V. Description of the invention (3) 1 0 0 is packaged with most CMOS image sensor IC 110, which can be automated production and easy to control the process; (2) UV glue is applied on the castle, which is easier to control. It is easy to apply glue and does not require air vents, and the glass can be automatically placed by the machine mold, and the error is small. (3) Vacuum in a vacuum environment before closing, and the glass can be sucked with a rubber pad, so the glass surface will not be scratched, and the glass can be fixed with a vacuum pressure difference. (4) Use UV light to irradiate UV glue with uniform energy and curing in a few seconds. The process is fast. In summary, with the present invention " IC vacuum capping process 11, the 1C capping process can be accelerated, and the yield rate can be improved. It is a rare invention. An application was filed according to law. Please check and approve this case in detail. Patent to protect the rights and interests of the inventor

44989 1 圖式簡單說明 圖式說明: 第一圖為習知I C封裝製程之流程圖; 第二圊為本發明I c真空封裝製程之流程圖。 圖號說明: 1 0 0基板 1 0 2城堡 1 0 4接線44989 1 Brief description of the diagrams Description of the diagrams: The first diagram is a flowchart of the conventional IC packaging process; the second is the flowchart of the I c vacuum packaging process of the present invention. Drawing number description: 1 0 0 substrate 1 0 2 castle 1 0 4 wiring

1 10 CMOS影像感測器1C 2 0 0透明上蓋 2 0 2封膠 2 04 vm 3 0 0夾具 3 0 2夾子 4 0 0烤箱 5 0 0紫外光燈1 10 CMOS image sensor 1C 2 0 0 Transparent cover 2 0 2 Sealant 2 04 vm 3 0 0 Fixture 3 0 2 Clip 4 0 0 Oven 5 0 0 UV light

Claims (1)

六、申請專利範圍 L.. 一種I C真空封蓋製程,包含下列步驟: (1 )置備一透明上蓋; (2)置備一基板,此基板四周具有城堡,將1C安置 在此基板上,打上接線,在城堡上側塗上UV膠,將此透明 上蓋安置在基板四周的具有UV勝的城堡上; (3 )將上述所得結構置於一真空環境中; (4)使用紫外光燈照射,使UV膠固化,因此透明上蓋 可以固定在城堡上。 2. 如申請專利範圍第一項之1C真空封蓋製程,其中 基板為陣列型基板以封裝多數I C,且透明上蓋亦可涵蓋此 多數1C,在於封蓋後進行切割作業,切成單獨1C。 3. 如申請專利範圍第一項之1C真空封蓋製程,其中 1C為CMOS影像感測器1C。 .4·如申請專利範圍第一項之1C真空封蓋製程,其中 在步驟(3)時,可真空環境裡先抽真空再封蓋,且可使用 一皮軟塾吸取玻璃,因此玻璃表面不會被刮傷。Scope of patent application L .. An IC vacuum capping process includes the following steps: (1) Provision of a transparent cover; (2) Provision of a substrate with a castle around the substrate, 1C is placed on this substrate, and wiring is provided Apply UV glue to the upper side of the castle, and place this transparent cover on the castle with UV light around the substrate; (3) Place the structure obtained above in a vacuum environment; (4) Use ultraviolet light to irradiate UV The glue is cured, so the transparent cover can be fixed to the castle. 2. For example, the 1C vacuum capping process in the first item of the patent application scope, where the substrate is an array substrate to encapsulate most of the IC, and the transparent upper cover can also cover this majority of 1C. After the capping, a cutting operation is performed to cut into 1C. 3. For example, the 1C vacuum capping process in the first item of patent application scope, where 1C is CMOS image sensor 1C. .4 · If the 1C vacuum capping process of the first item of the patent application scope, in step (3), the vacuum can be evacuated and then capped in a vacuum environment, and the glass can be sucked with a soft skin, so the glass surface is not Will be scratched.
TW89110312A 2000-05-26 2000-05-26 IC vacuum capping process TW449891B (en)

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