TW449883B - A 3-D interpoly dielectric film to improve the gate coupling ratio of stacked gate flash memory - Google Patents

Abstract

A stacked-gate flash memory cell with enhanced gate coupling ratio is disclosed. It contains a U-shaped floating gate, a control gate, and an interpoly oxide layer sandwiched therebetween. The interpoly oxide layer and the control gate conforming to the U-shape of the floating gate so as to achieve increased areal overlap. In a preferred embodiment, the stack-gate flash memory is fabricated from a process which includes the following steps: (a) depositing a tunnel oxide layer and a poly layer on a silicon substrate, followed by poly 1 implantation; (b) depositing a thin oxide layer, then a nitride layer on the poly 1 layer, followed by a poly 1 photolithography process to form a poly 1 stack; (c) performing a silicon substrate etch to create shallow trenchs in the silicon substrate, followed by second oxide deposition to fill the shallow trench; (d) performing CMP planarization and oxide etch-back to remove the second oxide; (e) depositing a poly 2 layer, followed by poly 2 implantation and poly 2 etch to form a poly 2 spacer on sidewalls of the poly 1 stack; (f) removing the nitride layer by wet etch, followed by wet dip to remove the first oxide layer on top of the poly 1 layer, (g) depositing an interpoly dielectric and a poly 3 layer, followed by using a poly 3 photolithography process to form control gate from the poly 3 layer.

Description

!, 449883 V. Description of the invention 0) The present invention relates to an improved stacked idle flash memory cell structure capable of increasing the overlap area (Areal Overlapping) between the floating gate (FG) and the control gate (CG) (Stacked Gate Flash Memory Cell), because it can increase the control gate-to-floating-gate coupling ratio (Control-gate-to-floating-gate Coupling Ratio), and improve the performance of the memory cell. In particular, there is a novel method for manufacturing a stacked gate flash memory cell, and in this method, a flash memory cell is formed, in which a floating self-aligned (Self-aligned) layer is formed on the field oxide layer without sacrificing floating Coupling rate between gate and control gate. The novel method applied in the process of the present invention also reduces the distance between floating gates because it exceeds the limit of the traditional basic lithography technology. Therefore, the present invention can further reduce the size of the flash memory cell (Scaling Down) 'And will not lead to excessive costs due to improved lithography technology. In addition, a higher light rate allows the memory cell to operate at a lower control gate voltage; this advantageous feature reduces a stringent stringent standard of breakdown voltage between flash memory cells. Therefore, the method disclosed in the present invention basically can not only reduce the size of the flash memory cell, but also reduce the voltage of the floating gate. With the introduction and rapid increase of digital cameras and palm-size personal computers, high-density flash memory having a small size and being a portable large-capacity memory has been widely noticed. For electronics consumers, the most important key of Flash 5 memory is that it can reduce the cost of bits by reducing the size of the memory cell. In order to reduce the size of the cells, the data line spacing (D a t a L in n P e t c h) must be reduced as much as the gate length. Floating gates reduced in size-like ^ _ 免 _ makes the quick step smaller, this pair

b 4 49883_ 5. Description of the invention (2) The coupling rate between the floating gate and the control gate in the stacked gate flash memory has an adverse effect. Therefore, in the semiconductor manufacturing industry, a high gate coupling rate is achieved and at the same time, the flash memory cell scale can be made smaller * ~~ ~ more > .__ is challenging. -One by one___ On page 271 (1997) of the IEDM, the title is "A Novel High Density 5F2 NAND STI Memory Cell Technology for 2 56 Mbit and 1 Gbit Flash Memory" by K. Shimizu, K, Narita, H.

The public literature of Watanabe, E. Kamiya, Takeuchi, T. Yaegashi, S. Aricome, and T. Watanabe, has revealed the 5F2 NAND STI memory cell technology of Low Bit-cos t flash memory. Figure 1 shows the three polycrystalline silicon layers used in Shimizu et al's literature to make flash memory. The first thin polycrystalline silicon film 22 (forming a part of the floating gate) provides a function of improving the controllability of the planarization process during the formation of the shallow trench isolation (Shallow Trench Isolation). The second polycrystalline spar film 24 (which also forms part of the floating gate) can be defined by the silicon nitride mask layer 26 and two nitride spacers (Spacer) 28. The nitride spacer 28 can provide a second polycrystalline silicon film 24 on top of the Field Oxide to overlap, so as to improve the engagement rate of the memory cells. The memory cells disclosed in Shimizu et al's literature are not self-aligned due to the formation of the SiN pattern (before the formation of the Si N gap wall); ^ & & layer boundaries, the SiN mask at the memory cell scale The misalignment tolerance between the layer and the polycrystalline sand layer is significantly limited. Furthermore, the internal dielectric film between the control gate and the floating gate is a two-degree space.

44988 3 Fifth, the description of the invention (3) Therefore, the improvement of the light-on rate is all due to the floating gate overlap (controlled by the nitride spacer) on the top of the field oxide layer, so the improvement of the coupling rate is quite affected limit. In another heading, "A kind of 0,24- # m2 memory cell system with _ 18_ μm width isolation and 3-D internal polycrystalline silicon dielectric film for Gb flash memory

The publications of Katayama, H. Kurata, A. Miura, T. Mine, Y. Goto, T. Morimoto, H. Kiime, T. Kure, and K. Kimura, disclose the use of a 0.2-ym process technology, A method for fabricating a flash memory cell of 0. 24-μm 2 contactless (array). Between the memory cells, a borophosphosilicate glass (BPSG) 42 is filled into the grooves, forming a self-aligned shallow groove isolation of 0.18- // m wide 44 (Shal l0w Groove Isolation, SGI) To maintain the isolation breakdown voltage. In addition, a two-degree space, single-layer chemical vapor deposition oxide layer with intercapacitance is used as the internal composite aa lithium dielectric film 38. The internal operating voltage is reduced by increasing the area ratio. In Kobayashi The process disclosed in the et al literature includes the following main features: (1) the first polycrystalline silicon film can be used as the first floating gate 32, and is self-aligned to the boundary of the field oxide layer; (2) the second polycrystalline The silicon film is used as a sacrificial layer and will be removed later to form a U-shaped floating gate. (3) After the Bu-type floating gate is formed and the floating gate is patterned, the third polycrystalline silicon film can be used as the second floating gate. Gate 36: (4) The fourth polycrystalline silicon film 40 can be used as a control gate pattern; a single-layer three-dimensional (3I)) CVD oxidation internal dielectric fine is formed between the control gate and the floating gate to further improve the light However, 丄 = 449883 V. Description of the invention (4) There are also several obvious shortcomings in the process of al. First, four layers of polycrystalline silicon are required. The second 'due to the formation of the floating gate pattern (the third polycrystalline silicon) is not self-aligned with the first polycrystalline silicon pattern, the floating gate pattern cover layer (ie, the top of the floating gate layer) and the first The misalignment tolerance between the polycrystalline silicon patterned curtain layer (the bottom of the floating gate layer) will be limited in the memory cell size. In addition, the accumulated oxide layer between the floating plutonium and the control gate is a potential cause of data reliability problems. Therefore, the stack gate flash memory of the size of one object of the present invention consumes-. It is particularly relevant to provide a cell, which can increase the coupling between the floating gate (FG) and the control gate. The floating gate can be manufactured by a novel method under the light-on ratio of the floating gate. The novel method used can reduce the distance between floating gates beyond the pass and further reduce the size of the gates without causing costs. The memory cell of the present invention enables the sigma cell to control the gate power at a lower level. The main features of the preparation reactor disclosed in the present invention include: (1) a first quasi-field oxide layer boundary and a compound crystal trench isolation) a planarization step; (2) The problem that the internal dielectric film is a single-layer chemical vapor deposition (dataretenti ο η) will receive severe attention. 'It is to provide a high-performance, but small', and an improved stacked gate flash mark (C G) which can increase the control gate to the gate to increase the overlap area between gates, so the closing rate. The stacked flash memory of the present invention is aligned with the field oxide layer without sacrificing the control gate and the floating question. The process of the present invention is based on the limit of the basic lithography technology-therefore, the present invention can cause the flash memory cell to cause too much higher gate lightening rate, which is proposed by the improved lithography technology, and can also be operated under pressure. The process of stacking flash memory cells has several polycrystalline stones (part of the floating gate). The self-aligning stone film is quite thin to facilitate s τ I (the shallow oxide / nitride layer can be used as a sacrifice.

Page 8 449883 V. Description of the invention (5) The layers are removed before the second polycrystalline silicon layer is deposited; (3) The first polycrystalline stone layer is deposited to form the first polycrystalline silicon layer Polycrystalline silicon spacers on each side of the layer pattern (part of the floating gate) ^ The formation of the spacers proposed in the process of the present invention allows the final floating gate to self-align with the field oxide layer ° field oxidation The floating gate overlap at the top of the layer can be determined by the thickness of the polycrystalline silicon spacer. In addition, the formation of the polysilicon spacer wall can make the distance between two adjacent floating gates smaller than that restricted by the traditional basic lithography technology. These two features further reduce the scale of memory cells. The process disclosed in the present invention can be summarized by the following steps: 0) Deposit a tunneling oxide layer (about 70-120 angstroms) on a silicon substrate and one? The first polycrystalline stone layer (about 300-1000 angstroms) is then implanted with the first polycrystalline silicon layer. C 2) depositing a thin oxide layer (about 丨 00_ 丨 0000 angstrom) on the substrate, and then a nitride layer (about 3,000 angstrom), and then lithography the first polycrystalline silicon layer to form a first A polycrystalline silicon stack structure. (3) Performing a broken substrate etching 'produces at least one shallow trench, and then an oxide layer is deposited to fill the shallow trench, and then chemical mechanical polishing is performed to planarize and etch back the oxide layer. This shallow trench will serve as insulation between memory cells. (4) Depositing a second polycrystalline silicon layer, ion implanting the second polycrystalline silicon layer, and etching the second polycrystalline silicon layer to form a second polycrystalline silicon spacer. (5) The nitride layer is removed by etching, and then the oxide layer on top of the first polycrystalline stone layer is removed by wet dipping. (6) depositing an inner polycrystalline silicon dielectric film and a third polycrystalline silicon layer, and then

Page 9 " 4498 83 V. Description of the invention (6) The lithography of the third polycrystalline silicon layer is used to make ribs to form a control gate from the third polycrystalline silicon layer. The present invention proposes that one of the main components of a Qin flash memory cell is a thin first-complex broken floating gate portion and a compound crystal gap wall floating gate portion, which can form a self-aligned field nitrided living space. This structure is basically It can increase the effective cross-section area between the floating gate and the control gate. Therefore, without increasing the memory cell area, the memory cell can achieve a higher gate coupling rate. Compared with the conventional 3-D floating gate structure, the present invention only requires three polycrystalline silicon films (the first floating gate portion, the second floating gate portion, and the control gate). Furthermore, in the present invention, the use of an inner multiple crystal silicon dielectric film having an oxide layer / nitride layer / oxide layer can achieve a satisfactory data storage capability. The detailed description is as follows. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following exemplifies-the preferred embodiment, and is accompanied by the accompanying drawings to make the detailed illustration simple. Guo Ming: A manufacturing method for forming a flash memory cell, a sectional view of a manufacturing method for forming a flash memory cell. The first display shows 1 ^ 1. The other display shows the conventional display, and the third picture is shown on the silicon. The substrate is the first polycrystalline stone, and one station is to penetrate through the oxide layer, a thin ^ ^ 46 a », a rolling layer, and a nitride layer ', and then proceed to the second photolithography process, To form the first polycrystalline bite stack: Figure 3b shows a silicon substrate etched to form a shallow trench and then by oxygen

4498 8 3 V. Description of the invention (7) Deposition of the compound will fill the shallow pond, and the reduction layer 'will be outside the shallow trench. = Mechanical mechanical grinding and etch back to form the second polycrystalline stone interlayer :: eve Layer deposition, ion implantation, and 3D image display-the station's office, "soil" to remove oxides \ 7 etch to remove nitrides, and then wet soak the second image display ":: type three degrees The floating closure of the space, and after that, the lithography process of patterning and cladding the polycrystalline silicon dielectric 骐 and the third polycrystalline silicon layer in the r: s ′ product is performed. '' Invented stacked gate flash memory. 4: Nitride layer oxygenated layer ~ Polycrystalline silicon layer; 3: Thin oxide layer; 7: First stacked polycrystalline silicon layer structure; 6, No. Two polycrystalline stone walls; dielectric film; 1 2 > & '° ϋ _ type floating gate; 11: inner polycrystalline silicon Π gas / I22 :. first-complex floating open; H stone Overlay layer, 28: nitride barrier wall; 32: first compound stone film 1 · second floating open; 38: internal dielectric film · 40 · fourth compound stone film, 42: Rpqr * α n. v, and 44. shallow groove isolation a Example: H /: It is an improved stacked flash memory cell that increases the coupling rate of the control gate to the floating gate by using the gate (FG) and the control gate (CG). The stacked flash memory of the present invention The cells can be prepared by a novel method, in which the floating gate has a three-dimensional space-type structure, and without sacrificing the coupling rate between the control gate and the floating gate, the floating gate can be self-aligned to the field oxide layer. The novel method applied in the present invention enables

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The pitch is narrower than that restricted by traditional basic lithography technology. So the invention of clothing makes! The size of the memory cells is further reduced, and the inconsistency leads to the cost of bismuth. The higher gate coupling two proposed by the memory cell of the present invention can also enable the memory cell to operate at a lower control gate voltage. The following is a detailed summary of the main steps of the present invention: • Deposition of a tunneling oxide layer (70-120 Angstroms) • Deposition of a first polycrystalline silicon layer (300-1000 Angstroms); A polycrystalline silicon layer; • depositing a thin oxide layer (300-1,000 angstroms); depositing a nitride layer (~ 300 angstroms) (as a CMP stop layer) defining a first polycrystalline silicon stack structure with a photomask; etching the first Multicrystalline silicon stack structure; lithography of silicon substrate to produce shallow trenches; deposition of oxide layer to fill shallow trenches; chemical mechanical polishing and planarization and return of oxide layer; pre-deposition cleaning of the second polycrystalline silicon layer; Second polycrystalline silicon layer; Ion implanted second polycrystalline silicon layer; Etching the second polycrystalline silicon layer to form a second polycrystalline silicon bulkhead 'Wet etching removes nitrides of the deposited layer;' When removing by wet soaking The oxide layer on top of the first polycrystalline silicon layer forms a U-shaped float from the first polycrystalline silicon layer and the second polycrystalline silicon layer, and deposits the inner polycrystalline silicon dielectric film; τ 'deposits the third polycrystalline Silicon layer, the third polycrystalline silicon layer is controlled with < 1 tile formation 449883 9) Gate; • Defining the control gate with a photomask; and • Engraving the control gate / floating gate to form the final memory cell. As described above, the process for preparing a stacked flash memory cell disclosed in the present invention has several main features, including: (1) forming a first polycrystalline silicon layer or a polycrystalline silicon 1 film on the bottom portion of the floating gate; Aligned to the field oxide boundary, and the first polycrystalline silicon film is so thin that the ST I planarization step can be used; (2), the compound and gaseous layers can be used as sacrificial layers, the wings are more than one, and the two The layers are removed before the silicon layer is deposited; (3) a second polycrystalline silicon layer is deposited to form a polycrystalline silicon spacer on each boundary of the first polycrystalline silicon layer pattern, that is, the wings of the floating gate. According to the novel step of the silicon spacer of the present invention, the most converted floating gate can be self-aligned with the field fization layer. The overlapping portion of the floating gate on top of the field oxide layer can be determined by the thickness of the polycrystalline silicon spacer. . Furthermore, the formation of the 'gap wall' can make the distance between the floating gates smaller than that restricted by the traditional basic lithography technology, and the point feature will further reduce the size of the flash memory. The present invention will be described in more detail by the following examples. It should be noted that: Including the preferred embodiments of the present invention, the description of the following embodiments is-the drawings are not for illustration, and are not exhaustive or intended to limit the present invention. He, Sheng, and Figure 3e show the main features of the improved male stacked gate flash memory with increased gate coupling between the gate and the control gate according to the preferred embodiment of the present invention. step. As shown in Figure 3a, a tunneling oxide layer i, a first

t. 4 4 9 8 8 3 V. Description of the invention (thin) 'Thin polycrystalline silicon layer 2, thin oxide layer 3 and nitride layer 4, followed by micro-viewing; process to form a first polycrystalline silicon stack structure 7. The thickness of the oxide layer 3 determines the final coupling ratio between the floating gate and the control gate. A larger thickness is more beneficial for the ^ 2 area ratio, but it will increase the difficulty of flattening the CMP (chemical mechanical polishing) when a shallow trench isolation is subsequently formed. As shown in FIG. 3b, a shallow trench 5 is formed by etching on a silicon substrate, and then an oxide layer is deposited to fill the shallow trench. After that, the oxide layer outside the shallow trench is removed by chemical mechanical polishing and etch-back of the oxide layer. Figure 3c shows that a second polycrystalline silicon spacer wall 6 is formed on the boundary of the first polycrystalline silicon stack structure 7. The second polycrystalline silicon spacer wall 6 is firstly deposited by depositing a second polycrystalline silicon layer and ion implantation. A second polycrystalline silicon layer is formed by anisotropically etching the second polycrystalline silicon layer. As shown in Fig. 3d, a -u-type three-dimensional floating gate § is formed. This floating gate 8 includes a portion from the bottom of the first polycrystalline silicon layer 2 and the wing portion of the second polycrystalline silicon spacer wall 6. . The formation of the three-dimensional space u-type floating gate 8 first removes the nitride layer 4 by wet etching, and then removes the oxide layer 3 on the first polycrystalline T layer 2 / page portion by a immersion immersion method. The height of the second polycrystalline broken spacer 6 can be determined by the combined height of the thin oxide layer, the nitride layer, and the first polycrystalline silicon layer. The wet soaking process will consume part of the oxide layer in the shallow trench isolation 6, and the degree of consumption depends on the thickness of the thin oxide layer 3. However, since the second polycrystalline silicon spacer wall exists along the sidewall of the tunneling oxide layer, the tunneling oxide layer can be protected without being damaged by the HF traditionally used for wet soaking. As shown in FIG. 3e, the polycrystalline silicon dielectric film 11 and the third polycrystal 44988 are deposited in the deposition. V. Description of the invention (11) Silicon layer 1 2 'Then a lithography process is performed on the third polycrystalline silicon for After the control gate is patterned from the third polycrystalline stone layer, the stacked gate flash memory 10 of the present invention is formed. The inner polycrystalline silicon dielectric film 11 and the third polycrystalline silicon layer 丨 2 are both formed by matching the outline of a U-shaped two-dimensional floating gate. Therefore, the overlap area 'between the floating gate 8 and the control gate 12 will be increased subsequently, and the handle ratio between the floating gate control and the control gate will be increased. In addition, since the floating section 8 also includes the wing portion formed in the silicon layer, the distance between adjacent floating gates can be shortened, so the present invention can be further improved without improving the lithography process. Flash memory cell scale. 'Although the present invention has been limited to the present invention by a preferred implementation, anyone familiar with this technique and scope, when it can be modified and retouched, the examples defined in the scope of the patent application attached below are disclosed above, but it is not intended to be used' The spirit of the present invention, therefore, the scope of protection of the present invention shall prevail.

15th stomach

Claims (1)

4 49 8 8 3 __ Case No. 88107972 Amendment 6. Scope of patent application 1. A method for manufacturing a stacked gate flash memory cell, including the following steps (a) depositing a tunneling oxide layer and a silicon oxide substrate on a silicon substrate A first polycrystalline silicon layer, and then ion implanting the first polycrystalline silicon layer; (b) depositing a first oxide layer on the first polycrystalline silicon layer, and then depositing a nitride layer; A lithography process is performed on a polycrystalline silicon layer to form a first polycrystalline silicon stack structure; (c) etching the silicon substrate to generate at least one shallow trench in the silicon substrate, and then depositing a second oxide layer To fill the shallow trench; (d) performing chemical mechanical polishing to planarize and etch back the oxide layer to remove the second oxide layer beyond the shallow trench; (e) depositing a second polycrystalline silicon layer, and then ionizing Implanting the second polycrystalline silicon layer and etching the second polycrystalline silicon layer to form a second polycrystalline silicon spacer on the side wall of the first polycrystalline silicon stack structure; (f) wet contact Remove the nitride layer, and then wet soak the first polycrystalline silicon The first oxide layer on top of the layer, wherein the second polycrystalline silicon spacer and the first polycrystalline silicon layer form a ytterbium-type three-dimensional space floating gate; and (g) depositing an inner polycrystalline silicon dielectric The electric film and a third polycrystalline silicon layer are then subjected to a lithography process to form a control gate from the third polycrystalline silicon layer; (h) the inner polycrystalline silicon The dielectric film and the control gate cooperate with the U-shaped three-dimensional space contour of the floating gate, so the area overlapping portion between the control gate and the floating gate can be increased. 1 ^ · 0492-4386m] ptc page 16 4 4 9 8 g3 88107972 Λ_ i 正 Six 'application for patent scope 2. As described in the first patent application scope for the method of manufacturing memory cells, 1g of this gate gate flash memory said that the thickness of the material layer deposited in the silicon stack is so that the first-blessing « The Xixi reactor oxygen structure is consistent with the design height of the U-shaped floating gate. Resume the method of covering the memory cells as described in the patent application | a. Item 1 above, i + bowl penetration ~, day stack gate flash memory m, the thickness of the deposited silicon layer is The design separation distance between the π gates—the method of manufacturing stacked flashes = cells described in the following paragraphs of the adjacent cell 4, where the tunneling oxide layer has about 70 angstroms To _Erji! 'Manufacturing stack flashes described in item 1 of the patent scope <, 仏' wherein the first polycrystalline silicon layer has about 300 Angstroms to 1,000 Angstroms 6 * as applied The method for manufacturing a stacked gate flash memory cell according to item 1 of the patent, wherein the first oxide layer has a thickness of about 100 angstroms to 1,000 angstroms. 7. A method for manufacturing a stacked gate flash memory as described in item 1 of the scope of patent application, wherein the halide layer has a thickness of about 300 angstroms. 8 · A stacked gate flash memory cell structure with increased gate coupling rate, including: (a) a substrate and a tunneling oxide layer on the substrate; (b) on the tunneling oxide layer A U-shaped floating gate, the U-shaped floating gate includes a bottom portion and a wing portion; and (c) a control gate, and an inner loop between the floating gate and the control gate Crystalline silicon oxide sandwich structure, the inner polycrystalline silicon oxide layer and the control gate 0492-4386TW? Lpu Page 1? 449883 0492 ~ 4386TWFl'pic Page 18