TW449859B - Embedded type alignment mark - Google Patents

Abstract

The present invention is about a kind of embedded type alignment mark and the fabricating method of this embedded type alignment mark. The spirit of this invention is that the whole alignment mark is embedded inside the substrate and a passivation layer is used to cover the whole alignment mark. Because the whole alignment mark is located inside the substrate and is not exposed outside the substrate surface, any procedure in the fabricating process of semiconductor device will not cause damage of alignment mark such that the precision of alignment in the following process is assured.

Description

49 85 9 V. Description of the invention (1) Field of the invention: The present invention relates to a method of exact accuracy, in particular B ', the parent mark (base mark) to the inside of the substrate to prevent correction. By inserting the calibration tag into the private interception method. 5 ~ 2 Background of the Invention: A process in which a plurality of crystal semiconductors are used to perform the necessary first calibration is used to calibrate the tangible layer to the actual chip. The semiconductor process is often used to form the wafer. The mark used in the wafer (the semiconductor device needs to be formed, including the edge of the light source or the crystal layer of the special calibration mark before the calibration label is not included, but it is not only signed more than once.) The pattern, wavelength, and ignment on the surface of the wafer are only allowed to be performed on one wafer and one die. Therefore, before, there are subsequent lithography procedures for each subsequent lithography process and the calibration is zero. The size of the program is determined by the shooting method. Here, it is called mark). Obviously, since each lithography process must use the calibration label as the basis for calibration, any step in the semiconductor process must be It meets the requirement of not damaging the calibration label, otherwise it will cause intractable misalignment in subsequent steps. In any case, some conventional semiconductor processes can cause damage to the calibration process. An obvious example early θ

Isolation, STI) ^ t fl /. ^ (Shallow Trench 10 is located on the table of the substrate 12 & ψ ° —A, the calibration label w is formed on the upper surface of the calibration label, which is formed by the calibration engraving procedure. A label 1 0 is used to form a shallow channel in the shadow-etching process. 4 In the figure, the first step is to cover the substrate 12 with another-micro-etching J to the surface of the substrate 12 and Fill all the schools: the material of the protective layer ⑺ coating layer 16 is usually nitrided:; = \ °, channel 14, where the protective mill (chemical mer-h · (1) is taken, and Uhenucal is ground with a chemical machine mechanical p〇Ushing, "The surface of material 12 is shown in Figure -c. Obviously, because the polishing rate (P0HShing rate) of layer 1 in the CMP process is not the same, 18 shots, 0 accurate = [ Both the edge of 10 and the failure of shallow channel 14 will cause damage: quasi-damage 18 will not cause isolation function ^ To & quasi ^ Sign 1 () '在 其 边 所 # The current damage 18 will cause the subsequent lithography procedures to be unable to be properly and accurately calibrated. In response to the aforementioned deficiency, the conventional semiconductor process technology solutions are located in the lithography procedures. The number of calibration labels 10 is increased in the mask, which reduces the degree of error by more calibration sources. In any case, this method is also accompanied by some unavoidable defects such as the assembly of the multilayer structure and the layers. Tolerance will increase, especially when the device pitch shrinks. As can be seen from the previous discussion, the conventional calibration labels still cannot be damaged by subsequent semiconductor processes, so in order to Determine the lithographic process

449859 Five "Invention Description (3) Accuracy" quasi-tag 15 Must be a school that can not be damaged by the semiconductor process 5-3 Purpose and summary of the invention: A manufacturing method damaged by the main semiconductor process of the present invention ^ To achieve the foregoing, in order to realize the present invention, manufacturing the push-in calibration mark is to form a calibration mark originally formed on a substrate into a surface of the substrate. This zero-level calibration label is the same, i ::? Layer protection, because it will ... in-type calibration standard 5 simple illustration of the diagram 3, in providing a ^ standard label that will not be carried out subsequently. Another object of the present invention is to propose a purpose The process of calibration labels. $ Each purpose ’An in-line calibration label and a method are proposed. The main feature of this invention is the face calibration label (zero-level calibration label), the bottom of the trench canal, and covered with a protective layer. The inside of the substrate can ensure damage to subsequent semiconductor fabrication. vFigure ~ a to the Dai shallow trench isolation process depicts how the conventional calibration label 'damages' in the poles 媸 Figure 本 The damage mechanism of the present invention; It is not intended; and 5. Description of the invention (4) The third diagram A to the third diagram E are a series of cross-sectional schematic diagrams showing steps in another embodiment of the present invention. Representative symbols of the main parts: 1 0 calibration label 12 substrate 14 shallow trench 16 protective layer 18 damage 20 trench 22 substrate 24 push-in calibration label 2 6 protective layer 28 damage 30 substrate 3 1 first oxide layer 32 Channel 33 Insertion type calibration label 34 Second oxide layer 35 First photoresist layer 3 6 Second photoresist layer 5-5 Detailed description of the invention:

449859 Five 'invention description (5) The structure of the penetrating calibration mark proposed by the present invention can be sketched qualitatively with the second input = ditch 20 is located on the surface of the substrate 22, and the calibration calibration The sign 24 is located at the bottom of the trench 20 and is covered by a protective layer 26. Usually, the protective layer 26 fills the entire trench 20. In addition, since the surface of the substrate 22 is flattened by chemical mechanical polishing, a shape of 0 = edge will cause damage28. In addition, the form of the zero-level calibration label of the penetrating calibration label 24 is completely the same. The only difference is that the type-2 calibration label 24 is located inside the substrate 22 and is obviously protected by the protective layer 26. It is damaged by the manufacturing process such as lithography. Even the calibration standard can correctly learn the assembly tolerances between technologies. Most photomasks effectively improve the calibration standard. The in-line calibration says that 'such as adding' requires the use of the substrate 22 to remove any damage to the shadow process and effectively modify the signing of the layer or even the signing of 2 4. As the penetration of the protective layer 2 6 will not cover and etch Make the complete calibration of the 2 4 structure at the open side of the trench 20, that is, the absence of 崁. In other words (tolerance), the absence of 増, etc. can be completely iron 2 4 where the subsequent quasi-label 24 is injured 2 8, nor will the subsequent micro-label 24 have a multi-layered structure with most of the calibration marks: enter Calibration standard

Incidentally, the substrate? 9 M and 1 drawer? The material type of fi DING # 2 can include at least silicon, and the possible material types 7 碉 to v of the protective layer 2 6 include oxides. In addition, on page 8 4 sentence 859 'V. Description of the invention (6) = The pattern and size of the Tibetan 24 depend on the subsequent semiconductor, and must be thick to the subsequent semiconductor fψ = guarantee. Thickness of the mantle layer 26? h "" can ensure that the push-in calibration standard 24 will not be damaged. In addition, the present invention can further include a surface of the protective layer for a flattening process— ' 〇 // of the frankization procedure are wet etching and dry etching. In another embodiment of the present invention, a method capable of forming-insertion type calibration is proposed. The method At least the following steps are included: (1) As shown in the third A ',' provide the substrate 30 covered by the first oxide layer 3] and the possible material types of the substrate 30 include at least silicon and polycrystalline silicon, and then form a photoresist The layer 35 is above the surface of the first oxide layer 31. (2) As shown in FIG. 3B, using the first photoresist layer as a mask, a first lithographic etching process is performed on the substrate 30 to form the trench 32. On the surface layer of the substrate 30, the depth of the trenches 32 must be greater than the thickness of the first oxide layer 31. Here, the first lithography etching sequence includes at least the following procedures: (a) forming a first photoresist 35 is above the first oxide layer 31, and the pattern of the first photoresist includes at least a blank area (B) A first etching process is used to remove the parts not covered by the first photoresist.

u 85S V. Description of the invention (7) The first oxide layer 31 and a part of the substrate 30 form the trench 32 on the surface of the substrate 30. (c) Remove the first photoresist 35. (3) As shown in FIG. 3D, a second lithography etching process is performed on the trench 32 to form a penetrating calibration label 33 at the bottom of the trench 32. Here, the embedded calibration label 33 is the entire It is located below the surface of the substrate 30, and the pattern and size of the penetrating weight label 33 are determined by the wavelength and incident method of the light source used in the subsequent process of the substrate 30. The above-mentioned second lithography engraving procedure includes at least: (a) forming a second photoresist 36 on the first oxide layer 3}, and the pattern of the second photoresist is a pattern of a penetrating calibration label 33; and The position of the pattern of the second photoresist completely corresponds to the trench 32, as shown in FIG. 3c. Adjacent parts remove the four parts of the substrate 30 not covered by the second photoresist 36 in a first-step process, so as to form a penetration at the bottom of the trench 32. The so-called partial primer refers to the surface layer of the substrate 30. (c) Remove the second photoresist 36. (4) As shown in FIG. 3E, a second oxide layer is first deposited on the layer 31, and the trench 32 is completely filled, and then all the second oxide layers 34 other than ^ 32 are removed and removed. Of course, this method can be further advanced

449859 V. Description of the invention (8) The steps of the planarization process of the second oxide layer 34 and the first oxide layer 31 include at least the second oxide layer 34 as a penetration type and the material phase of the first oxide layer 31. ^ The surface is subjected to a flattening process, a diffuse engraving and a dry button engraving. It is used for the calibration label 33, and its material can be used as described above. It is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; Equivalent changes or modifications should be included in the scope of patent application described below.

Claims (1)

^^ 985 $ A description of the standard entry form for signing. The silicon items include 1 package of the least profitable to the special application, as described in the material, and the process of the light source used in the process and the wavelength 4 and the incident method 4 .--The material of the protective layer includes at least oxides. 4 ^, the above mentioned in 5 · Shi Shen sqing patent item 1 step into the Shi Shizuo pile ^ protective layer surface "quasi standard storage, ... the 6 mentioned in the 1 item Calibration label, wherein the method described above at least includes dry etching. The carbon-in-calibration label described in item 7 above, "The eleven-step method described above includes at least wet etching. Page 12 449859 Sixth, the scope of patent application 8 kinds of methods for forming a push-in calibration label, including at least: providing a substrate, the substrate is covered by a first oxide layer. A first lithographic etching process is performed on the substrate, Thereby, a trench is formed on a surface layer of the substrate, and the depth of the trench is greater than the thickness of the oxide layer; the second lithography process is performed on the trench to form a -p calibration mark hidden in the The bottom of the trench 'The calibration label is located entirely below one of the surfaces of the substrate;' "-a second oxide layer is deposited on top of the first oxide layer and the layer completely fills the trench; and-removed All of the second oxide layer located outside the trench. The material of the above substrate 9. The method described in item 8 of the patent application includes at least silicon. 10. The method described in item 8 of the patent application The above-mentioned first lithography etching process includes at least: forming a first photoresist on the first oxide layer, and the pattern includes at least a blank area; removing the first etching process without using the first etching process The first oxide layer covered by a photoresist Portion of the substrate, thereby forming a trench in the surface of the substrate; and removing the first photoresist. 449859 The method of applying for patent scope is the method described in item 8 of the patent application, wherein the above-mentioned second lithography process d includes at least: a pattern forming a second photoresist on the first oxide layer, the second photoresist ^ Is the pattern of the embedded calibration label, and the pattern of the second photoresist completely corresponds to the trench; 枓 M-a second engraving procedure to remove the second photoresist that is not covered by the second photoresist The bottom layer and the surface layer are used to form the insertion calibration label at the bottom of the trench; and the second photoresist is removed. 12 .. The method described in item 8 of the hub application patent, in which the pattern and size of the above-mentioned in-cell calibration are determined by the wavelength and incident mode of the light source used in the subsequent process of the substrate. The method described in item 8 of the patent application further includes a process of leveling the second oxide layer. U. ^ Fang & the method described in the eighth patent application, wherein the above-mentioned flattening procedure includes at least one money and one rhyme. Page 14