經濟部智慧財產局員工消費合作社印^ 449831 . A7 4758twf.doc/008_..__B7 五、發明說明（，） 本發明是有關於一種靜電放電保護結構’且特別是有 關於一具有雙重靜電放電（ESD)植入層之金氧半導體場效 電晶體(MOSFETS)的結構。 靜電放電被認爲是一镡現象，此現象是當一具有固定 能量的帶電元件突然將載子（carriers)放電到另一個具較低 能量元件的過程。放電過程非常快速，因此，若放電路徑 具低電阻，則會導致高的瞬間電流。有關靜電放電最常見 .的例子是，當一個人走過低濕度的地毯而帶有靜電後，此 人一旦碰觸半導體元件，則從人體到半導體元件便會發生 靜電放電。除非有箝制大電壓和轉移因靜電放電產生的電 流之方法，否則放電會造成半導體元件的損壞。 圖1顯示積體電路（integrated circuit-IC)輸入墊（input pads)典型的放電保護電路之習知技術圖示解說。一輸入墊 101爲內部電路103的界面，且在輸入墊101和內部電路 103之間配置一 p型金氧半導體（metal oxide semiconductor-MOS)105 和一η 型金氧半導體 107。而 p 型 金氧半導體和η型金氧半導體的閘極均連接至其源極。一 般而言，對於輸入墊的保護，ρ型金氧半導體和η型金氧 半導體的接面崩潰電壓（the junction breakdown voltage)應 當小於闇極氣化層崩潰電壓（the gate oxide breakdown voltage) ’而且應大於Μ倍的工作電壓（Vdd)。然而，爲配 合元件更小化和低耗電電路需要，工作電壓會逐漸降低， 此時’被應用在金氧半導體場效電晶體(MOSFETS)的閘極 氧化層厚度更加縮小’因而造成閘極氧化層崩潰電壓也隨 之更加降低，使得在深次微米技術中的，，回衝，，(snapback) 4 紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公g ) (請先閱讀背面之注意事項再填寫本頁) 裝 ----訂·-------- 經濟部智慧財產局員工消費合作社印製 449831 . A7 4758twf.doc/008 B7 五、發明說明（>) 效應會變得更難控制在適合範圍。回衝效應的細節可查閱 Amerasekera 在 U.S. Patent N〇.5,804,860 中的說明。 一般而言，一靜電放電脈衝會在金氧半導體場效電晶 體（MOSFETS)中產生大量的熱，習知稱此現象爲熱焦耳 (joule heating)效應，若金氧半導體場效電晶體(MOSFETS) 不能均勻且有效地導流靜電放電脈衝電流，此電晶體將會 被熱燒燬。然而，深次微米元件則利用淺接面（fallow junctions)藉以較佳地控制短通道（short channel)效應，此 種淺的導流接面會增加電流密度，結果是加強熱焦耳效 應。因此，爲了降低最大電流密度，以及提供一均勻的電 流路徑，習知的技術運用一靜電放電植入層（implant)去增 寬源極/汲極的輪廓。因此，在圖2中可以看見’ 一傳統 輕摻雜汲極(lightly doped drain-LDD)2〇1之金氧半導體場 效電晶體（MOSFETS)包含一閘極201，一側壁間隙壁 (sidewall spacer)203，源極和汲極區 207 和 209。此外’ 利用一靜電放電植入層(implant)211去增寬源極/汲極的輪 廓。一般而言，靜電放電植入層（imPlant)211具有與源極 和汲極相同的導電型式，但是具較低的濃度。因此，靜電 放電植入層(implant)211是一個η型植體，比如是形成磷 系植入層。更進一步而言，雖然圖2只顯示η型金氧半導 體元件，而Ρ型金氧半導體電晶體製造則可以由簡易地轉 換植入層型式獲得。習知的技術細節可參閱 A.Amerasekera 和 C.Duvvury 的著作”ESD in Silicon Integrated Circuits” 第 180 頁，John Wiley and Sons，Inc. 出版。 (請先閱讀背面之注意事項再填寫本頁) 裝------丨訂---------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1 A7 B7 449831 4758twf.doc/008 五、發明說明（、） 不過，習知的技術並沒有對回衝起動電壓（snapback trigger v〇hage)提供足夠的控制。本發明提出處理這個問 題的技術。 本發明在揭露一種具有改良式雙重靜電放電（ESD)保護 的金氧半導體場效電晶體的結構。此電晶體包含：一閘極 結構、一側壁間隙壁、一具有輕摻雜汲極結構之源極/汲 區、一第一層靜電放電植入層與一第二層靜電放電植入 層。閘極結構係由一薄的閘極氧化層及其上的導電層所組 成，其配置於一半導體底材之上。側壁間隙壁係配置於閘 極結構的側壁。輕摻雜汲極結構之源極/汲區之中的輕摻 雜源極/汲極區係位於側壁間隙壁正下方的底材之中。輕 摻雜汲極結構之源極/汲區之中的源極區係位於緊鄰一側 壁間隙壁的底材之中。汲極區係位於緊鄰另一側壁間隙壁 的底材之中。第一層靜電放電植入層係位於源極區和汲極 區的正下方，其雜質型式與源極區、汲極區相同。第二層 靜電放電植入層係位於第一層靜電放電植入層的正下方’ 其雜質型式與第一層靜電放電植入層相反，並且離第一層 靜電放電植入層有一垂直距離。爲讓本發明之上述目的' 特徵、和優點能更明顯易懂，下文特舉一較佳實施例’並 配合所附圖式，作詳細說明如下： 圖式之簡單說明： 圖1係一習知靜電放電保護電路技術之示意圖； 圖2係一習知爲減低靜電放電效應而設計的電晶體之 半導體剖面示意圖： 圖3係一根據本發明製作的電晶體之半導體剖面示意 6 (請先閱讀背面之生意事項再填寫本頁) 裝--------訂---------線CV. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 449831 A7 4758twf.doc/008 gy 五、發明說明（V) 圖；以及， 圖4係一比較本發明與習知技術在改善回衝起動電壓 (snapback trigger voltage)特性上的數據圖。 (請先閱讀背面之注意事項再填寫本頁) 圖式標記說明： 101 :輸入墊 103 :內部電路 105 : p型金氧半導體 107 : η型金氧半導體 201、301 :閘極 203、303 :間隙壁 205、314 :輕摻雜源/汲極 207、305 :源極區 209、307 :汲極區 211 :靜電放電植入層 300 :底材 309 :第一層靜電放電植入層 311 :第二層靜電放電植入層 312 :導體層 313 :氧化層 經濟部智慧財產局員工消費合作社印製 401 :習知的回衝電壓曲線 403 :本發明的回衝電壓曲線 實施例 圖3係一根據本發明製作的金氧半導體場效電晶體之 剖面示意圖。此金氧半導體場效電晶體包含一閘極結構 301、具有輕摻雜汲極結構314之源極區305與汲極區307 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 4 4.9 831 4758twf.doc/〇〇8 五、發明說明（匕） 以及位於閘極結構301之側壁的側壁間隙壁（sidewall spaCe〇3〇3，其中，閘極結構301包括導體層312與氧化 層3Π。依據傳統的習知技術，側壁間隙壁303使用以製 造輕摻雜汲極結構。典型的製造方法係在底材300上形成 閘極結構301之後，先進行輕摻雜之源極/汲極區314之 離子植入製程，再於閘極結構301之側壁形成側壁間隙壁 3〇3，接著，再以離子植入的方式分別製成源極區305和 汲極區3〇7。一般而言，對於一 ο.5 μιη的n型金氧半導體， 閘極氧化層之厚度約120埃。輕摻雜源極/汲極區314的 形成，可以利用磷植入法(phosphorous implantation)以40 KeV的能量達4xl013/cm2的劑量。而源極區305及汲極 區307的形成方法例如使用砷離子植入法以5〇 KeV的能 量達3xl015/cm2的劑量。 下一步驟，運用一分離式的離子植入罩幕(a separate ion implant mask)製造第一層靜電放電植入層309。罩幕的形 成是爲了能完全包含源極區305，汲極區307和輕摻雜 汲極區。而第一層靜電放電植入層309是爲了減小熱焦耳 效應，其雜質型式與源極區3〇5和汲極區307相同◊較佳 的靜電放電植入層309的實例是使用磷系類在5〇 KeV能 量下達lxl〇15/cm2的劑量。 使用與靜電放電植入層309相同的罩幕，在第一層靜 電放電植入層309的正下方形成第二層靜電放電植入層 311。然而’其雜質型式與源極區305和汲極區3〇7相反， 其位置在源極區_305和汲極區3〇7的下方。在第一層靜電 放電植入層309與第二層靜電放電植入層311之間有—間 δ 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) ' 裝 il.— ίί 訂 --------線_ 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 449Β31 , Α7 4758twf.doc/008 五、發明說明（匕） 距，這垂直距離（於圖3中標示爲d)決定了崩潰電壓。當 距離d愈大，則崩潰電壓愈大。在較佳實例中，距離d約 爲 0.15μπι。 爲了形成重摻雜化及輪廓鮮明的第二層靜電放電植入 層311，其選用的植入物重量應盡可能地重。例如在700 KeV的能量下使用銦摻雜達2xl〇15/cm2的劑量。亦或者 可使用硼摻雜。 與習知技術比較，本發明加入第二層靜電放電植入層 311，藉著在製程上調整第二層靜電放電植入層311和第 一層靜電放電植入層3〇9間的距離，可以改善回衝發動電 壓（snapback trigger voltage)。圖4爲定量比較圖，圖中實 線401表示習知的回衝電壓’而虛線402表示本發明的回 衝電壓。 另外’雖然用圖3來說明一 η型金氧半導體，但事實 上’只要改變摻雜型式’本發明亦可以輕易堆應用於ρ型 金氧半導體。 ' 。、土 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內’當可作各種之更動與潤飾，因此本發明之保 護隼β圍當視後附之申請專利範圍所界定者爲準。. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂----III--線Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 449831. A7 4758twf.doc / 008 _..__ B7 V. Description of the Invention (,) The present invention is related to an electrostatic discharge protection structure ', and in particular to a device with dual electrostatic discharge ( ESD) The structure of the metal oxide semiconductor field effect transistor (MOSFETS) implanted layer. Electrostatic discharge is considered to be a phenomenon that occurs when a charged element with a fixed energy suddenly discharges carriers to another element with a lower energy. The discharge process is very fast, so if the discharge path has low resistance, it will cause high instantaneous current. The most common example of electrostatic discharge is when a person walks through a low-humidity carpet with static electricity. Once a person touches a semiconductor element, an electrostatic discharge occurs from the human body to the semiconductor element. Unless there is a method to clamp a large voltage and transfer the current caused by electrostatic discharge, the discharge will cause damage to the semiconductor device. FIG. 1 is a schematic diagram illustrating a conventional discharge protection circuit of an integrated circuit-IC input pads. An input pad 101 is an interface of the internal circuit 103, and a p-type metal oxide semiconductor (MOS) 105 and an n-type metal oxide semiconductor 107 are disposed between the input pad 101 and the internal circuit 103. The gates of p-type and n-type metal-oxide-semiconductor are connected to their sources. In general, for the protection of the input pad, the junction breakdown voltage of the p-type metal oxide semiconductor and the n-type metal oxide semiconductor should be lower than the gate oxide breakdown voltage 'and Should be greater than M times the operating voltage (Vdd). However, in order to meet the needs of smaller components and low power consumption circuits, the operating voltage will gradually decrease. At this time, 'the thickness of the gate oxide layer applied to the metal-oxide semiconductor field effect transistor (MOSFETS) is further reduced', thus causing the gate The breakdown voltage of the oxide layer is also further reduced, which makes the paper size in deep sub-micron technology, (snapback) 4 applicable to China National Standard (CNS) A4 (210 X 297 g) (Please read first Note on the back, please fill in this page again) Binding ---- Ordering ------------ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 449831. A7 4758twf.doc / 008 B7 V. Description of Invention (> ) Effect becomes more difficult to control in the appropriate range. Details of the kickback effect can be found in Amerasekera's description in U.S. Patent No. 5,804,860. Generally speaking, an electrostatic discharge pulse generates a large amount of heat in metal oxide semiconductor field effect transistors (MOSFETS). This phenomenon is known as the joule heating effect. If metal oxide semiconductor field effect transistors (MOSFETS) ) If the electrostatic discharge pulse current cannot be conducted uniformly and effectively, this transistor will be burned by heat. However, deep sub-micron devices use shallow junctions to better control the short channel effect. Such shallow diversion junctions will increase the current density, resulting in enhanced thermal Joule effect. Therefore, in order to reduce the maximum current density and provide a uniform current path, the conventional technique uses an electrostatic discharge implant to widen the source / drain profile. Therefore, it can be seen in FIG. 2 that a conventional lightly doped drain-LDD 205 MOSFET includes a gate 201 and a sidewall spacer. ) 203, source and drain regions 207 and 209. In addition, an electrostatic discharge implant layer 211 is used to widen the profile of the source / drain. Generally speaking, the electrostatic discharge implant layer (imPlant) 211 has the same conductivity type as the source and drain electrodes, but has a lower concentration. Therefore, the electrostatic discharge implant layer 211 is an n-type implant, for example, a phosphorus-based implant layer is formed. Furthermore, although FIG. 2 shows only an n-type metal-oxide semiconductor device, P-type metal-oxide semiconductor transistors can be obtained by simply changing the type of the implanted layer. Known technical details can be found in A. Amerasekera and C. Duvvury, “ESD in Silicon Integrated Circuits,” page 180, published by John Wiley and Sons, Inc. (Please read the precautions on the back before filling this page) Loading -------- 丨 Order ---------- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ) 1 A7 B7 449831 4758twf.doc / 008 5. Description of the Invention (,) However, the conventional technology does not provide sufficient control of the snapback trigger voltage (snapback trigger v〇hage). The present invention proposes a technique for dealing with this problem. The invention discloses the structure of a gold-oxide semiconductor field effect transistor with improved dual electrostatic discharge (ESD) protection. The transistor includes: a gate structure, a sidewall spacer, a source / drain region with a lightly doped drain structure, a first electrostatic discharge implanted layer and a second electrostatic discharge implanted layer. The gate structure is composed of a thin gate oxide layer and a conductive layer thereon, which is arranged on a semiconductor substrate. The sidewall spacer is disposed on a sidewall of the gate structure. The lightly doped source / drain region of the lightly doped drain structure is located in the substrate directly below the sidewall spacer. The source region of the lightly doped source / drain region is located in the substrate next to the side wall spacer. The drain region is located in the substrate next to the other side wall spacer. The first electrostatic discharge implant layer is located directly below the source region and the drain region, and its impurity type is the same as that of the source region and the drain region. The second layer of ESD implantation layer is located directly below the first layer of ESD implantation layer. Its impurity pattern is opposite to that of the first layer of ESD implantation layer, and there is a vertical distance from the first layer of ESD implantation layer. In order to make the above-mentioned object of the present invention 'features and advantages more obvious and easy to understand, a preferred embodiment is given below in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings: Figure 1 is a study Know the schematic diagram of the electrostatic discharge protection circuit technology; Figure 2 is a schematic diagram of the semiconductor cross section of a transistor designed to reduce the effect of electrostatic discharge: Figure 3 is a schematic diagram of the semiconductor cross section of a transistor made according to the present invention 6 (Please read first For business matters on the reverse side, please fill in this page again.) -------- Order --------- line CV. Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economy This paper applies Chinese national standards (CNS ) A4 specification (210x297 mm) 449831 A7 4758twf.doc / 008 gy V. Description of the invention (V) Figure; and Figure 4 is a comparison between the present invention and the conventional technology in improving the snapback trigger voltage characteristics Data graph. (Please read the precautions on the back before filling in this page) Description of the diagram marks: 101: input pad 103: internal circuit 105: p-type metal oxide semiconductor 107: n-type metal oxide semiconductor 201, 301: gate electrode 203, 303: Spacer walls 205, 314: lightly doped sources / drain electrodes 207, 305: source regions 209, 307: drain regions 211: electrostatic discharge implant layer 300: substrate 309: first electrostatic discharge implant layer 311: Second electrostatic discharge implant layer 312: Conductor layer 313: Oxide layer Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 401: Known backlash voltage curve 403: Example of the backlash voltage curve of the present invention FIG. 3 A schematic cross-sectional view of a metal-oxide-semiconductor field-effect transistor manufactured according to the present invention. This metal oxide semiconductor field-effect transistor includes a gate structure 301, a source region 305 and a drain region 307 with a lightly doped drain structure 314. 7 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297). (Mm) A7 B7 4 4.9 831 4758twf.doc / 〇〇8 V. Description of the invention (dagger) and side wall spacicle (sidewall spaCe03) located on the side wall of the gate structure 301, where the gate structure 301 includes a conductor The layer 312 and the oxide layer 3Π. According to the conventional conventional technology, the sidewall spacer 303 is used to manufacture a lightly doped drain structure. A typical manufacturing method is to lightly dope after forming the gate structure 301 on the substrate 300. In the ion implantation process of the source / drain region 314, a sidewall spacer 303 is formed on the side wall of the gate structure 301. Then, the source region 305 and the drain region are respectively made by ion implantation. 307. In general, for a n-type gold oxide semiconductor with a thickness of 0.5 μm, the thickness of the gate oxide layer is about 120 angstroms. For the formation of lightly doped source / drain regions 314, phosphorus implantation can be used. (phosphorous implantation) up to a dose of 4xl013 / cm2 with an energy of 40 KeV The formation method of the source region 305 and the drain region 307 is, for example, an arsenic ion implantation method with an energy of 50 KeV to a dose of 3 × 1015 / cm2. In the next step, a separate ion implantation mask (a separate ion implant mask) to produce the first electrostatic discharge implant layer 309. The mask is formed to completely include the source region 305, the drain region 307, and the lightly doped drain region. The first layer of electrostatic discharge implant The layer 309 is to reduce the thermal Joule effect, and its impurity type is the same as that of the source region 305 and the drain region 307. An example of a preferred electrostatic discharge implantation layer 309 is to use a phosphorus-based type to reach 1xl at 50 KeV energy. Dose of 〇15 / cm2. Using the same mask as the ESD implant layer 309, a second ESD implant layer 311 is formed directly under the first ESD implant layer 309. However, its impurity type is the same as The source region 305 is opposite to the drain region 307, and is located below the source region 305 and the drain region 307. In the first electrostatic discharge implant layer 309 and the second electrostatic discharge implant layer Between 311 and δ This paper size applies to China National Standard (CNS) A4 specifications (2〗 0 X 2 97 Gongai) (Please read the notes on the back before filling out this page) '' il.— ί Order -------- Line _ printed by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, consumer cooperative Printed by the Consumer Cooperative 449B31, Α7 4758twf.doc / 008 5. Description of the invention (dagger) distance, this vertical distance (labeled d in Figure 3) determines the breakdown voltage. The greater the distance d, the greater the breakdown voltage. In a preferred example, the distance d is about 0.15 μm. In order to form a heavily doped and well-defined second electrostatic discharge implant layer 311, the implant used should be as heavy as possible. For example, a dose of 2 × 10 15 / cm 2 is doped with indium at an energy of 700 KeV. Alternatively, boron doping can be used. Compared with the conventional technology, the present invention adds a second electrostatic discharge implant layer 311, and by adjusting the distance between the second electrostatic discharge implant layer 311 and the first electrostatic discharge implant layer 309 in the manufacturing process, Can improve the snapback trigger voltage. Fig. 4 is a quantitative comparison diagram. In the figure, a solid line 401 indicates a conventional kickback voltage 'and a dashed line 402 indicates a kickback voltage of the present invention. In addition, although an n-type metal oxide semiconductor is described with reference to FIG. 3, in fact, as long as the doping pattern is changed, the present invention can be easily applied to a p-type metal oxide semiconductor. '. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention shall be determined by the scope of the attached patent application. . This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page). -------- Order ---- III-- line