經濟部中央標準局員工消赀合作社印製 449807 A7 ____B7_____ 五、發明説明（） 5-1發明領域： ，本發明係有關於一種薄膜電晶體（Thin Film T「anSiSt〇「‘ TFT)令陽極氧化（anodized oxidation)閘極 導線之方法與結構’特別是有關於一種薄膜電晶體液晶 顯不器（Liquid Crystal Display : LCD)之陽極氧化閘極導 線之方法與結構。 5-2發明背景： 在一般液晶顯示器（UqUjd Crystal Display: LCD) 中’用來控制每一個圖素（pixei)的是薄膜電晶體（Thin Film Tfansistor : TFT)，其結構如第一圖所示。電晶艘 是形成在底材10上。閘極1彳是直接在底材1〇上形成的 铭合金所構成的，並且有—層氧化鋁層12包圍住閘極 1 1。作為閘極絕緣層的是二氧化矽層1 3，此二氧化矽層 1 3亦可以用氮化矽層取代。介電層1 6則是用來作.為當 電壓施於閘極11上時，產生感應電子，以提供導通所需 的電子。亦即’介電層16為此電晶體的通道層，並且一 般都是由非晶矽（amorphous silicon)所構成。當電晶體 導通時，源極（source electrode) 18 與没極（drain elect rode)19之間，則由於介電層16中感應的電子而形 成通路。 一般而言，若閘極1 1外圍沒有氧f鋁保護’則會Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 449807 A7 ____B7_____ V. Description of the invention (5-1) Field of the invention: The present invention relates to a thin film transistor (Thin Film T "anSiSt〇" 'TFT) for anodizing (Anodized oxidation) method and structure of gate wires' Particularly, it relates to a method and structure of anodized gate wires of a thin film transistor (Liquid Crystal Display: LCD). 5-2 Background of the Invention: In general In the liquid crystal display (UqUjd Crystal Display: LCD), 'Thin Film Tfansistor (TFT)' is used to control each pixei. Its structure is shown in the first figure. The transistor is formed on the bottom Material 10. The gate electrode 1 彳 is made of an alloy directly formed on the substrate 10, and has an aluminum oxide layer 12 surrounding the gate electrode 11. The silicon dioxide layer is used as the gate insulating layer. 13. The silicon dioxide layer 13 can also be replaced by a silicon nitride layer. The dielectric layer 16 is used for the purpose. When a voltage is applied to the gate electrode 11, induction electrons are generated to provide conduction. Electron. The layer 16 is a channel layer of the transistor, and is generally composed of amorphous silicon. When the transistor is turned on, between the source electrode 18 and the drain elect rod 19, A path is formed due to the electrons induced in the dielectric layer 16. Generally speaking, if the periphery of the gate 1 1 is not protected by oxygen f aluminum, it will
I 產生閘極中的鋁往介電層16的方向滲透，甚至導致與汲 2 本紙張尺度適用中國國家標卑（CNS ) Λ4規格（210X 297公釐） (请先閲讀背面之注意事項再填寫本頁) • L------------------订----- 449807 經濟部中央標準局貝工消货合作社印紫 Α7 Β7 五、發明説明（） 極或源極的短路’此即所謂的H i Μ 〇 c k效應。所以一般薄 膜電晶體中的閘極結構，必須要有一個絕緣層將閘極包 覆，以避免Hi丨丨ock效應的產生。在第一圖中的閘極結構， 即是將閘極1 1以堅硬的氡化鋁層1 2與外界隔絕，以避 免Hillock效應。 傳統的方法是以電化學法產生氧化鋁層1 2，其方法 為將閘極1 1通以電壓’並將其浸入酸性溶液中，使此時 的閘極11作為氧化還原反應中的陽極（ari〇de)，所以在 此時的閘極1 1表面上會生一層氧化鋁層12，以形成陽 極氧化鋁金屬閘級導線。因為以此電化學法所產生的薄 膜時’很難控制其厚度，所以陽極氧化鋁金屬閘級導線 上的k層氧化铭層12的厚度並不均勻。當想要將整個液 aa顯不盗平面的閉極串聯起來時，則必須要再進行_ -欠 微影及钮刻技術，以在陽極氡化銘金屬閘級導線上佈出 接觸窗，使得源極/汲極金屬導線得以穿越氧化鋁層彳2， 以和閘級導線接觸而導通。 但是因為氧化鋁層12的厚度並不平均，而且要独 刻穿透堅硬的氧化鋁層1 2並不容易，所以在蝕刻氧化鋁 層1 2時’就必須非常小心的控制。在上述的傳統的方法 中’因為要減少產生H i丨丨〇 c k效應產生的機會，所以閘级 導線必須使用紹合金形成。然而在液晶顯示器日益大型 化的趨勢下，必須要盡量減少液晶顯示器掃描時間，亦 即要減少薄膜電晶體閘極連接後所形成的 阻。但是上述的間極結構中，是使用铭、合二 本紙浪尺度適中國(¾家操举（CNS ) Λ4規格（21 〇 X 297公鐘：） (請先閱讀背面之注意事項再填寫本頁) > 訂 449807 A7 B7 五、發明説明（） 線，其電阻約為純鋁之二倍，所以上述的閘極結構並不 適用於大型液晶顯示器。 另外，在上述的閘級導線結構之製程中，還必須在 蝕刻氧化鋁層1 2時，對蝕刻製程嚴密控制，否則很容易 產生對閘極鋁合金的過度蝕刻，或是產生另一種問題， 亦即，一些圖素之閘極11表面的氧化鋁層12尚未形成 接觸窗，導致要連接閘極以形成閘級導線時，這些圖素 的閘極1 1未被連接，所以這些圖素就不能動作，影響液 晶顯示器的生產ί率。而且此增加出來的微影及蝕刻製 .程會導致製造時成及成本的增加，另外，因此一增加的 蝕刻製程是要蝕刻陽極氧化鋁金屬閘級導線，其蝕刻技 術較為困難，而且製程穩定性較難控制，所以更會影響 製程良率。 5-3發明目的及概述： 經滴部中央標準局負工消費合作社印聚 (請先間讀背面之注意事項再填寫本頁) 鑒於上述之發明背景中，傳統的薄膜電晶體閘.極結 構所組成之閘極鋁合金導線製程中，會使得薄膜電晶體 之製程增加一個對陽極氧化鋁金屬閘級導線之蝕刻，以 致製程不穩定而降低良率，所以本發明之第一個目的在 將製程簡化，避免對陽極氧化鋁金屬閘級導線之蝕刻， 以減少光罩之使用以及製程之不穩定性，並提高良率。 本發明的另一目的在改變薄膜電晶體之閘極結構， 用以使得薄膜電晶體之閘極不會因為長，期使用，而再度 產生Hillock效應。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 經滴部中决標苹扃兵工消贽合作社印製 4 4 9 807 A7 B7____ 五、發明説明（） 根據以上所述之目的’本發明提供了一種形成電晶體之 閘極之方法，該方法至少包含下列步驟：首先，形成第 一導t層於透明底材上’接著形成第二導電層於第一導 電層上。然後形成光阻圖案層於第二導電層上，並接著 蝕刻第二導電層。接著蝕刻第一導電層，使此第一導電 層與此第二導電層鄰接面之面積小於此第一導電層與此 透明底材鄰接面之面積。再度触刻第二導電層使得第二 導電層與光阻圖案層鄰接面之面積小於第二導電層與第 一導電層鄰接面之面積。然後形成介電層於第一 ^電層 表面未被第二導電層覆蓋之部分，最後去除此光阻圖案 層，以形成此電晶體之閘極。 然後沉積第二介電層於透明底材、第一介電層以及 第二導電層上，以形成此薄膜電晶體之閘極絕緣層（gate insulator)。接著沉積一第三介電層於第二介電層上，以 使得此電晶體導通時，提供導通所需電荷，此地三介電 層可以是非晶矽的介電層。最後，定義第四介電層於第 三介電層上，以形成此電晶體之汲極以及源極，最.後在 製作源極以及閘極金屬層與保護層，而完成此具有本發 明之閘極結構之薄膜電晶體的製作。其中的第四介電層 可以是以η型非晶矽所組成。 5-4圖式簡單說明： 第一圖為傳統閘極結構的薄膜電晶體之剖面圖，其 中的閘極是經過傳統陽極氧化處理，而為氧化鋁所包圍 本紙張尺度適圯中國國家摞準（CNS ) Λ4規格（210X29?公楚） (請先閱讀背面之注意事項再填寫本頁)I Generate the penetration of the aluminum in the gate to the dielectric layer 16, and even lead to the paper size. This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) (Please read the precautions on the back before filling (This page) • L ------------------ Order ----- 449807 Beizi Consumer Goods Cooperatives, Purple A7, B7, Central Standards Bureau, Ministry of Economic Affairs The short circuit of the electrode or source is called the H i Mock effect. Therefore, the gate structure in general thin film transistors must have an insulating layer to cover the gate to avoid the Hi 丨 ock effect. The gate structure in the first figure is to isolate the gate 11 from the outside by a hard aluminum halide layer 12 to avoid the Hillock effect. The traditional method is to generate the alumina layer 12 by electrochemical method. The method is to apply the gate electrode 11 to a voltage 'and immerse it in an acidic solution, so that the gate electrode 11 at this time serves as the anode in the redox reaction ( ariOde), so a layer of aluminum oxide 12 will be formed on the surface of the gate 11 at this time to form an anodized aluminum metal gate-level wire. Since it is difficult to control the thickness of the thin film produced by this electrochemical method, the thickness of the k-layer oxide layer 12 on the anodized aluminum metal gate wire is not uniform. When you want to connect the closed poles of the entire liquid aa display plane in series, you must perform _-under-lithography and button engraving technology to lay out contact windows on the anode gate metal gate wire, so that The source / drain metal wire can pass through the alumina layer 彳 2 to be in contact with the gate-level wire to conduct. However, since the thickness of the alumina layer 12 is not uniform and it is not easy to penetrate the hard alumina layer 12 at once, it is necessary to control the alumina layer 12 very carefully. In the above-mentioned conventional method, 'the gate wire must be formed by using a Sau alloy because the chance of generating the H i 丨 〇c k effect is reduced. However, with the increasing trend of liquid crystal displays, it is necessary to reduce the scanning time of the liquid crystal display as much as possible, that is, to reduce the resistance formed after the thin film transistor gate is connected. However, in the above-mentioned interpolar structure, the paper size and the size of the paper are suitable for China (¾ Family Exercise (CNS) Λ4 specification (21 〇 297 clocks :)) (Please read the precautions on the back before filling in this page ) > Order 449807 A7 B7 V. Description of the invention () wire, its resistance is about twice that of pure aluminum, so the above-mentioned gate structure is not suitable for large-scale liquid crystal displays. In addition, in the above-mentioned gate-level wire structure manufacturing process In addition, the etching process must be tightly controlled when the aluminum oxide layer 12 is etched; otherwise, it is easy to cause excessive etching of the gate aluminum alloy, or another problem, that is, the surface of the gate 11 of some pixels The aluminum oxide layer 12 has not yet formed a contact window. When the gates are to be connected to form gate-level wires, the gates 11 of these pixels are not connected, so these pixels cannot operate, which affects the production rate of the liquid crystal display. And this added lithography and etching process will lead to an increase in manufacturing time and cost. In addition, an additional etching process is to etch anodized aluminum metal gate-level wires, and its etching technology is relatively difficult. It is difficult, and the stability of the process is difficult to control, so it will affect the yield of the process. 5-3 Purpose and summary of the invention Page) In view of the above background of the invention, the traditional thin film transistor gate electrode structure made of aluminum alloy wire process will make the thin film transistor process an etched anodized aluminum metal gate wire, so that The process is unstable and the yield is reduced, so the first object of the present invention is to simplify the process and avoid the etching of anodized aluminum metal gate-level wires, so as to reduce the use of photomasks and the instability of the process and improve the yield. Another object of the present invention is to change the gate structure of the thin film transistor, so that the gate of the thin film transistor will not have the Hillock effect again due to long-term use. This paper standard applies to the Chinese National Standard (CNS) A4 specifications (210X 297 mm) Printed by the final award of the Ministry of Agriculture, Ping An Ordnance Industry Cooperative Cooperative 4 4 9 807 A7 B7____ 5. Description of the invention () According to the above Objective 'The present invention provides a method for forming a gate electrode of a transistor. The method includes at least the following steps: First, a first conductive t layer is formed on a transparent substrate', and then a second conductive layer is formed on the first conductive layer. Then, a photoresist pattern layer is formed on the second conductive layer, and then the second conductive layer is etched. Then, the first conductive layer is etched so that the area adjacent to the first conductive layer and the second conductive layer is smaller than the first conductive layer The area of the surface adjacent to this transparent substrate. The second conductive layer is etched again so that the area of the adjacent surface of the second conductive layer and the photoresist pattern layer is smaller than the area of the adjacent surface of the second conductive layer and the first conductive layer. Then a dielectric is formed Layer on the surface of the first electrical layer not covered by the second conductive layer, and finally removing the photoresist pattern layer to form the gate of the transistor. A second dielectric layer is then deposited on the transparent substrate, the first dielectric layer and the second conductive layer to form a gate insulator of the thin film transistor. Next, a third dielectric layer is deposited on the second dielectric layer so that when the transistor is turned on, a charge required for conduction is provided. The three dielectric layers here may be a dielectric layer of amorphous silicon. Finally, a fourth dielectric layer is defined on the third dielectric layer to form a drain and a source of the transistor, and finally a source and a gate metal layer and a protective layer are manufactured, and the present invention is completed. Fabrication of thin film transistor with gate structure. The fourth dielectric layer may be composed of n-type amorphous silicon. Figure 5-4 is a simple explanation: The first figure is a cross-sectional view of a thin-film transistor with a traditional gate structure. The gate electrode is traditionally anodized and surrounded by alumina. The paper is suitable for Chinese standards. (CNS) Λ4 specification (210X29? Gongchu) (Please read the precautions on the back before filling this page)
449807 經濟部中央標準局兵工消t合作社印5;: A7 B7 五、發明説明（） 的閘極結構。 第二圖至第七圖為根據本發明所提供的方法所形 成薄膜電晶體的各個步驟之剖面圖。 第二圖為在玻璃底材上形成閘級金屬層以及缓衝 金屬薄膜後之剖面圖。 第三圖為在緩衝金屬薄膜上形成光阻圖案層之後 的剖面圖。 第四圖為以上述光阻圖案層為遮罩，先後分別對缓 衝金屬薄膜以及閑級金屬層蝕刻之盔的晶圓剖面圖。 第五圖為以上述經過蝕刻後之光阻圖案層為遮罩， 再度對缓衝金屬薄膜蝕刻之後的晶圓剖面圖。 第六圖為在閘級金屬層未被該蝕刻後的缓衝金屬薄 膜覆蓋的部分外表上形成氧化鋁，並且將光阻圖案層去 除，以形成本發明的閘極結構之後的晶圓剖面圖。 第t圖為根據本發明的閘極結構所形成的薄膜電晶 體之剖面圖。 5·5發明詳細說明： 為了在避免 H m 0 c k效應的同時，盡量減少閘極導 線之電阻，以符合大型液晶顯示器之需要。所以本發明 提供一種薄膜電晶體液晶顯示器之陽極氧化閘級導線製 程及結構，使得本發明的閘極結構之製程中，不必蝕刻 氧化鋁層，故可以避免對蝕刻氧化鋁製，程的嚴苛要求， 藉以提高液晶顯示器的生產良率。甚至，本發明所提供 本紙張尺度適;1]中國國家標準（<：奶）八4規格（2!0乂 297公釐） (诗-¾讀背面之注意事項再填芎太頁)449807 Central Standards Bureau of the Ministry of Economic Affairs, Military Industry Cooperative Press 5 ;: A7 B7 V. Gate structure of the invention (). The second to seventh figures are cross-sectional views of each step of forming a thin film transistor according to the method provided by the present invention. The second figure is a cross-sectional view after a gate metal layer and a buffer metal film are formed on a glass substrate. The third figure is a cross-sectional view after a photoresist pattern layer is formed on the buffer metal film. The fourth figure is a cross-sectional view of a wafer with the above-mentioned photoresist pattern layer as a mask, and a buffer metal film and a helmet-level metal layer etching mask respectively. The fifth figure is a cross-sectional view of the wafer after the buffer metal film is etched again using the photoresist pattern layer after the etching as a mask. The sixth figure is a cross-sectional view of a wafer after forming alumina on a portion of the gate metal layer that is not covered by the etched buffer metal film and removing the photoresist pattern layer to form the gate structure of the present invention. . Fig. T is a cross-sectional view of a thin film transistor formed by a gate structure according to the present invention. The invention of 5.5 is explained in detail: In order to avoid the H m 0 c k effect, the resistance of the gate wires is minimized to meet the needs of large-scale liquid crystal displays. Therefore, the present invention provides a process and structure of anodized gate-grade wires for a thin-film transistor liquid crystal display, so that in the process of the gate structure of the present invention, it is not necessary to etch the alumina layer, so that the severe process of etching alumina can be avoided. It is required to improve the production yield of liquid crystal displays. Furthermore, the paper provided by the present invention is suitable for this paper; 1] Chinese national standard (<: milk) 8 4 size (2! 0 乂 297mm) (Poem-¾ Read the notes on the back and fill in the 芎 page)
經1¾-部中央標準局貝J..消贽合作社印架 449807 A7 B7 五、發明説明（） 的閘極結構中的閘極邊緣形狀不是直角，所以即使經過 一段長時間使用後*也不會再度產生Η丨Μ 〇 c k效應。所以 可以增加液晶顯示器的使用壽命。 本發明用來形成薄膜電晶體的方法主要是以不同的 製程形成不同於傳統的閘極結構，以形成本發明中的閘 級導線。參考第二圊，首先形成一第一導電層21於底材 22上，接著形成一第二導電層23於第一導電層21上。 其中底材2 2之材質係由玻璃或是透明樹脂所構成。依據 本發明的實施例，第一導電層是由純鋁所形成，然而也 可以鋁合金等金屬形成。而第二導電層在本發明的實施 例中，是以藏鍍而成的一個缓衝金屬薄臈'係由鉻（C r)、 鈦（Ti)、顧（Mo)、組（Ta)、以及鶴化翻（MoW)等金屬所構 成。接著參考第三圖，以微影步驟形成一光阻圖案層24 於第二導電層23上。 接著，參考第四圖，以光阻圖案層 24為遮罩，對 第二導電層2 3，亦即對缓衝金屬薄膜進行蝕刻，其蝕刻 製程可以為傳統的乾式蝕刻或是濕式蝕刻。在本發明的 實施例中，若第二導電層是由鉬（Μ 〇)所構成，則可以使 用C F4為蝕刻氣體，對第二導電層2 3進行乾式蝕刻。 因為第二導電層是以濺鍍而成的緩衝金屬薄膜，所以在 此蝕刻步驟中，不但有縱向蝕刻，也有橫向蝕刻，縱向 蝕刻率與横向蝕刻率之比為1 : 1，所以使得第二導電層 23退到光阻圖案層24下。 然後以傳統的濕式或是乾式蝕刻，、對第一導電層進 本紙張尺度適州中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 &消部中次標導局負工消货合作'不印掌 449 80 7 A7 B7 五、發明説明（） 行蝕刻’在本實施例中是以傳統鋁的蝕刻劑對第一導電 層進行蝕刻，例如BCI3 + CI2 + CHCI3 + N2。因為此蝕刻步 驟中，；縱向蝕刻率與橫向蝕刻率之比為1 : 0.7，所以晶 蝕刻之後的第一導電層21的外形如第四圖中的第一導電 層21之外形所示，第一導電層21與底材22的鄰接面之 面積大於第一導電層與該光阻圖案層 24的鄰接面之面 積。 接著是以一個傳統的濕式或是乾式蝕刻步驟，以經 過第一次蝕刻的光阻圖案層24為遮罩，再對第二導電層 2 3進行一次蝕刻。因為光阻圖案層2 4，已經經過兩次蝕 刻，所以其寬度已經減小。故在此一蝕刻步驟時，以光 阻圖案層24為遮罩，對第二導電層21進行蝕刻。因為 此時的光阻圖案層24體積已經變小，而且光阻圖案層24 的邊緣已經變薄，所以在此次蝕刻中，會導致第二導電 層23與光阻圖案層24鄰接面面積小於第二導電層23與 第一導電層21鄰接面之面積，所以所形成的第二導電層 2.3之形狀如第五圖中所示。 接著，參考第六圖，以陽極氧化法將第一導電層外 表未被第二導電層23覆蓋的部分，形成第一介電層27, 使得第一介電層27將第一導電層21完全包圍，並且第 二介電層27是由氧化矽或是氮化矽所組成，且其邊緣不 是直角，所以不會有如習知技術中薄膜電晶體使用壽命 減少的問題。然後將光阻圖案層24去除，以形成本發明 所提供的薄膜電晶體之閘級結構之製程丨。在本發明的閘 本紙張尺度適州中國國家標準（CNS ) Λ4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -丁 經消-部中央摞準局員工消费合作社印製 449 80 γ A7 B7 五、發明説明（.） 極結構中，第一導電層21，是被第二導電層23以及第 一介電層27所完全包圍，所以不會有Hillock效應產生。 然後將各個薄膜電晶體的閘極結構串接，就可以獲得本 發明中所欲形成的閘級導線。因為第二導電層2 3具有導 電性，所以要將各個薄膜電晶體閘極結構串接時，不需 要對第二導電層2 3再進行一次微影及蝕刻以形成閘級導 線接觸窗的步驟，所以本發明可以減少製程時間。並且 因為本發明避免了對陽極氧化鋁金屬閘級導線之蝕刻， 所以較好控制製程穩定性，故可以減少蝕刻過程的失 誤，並提高製程良率。 然後要形成薄膜電晶體完整結構時，可以用傳統方 法形成薄膜電晶體的各個部分。例如，接著形成一第二 介電層3 0於上述的閘極結構以及底材2 2上。此第二介 電層3 0的目的是作為薄膜電晶體的閘極絕緣層之用，在 本實施例中是以二氧化矽所構成。然後以傳統微影及蝕 刻方法在第二介電層30上形成第三介電層35，在本發 明的實施例中，第三介電層 3 5雖為非晶矽（a m 〇 r p h 〇 u s s i I i c ο η)所構成，然亦可以複晶矽（p ο I y c r y s t a丨I i n e s i I i c ο η) 構成。第三介電層 35的目的是在提供薄膜電晶體導通 時，在通道上產生感應電子以形成通道。 然後形成第三導電層，並定義出薄膜電晶體的源極 4 1以及汲極4 2。接著形成保護層5 0，以將薄膜電晶體 的源極41、汲極4 2以及第三介電層3 5與外界電性隔 絕，材料乃為氮化_矽。則依此一製程完成的’具有本發 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁) -5According to 1¾-Ministry of Standards of the People's Republic of China, J .. Consumer Cooperative Press Frame 449807 A7 B7 V. The gate shape of the gate structure of the invention () is not right-angled, so even after a long period of use *, it will not The Mock effect was again generated. Therefore, the service life of the liquid crystal display can be increased. The method for forming a thin film transistor of the present invention is mainly to form a gate structure different from the traditional gate structure by different processes to form the gate-level wire in the present invention. Referring to the second step, a first conductive layer 21 is first formed on the substrate 22, and then a second conductive layer 23 is formed on the first conductive layer 21. The material of the substrate 22 is made of glass or transparent resin. According to the embodiment of the present invention, the first conductive layer is formed of pure aluminum, but may be formed of a metal such as an aluminum alloy. In the embodiment of the present invention, the second conductive layer is a buffer metal thin film made of Tibetan plating and is made of chromium (Cr), titanium (Ti), Gu (Mo), group (Ta), And made of metal such as Crane Chemical (MoW). Referring to the third figure, a photoresist pattern layer 24 is formed on the second conductive layer 23 by a lithography step. Next, referring to the fourth figure, with the photoresist pattern layer 24 as a mask, the second conductive layer 23, that is, the buffer metal film is etched. The etching process may be conventional dry etching or wet etching. In the embodiment of the present invention, if the second conductive layer is made of molybdenum (MO), the second conductive layer 23 can be dry-etched using C F4 as an etching gas. Because the second conductive layer is a buffer metal film formed by sputtering, in this etching step, there are not only vertical etching but also horizontal etching. The ratio of the vertical etching rate to the lateral etching rate is 1: 1, so that the second The conductive layer 23 is retracted under the photoresist pattern layer 24. Then use traditional wet or dry etching to enter the paper size of the first conductive layer into the state of China State Standards (CNS) A4 (210X 297 mm) (Please read the precautions on the back before filling this page) Order & Consumers ’Intermediate Standards Bureau's Work and Consumption Cooperation“ No Print 449 80 7 A7 B7 V. Description of the Invention () Line Etching ”In this embodiment, the first conductive layer is treated with a traditional aluminum etchant. Etching is performed, for example, BCI3 + CI2 + CHCI3 + N2. In this etching step, the ratio of the longitudinal etching rate to the lateral etching rate is 1: 0.7, so the shape of the first conductive layer 21 after the crystal etching is shown as the outer shape of the first conductive layer 21 in the fourth figure. The area of the abutting surface of the conductive layer 21 and the substrate 22 is larger than the area of the abutting surface of the first conductive layer and the photoresist pattern layer 24. Then, the second conductive layer 23 is etched by a conventional wet or dry etching step, using the photoresist pattern layer 24 after the first etching as a mask. Since the photoresist pattern layer 24 has been etched twice, its width has been reduced. Therefore, in this etching step, the second conductive layer 21 is etched with the photoresist pattern layer 24 as a mask. Because the volume of the photoresist pattern layer 24 has become smaller and the edges of the photoresist pattern layer 24 have become thinner, the area of the adjacent surface of the second conductive layer 23 and the photoresist pattern layer 24 will be smaller in this etching. The area of the adjacent surface of the second conductive layer 23 and the first conductive layer 21, so the shape of the formed second conductive layer 2.3 is as shown in the fifth figure. Next, referring to the sixth figure, the first conductive layer 21 is formed by partially covering the surface of the first conductive layer that is not covered by the second conductive layer 23 by anodization, so that the first dielectric layer 27 completely completes the first conductive layer 21. It is surrounded, and the second dielectric layer 27 is composed of silicon oxide or silicon nitride, and its edges are not at right angles, so there is no problem of reducing the service life of the thin film transistor as in the conventional technology. Then, the photoresist pattern layer 24 is removed to form a gate-level structure of the thin film transistor provided by the present invention. In the present invention, the Zhaben paper size is in accordance with the China National Standard (CNS) Λ4 specification (210X297 mm) (please read the precautions on the back before filling out this page) Manufacturing 449 80 γ A7 B7 V. Description of the invention (.) In the electrode structure, the first conductive layer 21 is completely surrounded by the second conductive layer 23 and the first dielectric layer 27, so there will be no Hillock effect. Then, the gate structure of each thin film transistor is connected in series to obtain the gate-level wire formed in the present invention. Because the second conductive layer 23 is conductive, when the thin film transistor gate structures are connected in series, it is not necessary to perform another lithography and etching on the second conductive layer 23 to form a gate-level wire contact window. Therefore, the present invention can reduce the process time. And because the invention avoids the etching of the anodized aluminum metal gate-level wires, the process stability is better controlled, so errors in the etching process can be reduced, and the process yield can be improved. When the complete structure of the thin film transistor is to be formed, various parts of the thin film transistor can be formed by a conventional method. For example, a second dielectric layer 30 is then formed on the gate structure and the substrate 22 described above. The purpose of this second dielectric layer 30 is to serve as a gate insulating layer for a thin film transistor. In this embodiment, it is made of silicon dioxide. A third dielectric layer 35 is then formed on the second dielectric layer 30 by conventional lithography and etching methods. In the embodiment of the present invention, although the third dielectric layer 35 is amorphous silicon (am 〇rph 〇ussi I ic ο η), but can also be composed of polycrystalline silicon (p ο I ycrysta 丨 I inesi I ic ο η). The purpose of the third dielectric layer 35 is to provide induced electrons on the channel to form a channel when the thin film transistor is turned on. A third conductive layer is then formed, and a source 41 and a drain 4 2 of the thin film transistor are defined. Next, a protective layer 50 is formed to electrically isolate the source 41, the drain 42, and the third dielectric layer 35 of the thin film transistor from the outside, and the material is silicon nitride. Then the “paper with this hairpin” completed according to this process is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) (Please read the precautions on the back before filling this page) -5
經濟'叫中央標準局員工消费合作社印製 ^ ^ y α 0 j 44980 7 Α7 Β7 五、發明説明（） 明之閘極結構之薄膜電晶體具有製程容易，可以省去陽 極氧化鋁金屬閘極導線之蝕刻難題，並且因為本發明的 閘極結構，可以延長薄膜電晶體使用壽命之優點。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之申請專利範圍；凡其它未脫離本發明所揭 示之精神下所完成之等效改變或修飾，均應包含在下述 之申請專利範圍内。 本紙張尺度適用中國國家標準（<1'肥）八4現格（2丨0>< 297公釐） (請先閱讀背而之注意事項再填寫本百；)The economy is called printed by the Central Standards Bureau's Consumer Cooperative ^ ^ y α 0 j 44980 7 Α7 Β7 V. Description of the invention () The thin-film transistor with a bright gate structure has an easy manufacturing process and can eliminate the need for anodized aluminum metal gate wires. Etching problems, and because of the gate structure of the present invention, the service life of the thin film transistor can be extended. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application. This paper size applies to the Chinese national standard (< 1'Fat) 8 4 grid (2 丨 0 > < 297 mm) (please read the precautions on the back before filling this one hundred;)