TW448609B - Oscillation circuit - Google Patents

Oscillation circuit Download PDF

Info

Publication number
TW448609B
TW448609B TW88104189A TW88104189A TW448609B TW 448609 B TW448609 B TW 448609B TW 88104189 A TW88104189 A TW 88104189A TW 88104189 A TW88104189 A TW 88104189A TW 448609 B TW448609 B TW 448609B
Authority
TW
Taiwan
Prior art keywords
transistor
base
current source
constant current
circuit
Prior art date
Application number
TW88104189A
Other languages
Chinese (zh)
Inventor
Masatoshi Tsuji
Hiroyuki Ashida
Tamotsu Suzuki
Satoshi Kawahara
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Application granted granted Critical
Publication of TW448609B publication Critical patent/TW448609B/en

Links

Landscapes

  • Oscillators With Electromechanical Resonators (AREA)

Abstract

An oscillation circuit is provided to shorten the oscillation rise time required for the oscillation output to be brought into an oscillation state at a prescribed output voltage level and a prescribed oscillation frequency after the application of the power voltage. An oscillation circuit having a piezoelectric vibrator such as a quartz crystal, oscillation capacitors and a feedback amplification transistor comprises a constant-current source connected in series with the emitter of the transistor, thereby shortening the oscillation rise time.

Description

448609 A7 B7 五、發明說明(1 ) 【發明所屬的技術領域】 · 本發明係關於使用水晶振盪元件等壓電振盪元件以低 電壓電源,獲得穩定之低消費電力及一定振幅之振盪輸出 的振盪電路者。 【習用技術】 水晶振盪元件等壓電振盪元件之振盪電路,係使用於 做爲各種電子機器的頻率及時間等之基準。該電子機器, 尤係攜帶電話機等攜帶機器,爲小型化及輕量化,同時, 爲使電力容量受限之電池等電源能有效利用,須減低其消 耗電力。 因此,如第19圖所示之攜帶用電話機等攜帶用通信 機,係於待機狀態時,以間歇方式導通電源,使之與基地 局通訊以確認有無收訊,如爲收訊即轉爲連續通電方式, 由此間歇供電減低電力之消耗。 第17圖係表示使用於水晶振盪電路之溫度補償水晶振 盪電路〔TCXO〕的一般電路圖。其中,7^爲NPN型電晶 体’ Rc爲集極電阻、RE爲射極電阻,、 R2爲分壓電阻, C, ' C2爲電容器,X爲水晶振盪元件,Rt ' Ct爲模擬溫度 補償電路特性的電阻及電容。又,B係電池,5#爲開關,448609 A7 B7 V. Description of the invention (1) [Technical field to which the invention belongs] · This invention relates to the use of piezoelectric oscillation elements such as crystal oscillation elements to obtain stable low power consumption and oscillation with a certain amplitude of oscillation output from a low voltage power source. Circuit person. [Conventional technology] Oscillation circuits for piezoelectric oscillators, such as crystal oscillators, are used as a reference for frequency and time of various electronic devices. This electronic device, especially a portable device such as a mobile phone, is miniaturized and lightened. At the same time, in order to effectively use a power source such as a battery with limited power capacity, it is necessary to reduce its power consumption. Therefore, as shown in Figure 19, the portable communication devices, such as portable telephones, are in the standby state, and the power is turned on intermittently to communicate with the base station to confirm the reception. If it is received, it will be continuous. The power-on mode reduces the power consumption by intermittent power supply. Fig. 17 is a general circuit diagram of a temperature-compensated crystal oscillator circuit [TCXO] used in the crystal oscillator circuit. Among them, 7 ^ is an NPN transistor, Rc is a collector resistor, RE is an emitter resistor, R2 is a voltage dividing resistor, C, 'C2 is a capacitor, X is a crystal oscillation element, and Rt' Ct is an analog temperature compensation circuit. Characteristics of resistance and capacitance. Also, B series battery, 5 # is the switch,

Cc係對負載電路之耦合電容器。 如第17圖,開關Sw接通時,電源電壓vcc由電阻R〆R2 分壓,而將分壓點之電位供於電晶体TR基極。由此,使電 晶体T R動作’則於集極電阻R c及射極電阻E有直流電流流 過以設定所定之直流偏壓。 本紙張尺度適用令國國家標準(CNS)A4規格(210 x 297公釐) ~ 1 310417 (請先閱讀背面之注意事項再填寫本頁) 裝 ----:1訂*--------線 經濟部智慧財產局員工消費合作社印製 448 609 A7 B7 五、發明說明(2 ) (請先閱讀背面之注意事項再填寫本頁) —方面,上述分壓點之電位施加於水晶振盪元件X、 溫度補償電阻RT、溫度補償電容器CT、同時亦施加於電容 器C t、 C2,使水晶振盪電路開始振盪。振盪信號則經連 接於集極的耦合電容器Cc,輸至負載電路。 如上構成之振盪電路•在施加電源電壓Vcc後爲使振 盪輸出達到額定輸出電壓位準及額定振盪頻率(±1 ppm) 之振盪狀態,須有相當長之振盪上升時間1^。第18圖係以 水晶振盪電路表示此狀態,其振盪上升時間Ts,通常約需 4至5ms。該水晶振盪電路之振盪上升時間Ts,較使用瓷質 〔celamic〕振盪元件等其他壓電振盪元件振盪電路之時間 爲長,故於使用水晶振盪元件之水晶振盪電路,成爲問題。 又於習用水晶振盪電路等之振盪電路係以個別零件組 裝成電路之所謂分立兀件電路(discrete circuit)構成,必 然有小型化上的限度。因此,於要求小型化,輕量化之攜 帶式電子機器,使用水晶振盪電路等振盪電路時,在其小 型化上成問題。 【發明所欲解決之問題】 經濟部智慧財產局員工消費合作社印製 在該振盪上升時間Ts*,振盪輸出不在額定輸出電壓 位準,及額定振盪頻率之振盪狀態,故不能將振遙輸出作 爲送收訊頻率之基準頻率信號使用。因此|在施加電源_ 壓Vcc後,須儘佚使振盪輸出上升至額定振邊位準,及額 定振盪頻率。當然,在該振盪上升時間Ts中,亦消耗電力, 該電力消耗爲無效電力t故爲有效地利用電源之容量,有 必要縮短該時間Ts。 本紙張尺度適用中®國家標準(CNS)A4規格(2〗〇x 297公釐) ' 2 310417 448609 A7B7 經濟部智慧財產局員工消费合作社印製 五、發明說明(3 ) 又’以個別零件組裝構成電路,所謂之分立元件構成 的水晶振盪電路等振盪電路,業已到達小型化,輕量化界 限,爲適合於攜帶式電子機器之使用,須以其他不同方法, 圖謀振盪電路本身之小型化。 因此’本發明之目的係提供一種,於施加電源電壓後, 能縮短振盪輸出到達額定輸出電壓位準及額定振盪頻率之 振盪狀態所需之振盪上升時間Ts的振盪電路《 又於1提供縮短振盪上升時間Ts,同時在電源電壓變動 時,亦使振盪頻率之變化爲極小,且能改善振盪頻率對電 源電壓依存性之振盪電路爲目的》 又於縮短振盪上升時間1^,改善振盪頻率對電源電壓 依存性之同時,提供一種於周圍溫度變化時,亦能使振盪 輸出位準及振邊輸出振幅無顯著變化之改善振盪輸出位準 及輸出振幅之溫度依存性的振盪電路爲目的。 縮短振盪上升時間Ts,同時亦獲得一種小型化、輕量 化之振盪電路爲目的。 【發明解決問題之手段】 申請專利範圍第1項記載之振盪電路,係於含有壓電 振盪元件,振盪用電容器及回授放大用電晶体之振盪電路 中。將上述電晶体之射極,串聯於定電流源。 於此構成中,自施加電源電壓Vcc1至振盪輸出成爲 額定輸出電壓位準,及額定振盪頻率〔±1 ppm〕之振盪狀 態,所需之振盪上升時間Ts ’係較習用以使用射極電阻振 盪電路之振盪上升時間1^特短。 1 I ----I ^ i I ---------^ (請先間讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(2】〇χ297公釐) 3 310417 448609 at Β7 五、發明說明(4 ) (請先閱讀背面之注意事項再填寫本頁) 申請專利範圍第2項記載之振盪電路,係由:.壓電振 盪元件;將基極連接於壓電振盪元件之電晶体:連接於電 源間且對上述電晶体之基極施加偏壓電位之電阻器;設於 上述電晶體基極與射極間之第一電容器:設於上述電晶体 射極與電源之一端間的定電流源;與該定電源並聯設置之 第2電容器以及設在上逾電晶体集極與電源另端間的輸出 電阻構成。 如上述構成,則與申請專利範圍第1項之記載一樣, 自施加電源電壓Vcc,至振盪輸出成爲額定輸出電壓位準, 及額定振鹽頻率〔±1 ppm〕之振Μ狀態,所需之振邊上升 時間Ts,係較習用使用射極電阻振盪電路之振盪上升時間 T s爲短β 又因定常振盪狀態中之振盪位準及振盪頻率穩定,且 不增加電力消耗。 經濟部智慧財產局員工消費合作社印製 申請專利範圍第3項記載之振盪電路,係由:壓電振 盪元件;將基極連接於壓電振盪元件之第1電晶体;與該 第1電晶体串聯之第2電晶体;連接於電源間,分別向上述 第1電晶体的基極及第2電晶体之基極施加偏壓電位之電 阻;設於上述第1電晶体基極與射極間的第1電容器:設在 上述第1電晶体射極與電源一端間的定電流源:與該定電 流源並聯之第2電容器以及設於上述第2電晶体集極與電源 另端間的輸出電阻構成。 如依此構成可獲得與申請專利範圍第2項記載之相同 效果。同時,將第1電晶体之集極與第2電晶体叠接 本紙張义度適用中國國家標準(CNS)A4規格(210x297公釐) 4 310417 448609 Α7 Β7 五、發明說明(5 ) (請先閱讀背面之注意事項再填寫本頁) 〔cascode〕,構成由該第2電晶体之集極與集極電·阻之連 接點,取出振盪輸出的方式。因此由第2電晶体之緩衝 〔buffer〕放大機能,使連接於輸出端之負載變化時,可 將負載變動之影響由做爲緩衝放大器機能的第2電晶体緩 和·因此,於負載變動時,亦能使振盪電路之振盪在輸出 電壓位準振盪頻率更爲穩定之情彤下進行。 申請專利範圍第4項記載之振盪電路,係由:壓電振 盪元件^將基極連接於壓電振盪元件之電晶体:連接於電 源間,將偏壓電位供於上述電晶体基極電阻;設於上述電 晶体之基極與射極之間的第1電容器:設於上述電晶体射 極與一電源端間的定電流源,及並聯於該定電流源之第2 電容器構成,且由上述電晶体之射極與定電流源之連接點 輸出 上述之構成可獲得與申請專利範圍第2項記載之相同 效果。且因係將電晶体射極側做爲水晶振盪電路輸出信號 之取出點,因此不需於電晶体之集極與電源間,設置集極 電阻,而使水晶振盪電路得以小型化及輕量化β 經濟部智慧財產局員工消費合作社印製 申請專利範圍第5項記載之振盪電路,係由:壓電振 盪元件:將基極連接於壓電振盪元件之第1電晶体;與該 第1電晶体串聯之第2電晶体;設於該第2電晶体基極與~ 電源端間之偏壓用定電流源,或設在該第2電晶体基極與 電源另端間之偏壓用定電壓源;分別設於上述第1電晶体 基極與上述第2電晶体基極間,及上述第1電晶体基極與電 源另一端間的偏壓電阻,設於上述第1電晶體基極與射極 本紙張尺度適用中國國家標準(CNSM4規格(210 X 297公楚) 5 310417 448609 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(6 ) 間的第1電容器;設在上述第1電晶体射極與另端電源間的 定電流源;與該定電流源並聯之第2電容器以及設在上述 第2電晶体集極與電源一端間的輸出電阻構成。 如此該構成可獲得與申請專利範圔第3項記載之相同 效果。同時,又以在第2電晶体基極與一電源端間之偏壓 用定電流源,或設在第2電晶体基極與另一電源端間之偏 壓用定電流源,及分別在上述第1電晶体基極與第2電晶体 基極由/以及上述第1電晶体基極與另一電源端間設置偏 壓電阻,可使第1電晶体及第2電晶体之基極偏壓保持於定 位。因此,即使電源電壓變動,亦可將第1電晶体及第2電 晶体之基極偏壓保持於定値。以使振盪電路之振盪頻率的 變化顯著減少,故可改善振盪電路之振盪頻率變化對電源 電壓之依存性。 申請專利範圍第6,7項記載之振盪電路,係在由:壓 電振盪元件;將基極連接於壓電振盪元件之第1電晶体; 與該第I電晶体串聯之第2電晶体;設於該第2電晶体基極 與一電源端間之偏壓用定電流源;分別設在上述第1電晶 体基極與上述第2電晶体基極間,及上述第1電晶体基極與 電源另一端間的偏壓電阻;設在上述第1電晶体基極與射 極間之第1電容器;設在上述第1電晶体射極與另一電源端 間的定電流源;與該定電流源並聯設置之第2電容器;設 在上述第2電晶体集極與一電源端間的輸出電阻構成之振 盪電路中,由上述偏壓電阻及設於上述第2電晶体基極之 溫度補償電路及於振盪電路之溫度補償電路,在上述第1 {請先閱讀背面之泫意事項再填寫本頁) 我----- -訂--------線 本紙張尺度適用中S國家標準(CNS)A4規格(210 X 297公芨) 6 310417 4 b 〇 U 5ί A7 ________B7 五、發明說明(7 ) (請先閱讀背面之注意事項再填寫本頁) 電晶体基極與電源另一端間的偏壓電阻串聯之二極体;設 於上述第2電晶体基極與上述電源另一端間,將射極連接 於電源另一端之電晶体分別接於該電晶体基極與射極間。 以及接於基極與集極間的電阻器;及連接於上述電晶体集 極的電阻構成 如上述構成’能於振盪電路之周圍溫度變化時,可由 設有串設在偏壓電阻之二極体,電晶体及分別連接於該電 晶体之電阻等構成的溫度補償電路。使電晶体tr2集極電 壓vc及射極電壓VE對周圍溫度之變化不變動,以確保— 定的輪出振幅,故可不須限制振盪電路能力,可予以有效 利用。 同理,可由該溫度補償電路對因偏壓定電流源“之 參差’及偏壓用分壓電阻I,R2之參差發生之變化,使電 晶体TR集極電壓vc及射極電壓vE之變動減少,確保一定輸 出振幅Vc· VE,〇· VE。故得以允許構成振盪電路之定電 流源IB,電阻’ R2之參差,使構成振盪電路元件之選擇 更加容易。 經濟部智慧財產局員工消費合作社印製 申請專利範圍第8,9,10,及11項記載之振盪電路, 係於申請專利範圍第1至7項記載之振盪電路中,將定電流 源之電流設定電阻以具有負溫度特性之電阻構成;將定電 流源以具有負溫度特性的電流設定電阻之基準電流用定電 流源及接受該基準電流用定電流源基準電流的電流鏡電路 (current mirror circuit)構成;以及以薄膜電阻構成上述電 流設定電阻。 本紙張尺度適用t國國家標準(CNS)A4規格(210 X 297公釐〉 7 310417 448 6 09 A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明(8 ) 如依上述構成,當可達到申請專利範圍第1至7項記載 之效果。而且,在振盪電路周圍溫度變動時,可將基準電 流用定電流源之電流設定電阻作爲負溫度特性電阻,可使 由定電流源電流値溫度之變化顯著以減小,以使高溫時之 輸出電壓位準穩定化,可不依周圔溫度變化,使振盪輸出 穩定升起。 又於使定電流源電流値溫度之變化顯著地減小時,可 不需回授電路等特別附加電路,僅將負溫度系數之電阻作 爲電流設定電阻使用,所以可使電路構成簡化。 又,使振盪電路之輸出電壓位準可不依周圍溫度之變 化而得以穩定,其電路電流値不須預餘裕,故電流源之電 流値得爲較小値》 申請專利範圍第12項記載之水晶振盪電路,係於申請 專利範圍第1至7項記載之振盪電路中,至少係將電晶体及 定電流源,積體化於同一半導體基板。 如上述構成,當可達到申請專利範圍第1至7項記載之 效果。且可取代以個別零件裝組構成之,分立元件(discrete) 構成’將電路構成元件,積體化於同一半導體基板構成1C, 故適用於攜帶式電子機器,以使振盪電路更加小型及輕量 化。 申請專利範圍第1 3項記載之振盪電路,係如申請專利 範圍第1至7項記載之振盪電路,唯其壓電振動元件係使用 水晶振動7C件** 如上述構成,因振動元件爲水晶振動元件,可獲得較 I------------* ^---I I I I Ί -------•漆 {請先閲讀背面之注意事項再填寫本頁> 本紙張尺度適用中囷®家標準(CNS)A4規格(21ϋ X 297公爱) 8 310417 448 6 09 A7B7 經濟部智慧財產局具工消費合作社印製 五、發明說明(9 ) 申請專利範圍第1至7項記載中更高效果。 . 申請專利範圍第14項記載之攜帶式通訊機,係含有申 請專利範圍第1至7項記載之水晶振盪電路。 如該攜帶型通訊機係於進行間歇動作之攜帶型通訊機 中,內藏振盪電路之振盪上升極爲快速,所以可減少無效 電力之消耗。 【發明之實施形態】 茲參照第1圖至第3圖說明本發明之第1實施形態。第1 圖爲表示本發明之水晶振盪電路圖。定電流源I係連接於 電晶体TR之射極與接地間》其與第17圖習用例之不同點| 係以定電流源I取代射極電阻RE。其他構成則與第17圖相 同。 因此,電源電壓Vcc以電阻Ri,R2分壓分壓點電位, 則供電晶体TR基極。因而電晶体TR動作,在集極電阻1及 電晶体TR中流過設定之定電流,以設定定直流之偏壓 。 上述分壓點之電位即施加於水晶振動元件X,溫度補償電 阻RT及溫度補償電容器CT。同時也施加於電容器Ct,C2。 使水晶振盪電路之振盪動作開始·'以集極電阻Rc的電壓降 變動部份呈現之振盪信號,則經連接在集極電阻之耦合 電容器Cc,輸於負載電路。 如依該水晶振盪電路由施加電源電壓vcc至振盪輸出 達到額定輸出電壓位準,及額定振盪頻率[±1 ppm〕止之 振盪狀態所須之振盪上升時間1^,較習用使用射極電阻的 水晶振盪電路之振盪上升時間Ts爲短。 {請先閱讀背面之注意事項再填寫本頁) 衣-------Ί訂----------線_ 本紙張尺度適用乍國國家標準(CNS)A4規格(210 X 297公釐〉 9 310417 448 609 A7 B7 五、發明說明(10 ) 而且,於定常振盪狀態之振盪位準及振盪頻率穩定, 亦不增加消耗電力。 茲說明該振盪上升時間Ts較習用使用射極電阻RE的水 晶振盪電路之振盪上升時間Ts爲短之原因如以下β 第2及第3圖係表示水晶振盪電路之交流等價電路圖。 圖中爲簡化起見,將溫度補償電阻用RT及電容器CT予以省 略。 由水晶振盪電路水晶振盪元件端’看成的電路側’可 將電晶体基射極間電壓爲,電晶体TR之互感電導 (mutral conductance;^ gm,則如第2圖所不,可由具定電 流源等價電路表示。圖中,RS, CK爲電晶体*^ 之輸入阻抗(impetance)。R。爲電阻R,與電阻I之並聯電 阻e R E爲定電流源I之電阻》 於第2圖之等價電路中,由水晶振盪電路之水晶振盡 元件端,看成的電路側阻抗Z,係將電容器’電阻之並 聯電路,依序變換爲串聯電路,求其値°可得如下所示之 關係。即 Z = l/ R贫(wc'p+l/ RE(wc2)2+l/ R〇(iWC3)2-RN . j/wc3 = Rp -Cc is a coupling capacitor to the load circuit. As shown in FIG. 17, when the switch Sw is turned on, the power supply voltage vcc is divided by the resistor R〆R2, and the potential of the divided point is supplied to the base of the transistor TR. As a result, when the transistor TR is operated, a DC current flows through the collector resistor Rc and the emitter resistor E to set a predetermined DC bias voltage. This paper size is applicable to the national standard (CNS) A4 specification (210 x 297 mm) ~ 1 310417 (Please read the precautions on the back before filling this page) Packing :: 1 order * ----- --- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 448 609 A7 B7 V. Description of the invention (2) (Please read the precautions on the back before filling out this page) — In terms of the potential of the above-mentioned voltage division point is applied to crystal The oscillating element X, the temperature compensation resistor RT, and the temperature compensation capacitor CT are also applied to the capacitors C t and C2, so that the crystal oscillation circuit starts to oscillate. The oscillating signal is output to the load circuit via the coupling capacitor Cc connected to the collector. The oscillating circuit constructed as above. After applying the power supply voltage Vcc, in order to make the oscillating output reach the oscillating state of the rated output voltage level and the rated oscillating frequency (± 1 ppm), it must have a relatively long oscillating rise time 1 ^. Figure 18 shows this state with a crystal oscillation circuit. The oscillation rise time Ts usually takes about 4 to 5 ms. The oscillating rise time Ts of this crystal oscillating circuit is longer than that of other piezoelectric oscillating element oscillating circuits such as ceramic oscillating elements. Therefore, a crystal oscillating circuit using a crystal oscillating element becomes a problem. Oscillation circuits such as crystal oscillator circuits that are used in the past are composed of so-called discrete circuits that are assembled into circuits by individual parts. There must be limits to miniaturization. Therefore, in the case of portable electronic equipment that requires miniaturization and weight reduction, when an oscillation circuit such as a crystal oscillation circuit is used, there is a problem in miniaturization. [Problems to be Solved by the Invention] The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the oscillation rise time Ts *, the oscillation output is not at the rated output voltage level, and the oscillation state of the rated oscillation frequency, so the vibration remote output cannot be used as Used as a reference frequency signal for transmitting and receiving frequencies. Therefore, after applying the power supply voltage Vcc, it is necessary to increase the oscillation output to the rated edge level and the rated oscillation frequency. Of course, power is also consumed during the oscillation rise time Ts, and this power consumption is ineffective power t. Therefore, in order to effectively use the capacity of the power source, it is necessary to shorten the time Ts. This paper size applies to the National Standard (CNS) A4 specification (2〗 〇 × 297 mm) '2 310417 448609 A7B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (3) and' Assembled with individual parts Oscillation circuits such as crystal oscillator circuits composed of so-called discrete components have reached the limit of miniaturization and weight reduction. In order to be suitable for the use of portable electronic equipment, other methods must be used to try to miniaturize the oscillation circuit itself. Therefore, the object of the present invention is to provide an oscillation circuit capable of shortening the oscillation rise time Ts required for the oscillation output to reach the oscillation state of the rated output voltage level and the rated oscillation frequency after the power supply voltage is applied. The rise time Ts, at the same time when the power supply voltage changes, also makes the oscillation frequency change extremely small, and can improve the oscillation circuit's dependence on the power supply voltage. The purpose is to shorten the oscillation rise time 1 ^, improve the oscillation frequency to the power supply At the same time of voltage dependence, it is an object to provide an oscillation circuit that improves the temperature dependence of the oscillation output level and the output amplitude without changing the oscillation output level and the oscillation edge output amplitude significantly when the ambient temperature changes. The purpose is to shorten the oscillation rise time Ts and to obtain a miniaturized and lightweight oscillator circuit. [Means for solving problems by the invention] The oscillating circuit described in item 1 of the scope of patent application is an oscillating circuit including a piezoelectric oscillating element, an oscillating capacitor, and a feedback amplifier transistor. The emitter of the transistor is connected in series with a constant current source. In this configuration, from the time when the power supply voltage Vcc1 is applied until the oscillating output becomes the rated output voltage level and the oscillating state of the rated oscillating frequency [± 1 ppm], the required oscillating rise time Ts' is more conventionally used to oscillate with an emitter resistor The oscillation rise time of the circuit is extremely short. 1 I ---- I ^ i I --------- ^ (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (2). χ297 mm) 3 310417 448609 at Β7 V. Description of the invention (4) (Please read the precautions on the back before filling this page) The oscillating circuit described in item 2 of the scope of patent application is made by: piezoelectric oscillating element; A transistor whose base is connected to a piezoelectric oscillating element: a resistor connected between a power source and applying a bias potential to the base of the transistor; a first capacitor provided between the base and the emitter of the transistor: A constant current source between the transistor emitter and one end of the power source; a second capacitor arranged in parallel with the constant power source; and an output resistor provided between the transistor collector and the other end of the power source. As described above, it is the same as that described in the first patent application range. From the application of the power supply voltage Vcc until the oscillation output becomes the rated output voltage level and the vibration state of the rated vibration salt frequency [± 1 ppm], The rise time Ts of the vibration edge is shorter than the rise time T s of the conventional resistor-resistor oscillation circuit. The oscillation level and the oscillation frequency in the steady oscillation state are stable without increasing power consumption. The oscillating circuit described in item 3 of the scope of patent application by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is composed of: a piezoelectric oscillating element; a first transistor having a base connected to the piezoelectric oscillating element; and the first transistor A second transistor in series; a resistor connected between the power source to apply a bias potential to the base of the first transistor and the base of the second transistor; provided at the base and the emitter of the first transistor First capacitor between: the constant current source provided between the emitter of the first transistor and one end of the power source: a second capacitor connected in parallel with the constant current source and the second capacitor provided between the collector of the second transistor and the other end of the power source Output resistance. With this structure, it is possible to obtain the same effect as described in item 2 of the scope of patent application. At the same time, the collectors of the first transistor and the second transistor are laminated. The meaning of this paper applies the Chinese National Standard (CNS) A4 specification (210x297 mm) 4 310417 448609 Α7 Β7 5. Description of the invention (5) (please first (Please read the notes on the back and fill in this page) [cascode], which forms the connection point between the collector and collector / resistor of the second transistor, and takes out the oscillation output. Therefore, the buffer amplifier function of the second transistor can mitigate the effect of the load fluctuation when the load connected to the output terminal is changed by the second transistor as a buffer amplifier function. Therefore, when the load changes, It can also make the oscillation of the oscillation circuit under the condition that the oscillation frequency of the output voltage level is more stable. The oscillating circuit described in item 4 of the scope of the patent application is composed of: a piezoelectric oscillating element ^ a transistor having a base connected to the piezoelectric oscillating element: connected between a power source and supplying a bias potential to the base resistance of the transistor A first capacitor provided between the base and the emitter of the transistor: a constant current source provided between the emitter of the transistor and a power terminal, and a second capacitor connected in parallel with the constant current source, and Outputting the above structure from the connection point of the emitter of the transistor and the constant current source can obtain the same effect as described in item 2 of the scope of patent application. And because the emitter side of the transistor is used as the take-out point of the output signal of the crystal oscillation circuit, there is no need to set a collector resistor between the transistor's collector and the power supply, so that the crystal oscillation circuit can be miniaturized and lightweight β The oscillating circuit described in item 5 of the scope of patent application is printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, which is composed of: a piezoelectric oscillating element: a first transistor with a base connected to the piezoelectric oscillating element; A second transistor in series; a constant current source for bias voltage provided between the base of the second transistor and the ~ power source terminal, or a constant voltage for bias voltage provided between the base of the second transistor and the other terminal of the power source A source; a bias resistor provided between the first transistor base and the second transistor base, and between the first transistor base and the other end of the power source, provided between the first transistor base and the other Emitter's paper size applies Chinese national standard (CNSM4 specification (210 X 297 Gongchu) 5 310417 448609 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs V. First capacitor between the description of invention (6); set above The first transistor emitter and A constant current source between the two power sources; a second capacitor connected in parallel with the constant current source; and an output resistance structure provided between the second transistor collector and one end of the power source. In this way, this structure can be obtained and the third item of the patent application. The same effect as described. At the same time, a constant current source for the bias between the base of the second transistor and one power terminal, or a constant current for the bias provided between the base of the second transistor and the other power terminal And a bias resistor is provided between the first transistor base and the second transistor base and / or between the first transistor base and the other power supply terminal, so that the first transistor and the second transistor can be biased. The base bias of the crystal is kept in position. Therefore, even if the power supply voltage changes, the base bias of the first transistor and the second transistor can be kept at a fixed level. This can significantly reduce the change in the oscillation frequency of the oscillation circuit. Therefore, the dependence of the oscillation frequency change of the oscillation circuit on the power supply voltage can be improved. The oscillation circuit described in the sixth and seventh items of the scope of patent application is based on: the piezoelectric oscillation element; the first connection of the base to the piezoelectric oscillation element Transistor; and the first transistor A second transistor connected in series; a constant current source for bias voltage provided between the base of the second transistor and a power source terminal; respectively provided between the base of the first transistor and the base of the second transistor, and The bias resistor between the first transistor base and the other end of the power source; the first capacitor provided between the first transistor base and the emitter; the first capacitor provided between the emitter of the first transistor and the other power source A constant current source; a second capacitor provided in parallel with the constant current source; an oscillation circuit formed by the output resistance between the second transistor collector and a power supply terminal; 2 The temperature compensation circuit of the transistor base and the temperature compensation circuit of the oscillation circuit, in the above 1 (please read the intention on the back before filling in this page) I --------------------- -The paper size of the paper applies to the Chinese National Standard (CNS) A4 specification (210 X 297 male) 6 310417 4 b 〇U 5ί A7 ________B7 V. Description of the invention (7) (Please read the precautions on the back before filling in this Page) A diode in series with a bias resistor between the base of the transistor and the other end of the power supply; 2 transistor between the base and the other end of the power supply, the emitter connected to the other end of the power transistors are respectively connected to the transistor between the base and the emitter. And the resistor connected between the base and the collector; and the resistor connected to the transistor collector as described above, when the ambient temperature of the oscillating circuit changes, it can be provided with two poles connected in series to the bias resistor A temperature compensation circuit composed of a body, a transistor, and a resistor connected to the transistor. The transistor tr2 collector voltage vc and emitter voltage VE do not change to the surrounding temperature, so as to ensure a constant output amplitude. Therefore, it is not necessary to limit the ability of the oscillation circuit and can be effectively used. In the same way, the temperature compensation circuit can change the "variation" of the bias constant current source and the variation of the bias voltage dividing resistors I and R2, so that the transistor TR collector voltage vc and the emitter voltage vE can be changed. Reduce and ensure a certain output amplitude Vc · VE, 0 · VE. Therefore, the constant current source IB and resistance 'R2 constituting the oscillation circuit can be allowed to make the selection of the components constituting the oscillation circuit easier. The oscillating circuits described in items 8, 9, 10, and 11 in the scope of patent application are printed. In the oscillating circuits described in items 1 to 7 in the scope of application, the current of the constant current source is set to a resistor with a A resistor configuration; a constant current source using a constant current source with a current setting resistance having a negative temperature characteristic; a constant current source using a constant current source; and a current mirror circuit that receives the reference current using the constant current source reference current; and a thin film resistor The above-mentioned current sets the resistance. This paper size applies to the national standard (CNS) A4 specification (210 X 297 mm) 7 310 417 448 6 09 A7 B7 Wisdom of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau of Industry and Industry 5. Description of the invention (8) If the structure described above is achieved, the effects described in the scope of patent applications 1 to 7 can be achieved. Moreover, when the temperature around the oscillation circuit changes, the reference current can be used The current setting resistance of the current source is used as a negative temperature characteristic resistance, which can significantly reduce the change in the current and temperature of the constant current source, so as to stabilize the output voltage level at high temperature. Stable rise. When the constant current source temperature and temperature change are significantly reduced, a special additional circuit such as a feedback circuit can be eliminated, and only a resistor with a negative temperature coefficient can be used as a current setting resistor, so that the circuit configuration can be simplified. In addition, the output voltage level of the oscillating circuit can be stabilized without changing the ambient temperature. The circuit current does not need to be margined, so the current of the current source can be small. The oscillating circuit belongs to the oscillating circuits described in items 1 to 7 of the scope of patent application. At least the transistor and the constant current source are integrated. The same semiconductor substrate. As described above, when the effects described in the patent application scope items 1 to 7 can be achieved, and it can replace the individual component assembly, discrete component (discrete) configuration 'Integrate circuit components The same semiconductor substrate constitutes 1C, so it is suitable for portable electronic equipment to make the oscillating circuit smaller and lighter. The oscillating circuit described in item 13 of the patent application scope is the oscillating circuit described in item 1 to 7 of the patent application scope. Only the piezoelectric vibrating element uses 7C pieces of crystal vibration ** As stated above, since the vibrating element is a crystal vibrating element, it can be compared with I ------------ * ^ --- IIII Ί ------- • Lacquer {Please read the precautions on the back before filling in this page> This paper size is applicable to China 囷 ® Home Standard (CNS) A4 specification (21ϋ X 297 public love) 8 310417 448 6 09 A7B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 5. Description of Invention (9) The higher effect is found in the first to seventh records of the scope of patent application. . The portable communication device described in item 14 of the scope of patent application contains the crystal oscillator circuit described in item 1 to 7 of the scope of patent application. If the portable communication device is in a portable communication device that performs intermittent operations, the oscillation of the built-in oscillation circuit rises very quickly, so the consumption of reactive power can be reduced. [Embodiment of the invention] The first embodiment of the present invention will be described with reference to Figs. 1 to 3. Fig. 1 is a diagram showing a crystal oscillation circuit of the present invention. The constant current source I is connected between the emitter and the ground of the transistor TR. The difference from the conventional example in Figure 17 is that the constant current source I replaces the emitter resistor RE. The other components are the same as those in Figure 17. Therefore, if the power supply voltage Vcc is divided by the potentials of the resistors Ri and R2, the base of the crystal TR is supplied. Therefore, the transistor TR operates, and a set constant current flows through the collector resistor 1 and the transistor TR to set a constant DC bias voltage. The potential at the above-mentioned voltage dividing point is applied to the crystal vibration element X, the temperature compensation resistor RT, and the temperature compensation capacitor CT. Also applied to capacitors Ct, C2. Start the oscillation operation of the crystal oscillation circuit. 'The oscillation signal presented by the voltage drop of the collector resistor Rc will be input to the load circuit via the coupling capacitor Cc connected to the collector resistor. For example, according to the crystal oscillation circuit, from the application of the power supply voltage vcc until the oscillation output reaches the rated output voltage level, and the oscillation rise time required for the oscillation state at the rated oscillation frequency [± 1 ppm] is 1 ^, it is more The oscillation rise time Ts of the crystal oscillation circuit is short. {Please read the precautions on the back before filling in this page) Clothing ------------ Order ---------- Line_ This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm> 9 310417 448 609 A7 B7 V. Description of the invention (10) Moreover, the oscillation level and oscillation frequency in the steady oscillation state are stable, and the power consumption is not increased. It is explained that the oscillation rise time Ts is longer than that of conventional use. The reason why the oscillation rise time Ts of the crystal oscillation circuit of the pole resistance RE is short is as shown in the following β. Figures 2 and 3 show the AC equivalent circuit diagram of the crystal oscillation circuit. For the sake of simplicity, RT and Capacitor CT is omitted. From the crystal oscillator circuit, the crystal oscillator element terminal can be regarded as the circuit side. The voltage between the base and the emitter of the transistor can be expressed as the mutual conductance (^ gm) of the transistor TR, as shown in Figure 2. No, it can be represented by an equivalent circuit with a constant current source. In the figure, RS, CK are the input impedance of the transistor * ^. R. is the resistance R, and the parallel resistance e RE with the resistance I is the constant current source I. "Resistance" is oscillated by a crystal in the equivalent circuit of Figure 2. The crystal of the circuit vibrates the element end, and the circuit-side impedance Z is regarded as the parallel circuit of the capacitor's resistance, which is sequentially converted into a series circuit, and the relationship between them is obtained as follows: Z = l / R Poverty (wc'p + l / RE (wc2) 2 + l / R〇 (iWC3) 2-RN. J / wc3 = Rp-

Rn- 其中,R0 = R2 / (Rd R2) , C\ = C, + C3 = C, i · c? / c, ! + c2 因此,可將水晶振盪電路之等價電路表示如第3圖° 該阻抗Z之公式,由水晶振盪電路之水晶振擾元件端看2 電路側中,具有實數項的電路電阻部份損失電阻Rp’ 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 1〇 310417 (請先閱讀背面之注意事項再填寫本頁) 我--------訂----------線 經濟郤智慧財產局員工消費合作社印製 448 6 09 A7 B7 五、發明說明(11 ) 電阻Rn,及虛數項的電抗(reactance)j/&>c3。又,於第3圖 中之Lx,Rx,則分別表示水晶振盪元件X之阻抗及電阻* (諳先閱讀背面之注意事項再填寫本頁) 損失電阻RP與負性電阻RN之極性互異,故與負性電阻 RN互相抵消,實質上將降低負性電阻“的大小。 於本發明中’以設置定電流源I替代水晶振盪電路 射極電阻RE。因此,係於定電流源I流通固定電流,同 時如須變化該電流之大小,即有呈現極大電阻値之作用❶ 定電流源’I之交流電阻極大,理論上雖爲無限大,但實際 上係取電路元件構造上之有限値。又於電晶体射極係在一 定値之直流上,重疊振盪頻率之交流電流。又因定電流源 I之交流電阻極大,其在定値直流上重疊振盪頻率之交流 電流,係經由與定電流源I並聯之電容器C2流過,直流電 流則流過定電流源I。 如上述,由於定電流源I之交流電阻極大,於前述等 價電路(第3圖)中,由水晶振盪電路之水晶振盪元件端看 成之電路側阻抗Z有關射極電阻RE的損失電阻Rp變小。結 果,負性電阻RN與損失電阻RP之抵消量變小。 經濟部智慧財產局員工消費合作社印射农 因而,負性電阻値實質上變大,致使振盪電路中之實 效電阻(RX + RP)與負性電阻(RN)絕對値之差變大,以加速 水晶振盪電路之振盪上升。由此,在水晶振盪電路射極設 置定電流源I之本發明,其振盪上升時間Ts則較以往使用 射極電阻RE的振盪上升時間Ts爲短。 其次,就本發明第2實施例,參照第4圖,第5圖(a), 第5圖(b),第6圖(a),及第6圖(b)說明如下: 310417 本紙張尺度適用t國國家標準(CNS)A4規格(210 X 297公釐) 448 609 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(12 ) 第4圖爲表示本發明之水晶振盪電路圖。係於.第1實施 例之第1圖的電晶体1\集極將第2電晶体TRB(cascode)。由 該第2電晶体丁^集極與集極電阻Rc之連接點,取出振盪輸 出*同時,亦將偏壓用電阻RB及電壓穩定用CB,以圖示方 式,接第2電晶体TRB基極》其他,如包括定電流源丨接 於電晶体TR射極與接地間等各點,則與第1圖相同,其與 第1圖相同之部份係以相同符號編註。 於第'4圖所示之第2實施例中,係於水晶振盪電路之射 極設定電流源I。故其振盪上升時間Ts,亦與第1圖之水 晶振盪電路相同。較習用使用射極電阻的水晶振盪電路之 振盪上升時間Ts爲短。 又因於該第4圖所示之第2實施例中,係於電晶体1\集 極叠接第2電晶体TRB,由該第2電晶体TRB2集極與集極電 阻Rc之連接點,取出振盪輸出。故第2電晶体TRB將以緩衝 放大器動作由該機可使輸出端所接之負載變動時,爲可 將負載變動之影響以緩衝放大器作用的第2電晶体TRB予緩 和。 因此,在負載變動時,亦可穩定水晶振盪器的振盪。 第5圖(a)及第5圖(b)係用以證明第4圖所示第2實施例 之水晶振盪電路之振盪上升,對構成振盪電路各元件設定 具體數値之水晶振盪電路及其振盪上升之特性圖。而第6 圖U)及第6圖(b)係用以比較而將定電流源I與習用水晶振 盪電路一樣以射極電阻RE取代者,其他部份則與第5圖(a) 完全相同。至於第5圖(a)及第5圖(b)之振盪上升特性,係 — — — — ——----- ^------J— 訂 ----------"5^ {請先Μ讀背面之注意事項再填窵本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 12 310417 經濟部智慧財產局員工消費合作社印製 448609 A7 B7 五、發明說明(13 ) 依實測所得。 . 由第5圖(b)及第6圖(b)可知,由施加電源開始至輸出 振盪頻率,達到額定値之土 1 ppm內的,振盪上升Ts時間, 係與第6圖(b)之習用例一樣,在使用射極電阻的水晶振 盪電路爲4.4 ms,而於第5圖(b)之本發明之使用電流源I的 水晶振盪電路中則爲1.4ms。於此例中,顯示兩者的比率 爲3比1,可知使用定電流源I之本發明的水晶振盪電路 之振盪上'升時間1^的改善效果極大。 其次,參照第7圖說明本發明之第3實施例。 以第7圖表示本發明的水晶振盪電路圖。其與第1實施 例的第丨圖之不同,係由電晶体7\之射極側介由耦合電容 器Cc取出振盪輸出信號,而且去除集極電阻。此外,如包 括定電流源I連接於電晶体TR射極與接地間等各予,均 與第1圖相同。又於與第1圖相同之部份,則附與同一符號。 於第7圖所示第3實施例中因在水晶振盪電路射極設置 定電流源I,其振盪上升時間1\較習用之使用射極電阻水 晶振盪電路之振盪上升時間Ts爲短。此點係與第1圖及第4 圖之水晶振盪電路相同。 又因於第7圖所示之第3實施例中,係將水晶振盪電路 之輸出信號取出點設於電晶体TR之射極側,故可不須於電 晶体TR集極與電源vcc間設集極電阻。因而得以使水晶振 盪電路達成小型化,輕量化。 其次,參照第8圖,第9圖及第10圖說明本發明之第4, 5實施例於后: -----訂,--I-----線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公茇) 13 310417 448 6 09 A7 B7 五、發明說明(Η ) (請先閲讀背面之注意事項再填寫本頁) 於第8圖表示本發明之水晶振盪電路圖。係將第2實施 例之第4圖中之偏壓用電阻RB,以偏壓用定電流源I取 代。其他’如包括定電流源I連接於電晶体^射極與接 地間等各點,均與第1圖相同。又與第4圖中相同部份均附 與相同之符號。 如第8圖所示之第4實施例,係於水晶振盪電路射極設 置定電流源I ,故其振盪上升時間Ts較習用使用射極電 阻之水晶'振盪電路之振盪上升時間Ts爲短。且於連接輸出 端之負載變動時’其負載變動影響係由作爲緩衝放大器之 第2電晶體TRB機能予以緩和,則與第4圖之水晶振盪電路 相同β 經濟部智慧財產局員工消費合作社印製 又,如第8圖所示之第4實施例,係於第2電晶体了^基 極與電源間,連接偏壓用定電流源ΙΒ,以使在偏壓電阻 I,R2流過定電流,故可將電晶体TRB之基極偏壓保持於 定値。由此機能,雖能於電源電壓Vcc變動時,使第4圖中 之水晶振盪電路各電晶体之基極偏壓變動,以變化水晶振 盪電路之振盪頻率。但在本實施例中,即使電源電壓Vcc 變動,亦可將電晶体TR,及電晶体TRB之基極偏壓保持於 定値》故得以顯著減少水晶振盪電路之振盪頻率變化。亦 即,可改善水晶振盪電路之振盪頻率變化之電源電壓依存 性* 如上述電源電壓Vcc變動時,雖可變動水晶振盪電路 之振盪頻率。唯形成該變動途徑(mechanism),係與各參 數(par a me ter)有關,故不甚明確。只能確定水晶振盪電 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 14 310417 448609 A7 B7 五、發明說明(is ) (請先閱讀背面之注意事項再填寫本頁) 路中之電晶体輸入阻抗係因偏壓之設定而變化,且寄生於 電晶体各接端靜電容量係因偏壓之設定而變化,由該變化 影饗水晶振盪電路,使振盪頻率變化等,爲其變化之原因β 該偏壓用定電流源18,與設置在電晶体7\射極與接 地間之電流源I因爲例如帶域間隔(bandgap)型定電流電 路,因此可共用很多構成電路元件’其設置定電流源IB 增加之零件。 又,’於第4實施例中,爲保持電晶体心及電晶体TRB之 基極偏壓於定値。可如第9圖之第5實施例所示,設置電池 等定電壓源VBW取代定電流源IB。設置該定電壓源^之 作用,係與設置偏壓定電流源IB相同。 第10圖係用以表示第8圖所示第4實施例中,水晶振盪 電路之振盪頻率變化的電源電壓依存性改善度之電源電壓 -頻率特性圖。圖中,實線代表於本實施例定電流偏壓中 之特性,虛線爲表示比較用之第2實施例中第4圖之電阻 分割偏壓中之特性。該等特性係依實測値繪製》 經濟部智慧財產局員工消費合作社印製 由上述特性圖可知,於本實施例之水晶振盪電路中哥 獲對電源電壓變動之振盪頻率變化改善。 又,於本實施例中,可由對電源電壓變動之振盪頻率 變化少,獲知使用者(user)於使用水晶振盪電路時,即使 電源電壓稍有偏離預定値,亦可改善振盪頻率偏移問題。 上述保持電晶体1\及電晶体TRB基極偏壓爲固定値的 示例係由使用定電流源IB之第4實施例,及使用定電壓源 VB之第5實施例表示。以定電流源IB,定電壓源VB保持 本紙張尺度適用ΐ國國家標準(CNS)A4規格(210 X 297公釐) 15 310417 448 609 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明u ) 電晶体tr&/或電晶体trb之基極偏壓爲定値之方筠。亦適 用於第1圖中之第〗實施例,第4圖中之第2實施例及第7圖 中之第3實施例。此時,亦可由定電流源IB,定電壓源Vb, 使電晶体了11及/或電晶体TRB之基極偏壓保持於一定値。 其次,參照第Π圖及第12圖,說明本發明之第6實施 例於後: 第11圖爲本發明之水晶振盪電路圖》係於第8圖之第4 實施例的水晶振盪電路,增設串聯於偏壓電阻]^2之二極体 Dt&電晶体TRC。以及分別在電晶体集極與基極間,基極 與射極間,以及於集極連接電阻器R3,R4,R5,形成之溫 度補償電路。其他,如包括定電流源I連接於電晶体TR 射極與接地間,在偏壓電路設置定電流源IB等各點,均 與第8圖者相同。其與第8圖相同之部份均附與相同符號。 如前所述,於第8圖所示之第4實施例雖具有:水晶振 盪電路之振盪上升時間Ts,較習用水晶振盪電路短及水晶 振盪電路振盪頻率變化的電源電壓依存性顯著改善等優 點,但尙有對溫度變化之改善問題。 換言之,於偏壓用分壓電阻R!,R2,具有溫度係數時, 電晶体TR,電晶体TRB之基極偏壓將對應於周圍溫度之變 動而變化》當電晶体TRB基極偏壓變動時,則如第12圖U) 所示,電晶体TR集極之電壓Vc變動。而於電晶体tr基極偏 壓變動時,則如第12圖(b)所示電晶体TR射極之電壓VE, 動。如上起因於電晶体TRB基極偏壓的變化之電晶体TR 集極電壓Vc及射極電壓νε之變化,使水晶振盪電路之輸 ------------- 取-------1訂一-------線- (請先閱讀背面之注意事項再填寫本頁> 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 16 310417 448 6 0 9Rn- where R0 = R2 / (Rd R2), C \ = C, + C3 = C, i · c? / C,! + c2 Therefore, the equivalent circuit of the crystal oscillator circuit can be expressed as shown in Figure 3. ° The formula of the impedance Z is viewed from the crystal oscillator element end of the crystal oscillator circuit. 2 In the circuit side, the part of the circuit resistance with real numbers is lost. Resistance Rp 'This paper size is applicable to China National Standard (CNS) A4 specification (210x297 mm) 1〇310417 (Please read the precautions on the back before filling this page) I -------- Order ---- ------ Line economy but printed by Intellectual Property Bureau employee consumer cooperatives 448 6 09 A7 B7 V. Description of the invention (11) Resistance Rn, and reactance of imaginary term j / & & c3. In addition, Lx and Rx in Fig. 3 respectively represent the impedance and resistance of the crystal oscillating element X * (谙 Please read the precautions on the back before filling this page) The polarity of the loss resistance RP and the negative resistance RN are different. Therefore, the negative resistance RN cancels each other, which will substantially reduce the size of the negative resistance. In the present invention, the constant current source I is used to replace the emitter resistance RE of the crystal oscillation circuit. Therefore, the constant current source I flows and is fixed. At the same time, if the current needs to be changed, it will have a great resistance. The AC resistance of the fixed current source 'I is extremely large. Although it is theoretically infinite, it is actually limited by the circuit element structure. In addition, the transistor emitter is on a certain DC current and overlaps the oscillating frequency of the AC current. Because the AC resistance of the constant current source I is extremely large, the AC current on the fixed frequency of the oscillating frequency is superimposed on the constant current source. The capacitor C2 in parallel flows through the I, and the DC current flows through the constant current source I. As mentioned above, because the AC resistance of the constant current source I is extremely large, in the aforementioned equivalent circuit (Figure 3), the crystal oscillator The crystal oscillating element end is regarded as the circuit-side impedance Z and the loss resistance Rp of the emitter resistance RE becomes smaller. As a result, the offset amount of the negative resistance RN and the loss resistance RP becomes smaller. Therefore, the negative resistance 値 becomes substantially larger, causing the difference between the effective resistance (RX + RP) and the absolute resistance RN in the oscillation circuit to become larger, so as to accelerate the oscillation of the crystal oscillation circuit. In the present invention of the crystal oscillator circuit, the emitter of which is provided with a constant current source I, the oscillation rise time Ts is shorter than that of the conventional oscillation rise time Ts using the emitter resistor RE. Secondly, referring to FIG. 4 of the second embodiment of the present invention, Figure 5 (a), Figure 5 (b), Figure 6 (a), and Figure 6 (b) are explained as follows: 310417 This paper size is applicable to National Standard (CNS) A4 (210 X 297 mm) (%) 448 609 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (12) Figure 4 shows the crystal oscillation circuit diagram of the present invention. It is based on the first crystal of the first embodiment of the transistor 1 \ The collector will be the second transistor TRB (cascode). By The connection point of the second transistor D1 and the collector resistor Rc, and the oscillation output is taken out * At the same time, the bias resistor RB and the voltage stabilization CB are connected to the base of the second transistor TRB as shown in the figure " Others, such as including a constant current source connected to the TR emitter and ground of the transistor, are the same as in Figure 1, and the same parts as those in Figure 1 are marked with the same symbols. Figure 4 In the second embodiment shown, the emitter sets the current source I in the crystal oscillation circuit. Therefore, the oscillation rise time Ts is also the same as the crystal oscillation circuit in Fig. 1. A crystal oscillation circuit using an emitter resistor is more commonly used. The oscillation rise time Ts is short. Also, in the second embodiment shown in FIG. 4, the second transistor TRB is connected to the transistor 1 \ collector, and the collector of the second transistor TRB2 and Take the connection point of the collector resistor Rc and take out the oscillation output. Therefore, when the second transistor TRB operates as a buffer amplifier and the load connected to the output terminal can be changed by this machine, it is a second transistor TRB that can mitigate the effect of the load change by using the buffer amplifier. Therefore, even when the load fluctuates, the oscillation of the crystal oscillator can be stabilized. Figures 5 (a) and 5 (b) are used to prove the rise of the oscillation of the crystal oscillation circuit of the second embodiment shown in Fig. 4. The crystal oscillation circuit of each element constituting the oscillation circuit is set with a specific number and Characteristic diagram of rising oscillation. Fig. 6 U) and Fig. 6 (b) are for comparison, and the constant current source I is replaced with the conventional crystal oscillator circuit with the emitter resistor RE, and the other parts are exactly the same as those in Fig. 5 (a). . As for the oscillation rising characteristics of Figure 5 (a) and Figure 5 (b), it is — — — — — — — — — — — — — — — — — — — — — — -" 5 ^ {Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 12 310417 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System 448609 A7 B7 5. Description of the invention (13) Measured according to actual measurement. From Figure 5 (b) and Figure 6 (b), it can be seen that from the time when the power supply is applied to the output oscillation frequency, which reaches within 1 ppm of the rated soil, the oscillation rise time Ts is the same as that in Fig. 6 (b). As in the conventional use case, the crystal oscillation circuit using the emitter resistor is 4.4 ms, and the crystal oscillation circuit using the current source I of the present invention in Fig. 5 (b) is 1.4 ms. In this example, it is shown that the ratio of the two is 3 to 1. It can be seen that the crystal oscillation circuit of the present invention using the constant current source I has a great improvement effect on the rise time of the rise time 1 ^. Next, a third embodiment of the present invention will be described with reference to FIG. Fig. 7 shows a crystal oscillation circuit diagram of the present invention. This is different from the first diagram in the first embodiment in that the oscillation output signal is taken out from the emitter side of the transistor 7 \ via the coupling capacitor Cc, and the collector resistance is removed. In addition, if the constant current source I is connected between the emitter of the transistor TR and the ground, it is the same as the first figure. The same symbols are attached to the same parts as in Figure 1. In the third embodiment shown in Fig. 7, since a constant current source I is provided at the emitter of the crystal oscillation circuit, its oscillation rise time 1 is shorter than the oscillation rise time Ts of a conventional crystal oscillator circuit using an emitter resistor. This point is the same as the crystal oscillation circuit in Figures 1 and 4. Also, in the third embodiment shown in FIG. 7, the output signal of the crystal oscillation circuit is set at the emitter side of the transistor TR, so it is not necessary to set a collector between the transistor TR collector and the power source vcc. Extreme resistance. Therefore, the crystal oscillator circuit can be miniaturized and lightened. Next, the fourth and fifth embodiments of the present invention will be described with reference to FIG. 8, FIG. 9, and FIG. 10: ----- Order, -I ----- (Please read the note on the back first Please fill in this page again for this matter) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 cm) 13 310417 448 6 09 A7 B7 V. Description of the invention (Η) (Please read the precautions on the back before filling in this (Page) Fig. 8 shows a crystal oscillation circuit diagram of the present invention. The bias resistor RB in Fig. 4 of the second embodiment is replaced by a constant current source I for the bias. Other points such as the point where the constant current source I is connected between the transistor ^ emitter and the ground are the same as in the first figure. The same parts as in Fig. 4 are given the same symbols. As shown in Fig. 8, the fourth embodiment is based on the setting of a constant current source I at the emitter of the crystal oscillation circuit, so its oscillation rise time Ts is shorter than the oscillation rise time Ts of a conventional crystal 'oscillation circuit using an emitter resistor. And when the load at the output terminal is changed, its load fluctuation effect is mitigated by the function of the second transistor TRB as a buffer amplifier. It is the same as the crystal oscillation circuit in Figure 4. As shown in FIG. 8, the fourth embodiment is connected between the base and the power source of the second transistor, and a constant current source IB for bias is connected so that a constant current flows through the bias resistors I, R2. Therefore, the base bias of the transistor TRB can be maintained at a fixed value. With this function, when the power supply voltage Vcc fluctuates, the base bias voltage of each transistor of the crystal oscillation circuit in FIG. 4 can be changed to change the oscillation frequency of the crystal oscillation circuit. However, in this embodiment, even if the power supply voltage Vcc is changed, the base bias voltage of the transistor TR and the transistor TRB can be kept constant, so the oscillation frequency variation of the crystal oscillation circuit can be significantly reduced. In other words, the dependence of the power supply voltage on the oscillation frequency of the crystal oscillation circuit can be improved. * When the power supply voltage Vcc changes, the oscillation frequency of the crystal oscillation circuit can be changed. The mechanism that forms this change is related to each parameter (par a me ter), so it is not clear. It can only be determined that the paper size of the crystal oscillator is applicable to the Chinese national standard (CNS) A4 specification (210 X 297 mm) 14 310417 448609 A7 B7 V. Description of the invention (is) (Please read the precautions on the back before filling this page) The input impedance of the transistor in the circuit changes due to the setting of the bias voltage, and the capacitance of the terminals parasitic to the transistor changes due to the setting of the bias voltage. This change affects the crystal oscillation circuit and changes the oscillation frequency. The reason for its change β The constant current source 18 for the bias voltage and the current source I provided between the transistor 7 \ emitter and the ground I can share many constituent circuits because of, for example, a bandgap type constant current circuit Component 'is a component whose constant current source IB is added. Also, in the fourth embodiment, the base of the transistor core and the transistor TRB is biased to a fixed voltage. As shown in the fifth embodiment of Fig. 9, a constant voltage source VBW such as a battery may be provided instead of the constant current source IB. Setting the constant voltage source ^ has the same effect as setting the bias constant current source IB. Fig. 10 is a power supply voltage-frequency characteristic diagram showing the improvement of the power supply voltage dependency of the oscillation frequency of the crystal oscillation circuit in the fourth embodiment shown in Fig. 8. In the figure, the solid line represents the characteristics in the constant current bias of this embodiment, and the dashed line represents the characteristics in the resistance division bias of Figure 4 in the second embodiment for comparison. These characteristics are drawn according to actual measurement. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. From the above characteristic graph, it can be seen that in the crystal oscillation circuit of this embodiment, the oscillation frequency change of the power supply voltage variation is improved. In addition, in this embodiment, it can be seen that the oscillation frequency of the power supply voltage is less changed, and it is known that when a user uses a crystal oscillation circuit, even if the power supply voltage slightly deviates from a predetermined threshold, the problem of oscillation frequency offset can be improved. The above examples of maintaining the transistor 1 \ and the transistor TRB base bias to a fixed value are shown in the fourth embodiment using a constant current source IB and the fifth embodiment using a constant voltage source VB. The constant current source IB and constant voltage source VB are maintained at this paper. The national paper standard (CNS) A4 (210 X 297 mm) is applicable. 15 310 417 448 609 Α7 Β7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Note that the base bias voltage of the transistor tr & / or the transistor trb is fixed. It is also applicable to the first embodiment in Fig. 1, the second embodiment in Fig. 4, and the third embodiment in Fig. 7. At this time, the base bias voltage of the transistor 11 and / or the transistor TRB can also be maintained at a constant value by the constant current source IB and the constant voltage source Vb. Next, the sixth embodiment of the present invention will be described below with reference to FIG. 11 and FIG. 12: FIG. 11 is a crystal oscillation circuit diagram of the present invention. The crystal oscillation circuit of the fourth embodiment of FIG. 8 is added in series. In the bias resistor] ^ 2 of the diode Dt & transistor TRC. And temperature compensation circuits formed between the collector and the base of the transistor, between the base and the emitter, and the resistors R3, R4, and R5 connected to the collector. Other points, such as including the constant current source I connected between the transistor TR emitter and ground, and the constant current source IB in the bias circuit are the same as those in FIG. 8. The same parts as those in Fig. 8 are assigned the same symbols. As mentioned above, although the fourth embodiment shown in FIG. 8 has the advantages that the oscillation rise time Ts of the crystal oscillation circuit is shorter than that of the conventional crystal oscillation circuit and the power supply voltage dependency of the oscillation frequency of the crystal oscillation circuit is significantly improved, etc. However, there is no problem in improving the temperature change. In other words, when the bias voltage-dividing resistors R !, R2 have a temperature coefficient, the base bias of the transistor TR and the transistor TRB will change in response to changes in the ambient temperature. At this time, as shown in FIG. 12 U), the voltage Vc of the transistor TR collector varies. When the base bias voltage of the transistor tr fluctuates, the voltage VE of the emitter of the transistor TR moves as shown in FIG. 12 (b). The change in the transistor TR collector voltage Vc and the emitter voltage νε caused by the change in the base bias of the transistor TRB as described above makes the output of the crystal oscillation circuit ------------- take- ----- 1 Order one ------- Line- (Please read the notes on the back before filling in this page> This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 16 310417 448 6 0 9

經濟部智慧財產扃具工消费合作社印製 五、發明說明(Π ) 出位準νουτ變動,亦影響其輸出振幅。 . 又,於水晶振盪電路中爲使振盪正常動作,須以射極 電壓VE爲中心確保一定値以上的上限電壓,下限電壓乂^ νΕ ’ 0 - VE。但是,唯於周圍溫度變化時,由電晶体1\射 極電壓vE’集極電壓vc之變化,影響上限電壓,下限電 Mvc - VE,0 - VE。故須預估計變動,將射極電壓VE,集 極電壓乂^:設定爲較大値。 該結果’使輸出動態範圍(dynamic range) V。。- ν。^, Vc - V。^變小。成爲水晶振盪電路能力限制。 而且,上述變動問題,不限於周圍溫度之變化,亦可 由偏壓用定電流源IB之參差,以及偏壓用分壓電阻1^, 之參差而產生* 第11圖之第6實施例中,係將第4實施例之第8圖的水 晶振盪電路中,設與偏壓電阻112串聯之二極体Di,電晶体 TRC。且於電晶体集極與基極間,基極與射極間,以及集 極分別連接電阻R3’ R4’ R5,形成溫度補償電路。使電晶 体TR之集極電壓vc及射極電壓ν£,對周圍溫度之變化不變 動,以使水晶振盪電路之輸出位準Vui不變化,而不影響 其輸出振幅。且’可將以射極電壓VE爲中心之上限電壓, 下限電壓VC-VE,〇·νΕ,穩定於固定値。以確保輸出動 態範圍v〃- veut,vc - ,故得以不限制水晶振盪電路 能力|予以有效利用- 同理’可由該溫度補償電路,對偏壓用定電流源“ 之參差及偏壓用分壓’電阻R!,!^參差所生之變化,排除 — — — — ί — — — — « — — — — III 一&' — -ί — — — —— — — . (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中®國家標準(CNS)A4規格(210x 297公釐) 17 310417 449609 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明U ) 電晶体7^集極電壓Vc及射極電壓VE之變動|確保射極電壓 VE爲中心之上限電壓、下限電壓Vc- VE,〇 - VE,使構成 水晶振盪電路的定電流源,電阻容許其有參差, 故對構成水晶振盪電路元件的選擇較易。 以下,就於第6實施例所設之溫度補償電路動作,參 照第1 1圖詳述如下: 因電晶体TR之集極電壓Vc爲:Printed by the Intellectual Property Co., Ltd. of the Ministry of Economic Affairs and Consumer Cooperatives. 5. The description of the invention (Π) Changes in the output level νουτ also affect its output amplitude. In order to make the oscillation work normally in the crystal oscillation circuit, it is necessary to ensure the upper limit voltage and the lower limit voltage 乂 ^ νΕ ′ 0-VE with the emitter voltage VE as the center. However, only when the ambient temperature changes, the change of the collector voltage VC of the transistor 1 \ emitter voltage vc affects the upper limit voltage and lower limit power Mvc-VE, 0-VE. Therefore, it is necessary to estimate the change in advance, and set the emitter voltage VE and the collector voltage 乂 ^: to a larger value. This result 'causes a dynamic range V to be output. . -ν. ^, Vc-V. ^ Becomes smaller. Become a crystal oscillator circuit capability limitation. Moreover, the above-mentioned variation problem is not limited to the change of the ambient temperature, and can also be caused by the variation of the bias current source IB and the variation of the bias voltage dividing resistor 1 ^, * In the sixth embodiment of FIG. 11, In the crystal oscillation circuit of FIG. 8 of the fourth embodiment, a diode Di and a transistor TRC are provided in series with the bias resistor 112. Resistors R3 ', R4', and R5 are respectively connected between the collector and the base of the transistor, between the base and the emitter, and the collector to form a temperature compensation circuit. The collector voltage vc and the emitter voltage ν £ of the transistor TR are kept constant from changes in the ambient temperature, so that the output level Vui of the crystal oscillation circuit does not change without affecting its output amplitude. And, the upper limit voltage centered on the emitter voltage VE and the lower limit voltage VC-VE, 0 · νE can be stabilized at a fixed value. In order to ensure the output dynamic range v〃-veut, vc-, it is possible to not limit the ability of the crystal oscillation circuit | to be effectively used-the same way, the temperature compensation circuit can be used for the bias and constant bias of the constant current source Pressure 'resistance R!,! ^ Variation caused by variations, exclude — — — — ί — — — «— — — — III I &' — -ί — — — — — — (Please read the back first Please fill in this page before filling in this page) This paper size is applicable ® National Standard (CNS) A4 specification (210x 297 mm) 17 310417 449609 Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives printed A7 B7 V. Description of invention U) Transistor 7 ^ Variation of collector voltage Vc and emitter voltage VE | Ensure that the upper limit voltage and lower limit voltage Vc- VE, 0- VE centered on the emitter voltage VE, make the constant current source constituting the crystal oscillation circuit, and the resistance allows it to have variations Therefore, it is easier to select the components of the crystal oscillation circuit. In the following, the operation of the temperature compensation circuit set in the sixth embodiment is described in detail with reference to FIG. 11 as follows: Because the collector voltage Vc of the transistor TR is:

Vc= VA + VB +VBE2 -........(1) a Vc/ 5 τ =3 VA Id T + 3 VB /3 T - 3 VBE2 /5 T ..........(2) 式中:3VC/ 3 T表示Vc2溫度變化電壓。(以下以表示 / T) VB= VBE3X(R4 / R5+l) ..........(3) 又因,各電阻只4,R4之溫度係數相同, dVs=d VBE3x(R4 / R5+D ......----(4) 各電晶体之基極•射極間電壓VBE2 、VBEs相同(可由熱結 合實現),故將(4)式代入(2)式, 獲得,3 Vc= a vBE3X(R4 / R5) + VA ..........(5) 若須將集極電壓Vc;之溫度變化爲零,可使 3Va =: - 9VBE3X(R4^ R5) 其中,若3 VBE3爲通常電晶体之溫度係數-1.6X 1〇 -3, 3 VA = 1.6X10 ·3 X (R4 / R5) 0 又因,VA=R3X【2,如I2如固定,3vA可由電阻Rj之溫度 係數K3決定, 亦即 K3XVA= 1.6X10 -3x(R4/ R5) -I -----11----裝·! 11--"—訂-- - ----· {請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中固國家標準(CNS)A4規格(210 X 297公釐) 18 310417 經濟部智慧財產局員工消費合作社印製 ^48 6 0 9 A7 B7 五、發明說明(19 ) VA= 1.6X10 ·3 X { R4 /( K3R5) ----------(5) 如將VA設定爲(5)式,即可使集極間電壓Vc之溫度變化爲 零。 但,如電流12因溫度而不定時,流入電晶体基極之電流, 即因電阻Ri ’ 112之溫度係數變化。故該電壓νΑ之設定,係 以漸近(cut and try)方式設定。 若忽視電晶体之基極電電流’電晶体*^之射極電壓Ες; 則爲: VE = -VBE1 + ( Vj -Vf)XR2 / ( RI+ R2) + Vf 3 VE = - 5 VBE1 + ( 3 V, - 3 Vf) XR2 / ( R:+ R2) + Vf 因電晶体之VBE#二極体溫度係數相同,而vc係 於設定爲定値之3V1=3VBE2之關係 故 。 而 dVE = 0。 如上,可使射極電壓VE之溫度變化爲零》 其次,說明因偏壓用定電流源IB之電流値參差而變 動時之電晶体TR集極電壓乂。,及射極電壓VE之變動如下: 當電流値IB由額定値變動5“時,該電壓乂!之變動量 5 V 1爲 5 V! =:{ R3 II ( Ri+ R2)} 5 IB 其中,丨丨係表示電阻並聯。 在電路構成上可使電阻R3爲小,故電流IB之參差,對 電壓V,之變動極小。 因電晶体TR之集極電壓vc,爲vc = VBE2。射極電 ------------.裝-----JJI訂----------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用t國國家標準(CNS)A4規格(210 X 297公釐) 19 310417 448609 A7 B7 五、發明說明(2〇 ) 壓 VE,爲 VE^Vi-Vf) XRz/iRdRj + vf。,即使偏壓 用定電流源1^之電流値有參差,亦能使集極電壓Vc及射 極電壓vE之變動爲小《 其次’說明於各電阻阻値之參差導致變動時,電晶体 1\集極電壓vc及射極電壓vE之變動如下: 若電壓乂1爲: V I = ( V A + V B ) = 〇 + R 4 / R 5 ) X V B £ 3 + R 3 X I 2 其對電阻Rj參差,尺3之V!變化量5 ¥,爲: <5 V ! = 12 X 5 R 3 因電路構成上,可將電阻1^3爲極小値,其於各電阻參差導 致電壓V,之變動極小。 {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 該 m 曰 适曰曰 体TR之 .集極電壓V c可由Ve = :V, - VBE2,兩射極 電 壓 VE :則以 V£ ·=( V 1 - Vf) r2 > /(R1 - R2) + Vf表示。 即使各電阻値有參 差 該 集極 電壓V C及射極電壓VE之變動亦可爲極小。 於 此, 由第1 : 1圖中之第6實施例, 観察電晶体TR集極 電 壓 Vc 及射 極電歷 丨VEi變動, 其對於周圍溫度變化改善 之 模 擬 (simuUtion)結果如下。 該溫度, 係選擇標準溫度27 0 C, 低溫 -30° C ,高溫75° C » 本 實施 例(第1 1圖)之模擬 結果如下 : Vc VE 標 準 溫 度 1.290 v - - - 0.528 v --- 低 溫 度 1.282 v -0.620% 0.530 v + 0.379% 高 溫 度 1.268 v - 1.705% 0.512 v *0.030% 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 20 310417 經濟部智慧財產局員工消費合作社印5取 448 60 9 A7 B7 五、發明說明) 比較例(第8圖)之模擬結果如下: .Vc = VA + VB + VBE2 -........ (1) a Vc / 5 τ = 3 VA Id T + 3 VB / 3 T-3 VBE2 / 5 T ......... . (2) In the formula: 3VC / 3 T represents the temperature change voltage of Vc2. (Hereinafter it is expressed as / T) VB = VBE3X (R4 / R5 + l) .......... (3) Also, because each resistance is only 4, the temperature coefficient of R4 is the same, dVs = d VBE3x (R4 / R5 + D ......---- (4) The base-emitter voltage VBE2 and VBEs of each transistor are the same (can be realized by thermal bonding), so substitute (4) into (2) , Obtained, 3 Vc = a vBE3X (R4 / R5) + VA .... (5) If the temperature of the collector voltage Vc must be changed to zero, 3Va =:-9VBE3X ( R4 ^ R5) Among them, if 3 VBE3 is the temperature coefficient of ordinary transistor -1.6X 1〇-3, 3 VA = 1.6X10 · 3 X (R4 / R5) 0 and because VA = R3X [2, such as I2 as Fixed, 3vA can be determined by the temperature coefficient K3 of the resistor Rj, that is, K3XVA = 1.6X10 -3x (R4 / R5) -I ----- 11 ---- installed! 11-" —Order--- ---- · {Please read the precautions on the back before filling this page) This paper size is applicable to China Solid State Standards (CNS) A4 (210 X 297 mm) 18 310417 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs ^ 48 6 0 9 A7 B7 V. Description of the invention (19) VA = 1.6X10 · 3 X {R4 / (K3R5) ---------- (5) If VA is set to (5), The voltage between the collectors Vc The temperature change is zero. However, if the current 12 is not time-dependent due to temperature, the current flowing into the base of the transistor is changed by the temperature coefficient of the resistor Ri '112. Therefore, the voltage νΑ is set in a cut and try manner. If the base current of the transistor is ignored, the emitter voltage of the transistor * ^ is: VE = -VBE1 + (Vj -Vf) XR2 / (RI + R2) + Vf 3 VE =-5 VBE1 + (3 V,-3 Vf) XR2 / (R: + R2) + Vf Because the temperature coefficient of the VBE # diode of the transistor is the same, and vc is based on the relationship of 3V1 = 3VBE2 which is set to be fixed. And dVE = 0. As described above, the temperature change of the emitter voltage VE can be made zero. Next, a description will be given of the transistor TR collector voltage 时 when the current 値 varies with the bias current source IB. , And the change of the emitter voltage VE is as follows: When the current 値 IB changes by 5 値 from the rated value, the voltage 乂! Changes 5 V 1 is 5 V! =: {R3 II (Ri + R2)} 5 IB where,丨 丨 indicates that the resistors are connected in parallel. The resistor R3 can be made small in the circuit configuration, so the variation of the current IB and the change in the voltage V are extremely small. Because the collector voltage vc of the transistor TR is vc = VBE2. ------------. Install ----- JJI order ---------- line (Please read the precautions on the back before filling this page) This paper size applies t National Standard (CNS) A4 (210 X 297 mm) 19 310417 448609 A7 B7 V. Description of the invention (2) Pressure VE is VE ^ Vi-Vf) XRz / iRdRj + vf. The current of the current source 1 ^ has a variation, which can also make the changes in the collector voltage Vc and the emitter voltage vE small. "Secondly," when the variation in the resistance resistance causes changes, the transistor 1 \ collector voltage vc and The change of the emitter voltage vE is as follows: If the voltage 乂 1 is: VI = (VA + VB) = 〇 + R 4 / R 5) XVB £ 3 + R 3 XI 2 The resistance to Rj varies, and the V of the ruler 3 changes. The amount 5 ¥ is: < 5 V! = 12 X 5 R 3 Due to the circuit configuration, the resistance 1 ^ 3 can be extremely small, and the variation of the voltage V caused by each resistance difference is very small. {Please read the precautions on the back before filling this page) The collector voltage V c can be determined by Ve =: V,-VBE2, and the two-emitter voltage VE: V £ · = (V 1-Vf) r2 > / (R1- R2) + Vf. Even if the resistances vary, the variation of the collector voltage VC and the emitter voltage VE can be extremely small. Here, from the sixth embodiment in Fig. 1: 1, the transistor TR set is examined. The changes in the polar voltage Vc and the emitter calendar 丨 VEi, and the results of the simulation (simuUtion) on the improvement of the ambient temperature are as follows. The temperature is selected from the standard temperature of 27 0 C, low temperature -30 ° C, high temperature 75 ° C »This implementation For example (Figure 11), the simulation results are as follows: Vc VE Standard temperature 1.290 v---0.528 v --- Low temperature 1.282 v -0.620% 0.530 v + 0.379% High temperature 1.268 v-1.705% 0.512 v * 0.030% This paper size applies to China National Standard (CNS) A4 210 X 297 mm) 20310417 Intellectual Property Office employee Economic Co-op plate 5 448 60 9 A7 B7 take five, description of the invention) Analog Comparative Example (FIG. 8) The results were as follows:

Vc VE 標準溫度 1.290 v -·· 0.528 v ---低溫度 1.080 v -16. 28% 0.339 v - 3 5.80% 高溫度 1.500 v +16.28% 0.718 v +36.00% 由上述結果。因本實施例係於偏壓用電阻1串聯二極 体D i、電晶体TRC,於電晶体集極與射極間,基極與射極 間,及集極分別連接之電阻R3, R4,R5B成溫度補償電 路》故電晶体TR之集極電壓Vc及射極電壓VE對周圍溫度變 化之變動,較不設溫度補償電路之比較例,爲小。 又於第11圖之第6實施例中,係以設置溫度補償電路 使,以使電晶体τΒ之集極電壓vc及射極電壓VE對周圍溫度 變化不產生變動爲例,說明可適用於第8圖之第4實施例。 唯,以偏壓電阻R2串聯二極体D,、電晶体TRC,於電晶体 集極與射極間,基極與射極間以及集極分別連接電阻R3, R4, R5,形成之溫度補償電路,對周圍溫度之變化,消除 電晶体TR之集極電壓Vc及射極電壓VE之變動,並不限於上 述實施例,亦可適用於在基極偏壓電路設置電流源18之 水晶振盪電路,以達同樣效果。 其次,以第13圖,第14圖及第15圖,說明本發明之第 7實施例如下: 第13圖爲本發明之水晶振盪電路圖係將第4實施例設 在第8圖中之電晶体TR射極與接地間之定電流源I,及偏 壓用定電流源IB,具體地以第1定電流源h,及第2定電 -—II--I--I [ I 1 i I---!| ^*fllnl — (請先閱讀背面之注—¥項再填寫本頁> 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 21 310417 448 6 〇 9 經濟部智«.財產局員工消費合作社印製 A7 B7 五、發明說明(22 ) 流源12表示外,同時,使電流設定電阻具有負溫度係數, 以改善電晶体TR射極電流之溫度特性。其他各點則與第8 圖相同|其與第8圖相同之部份均附與相同之符號6 在該第13圖中,第1定電流源I,係包含2個定電流源。 其第一個定電流源係連接於PNP型電晶体Q6與電源Vcc偏 壓用電阻1間,同時於電晶体Q6之基極施加定電壓V,。該 電晶体Q6,係於基極施加定電壓丫1,作爲定電流源作用》 與第8圖之偏壓用定電流源IB—樣,供給定電流至偏壓用 電阻Rt,R2,且將各電晶体TR,TRB之基極偏壓設定於定 電壓。 第1定電流源I,之另方定電流源係以具有負溫度特 性之電流設定電阻R6,與PNP型電晶体(^7串聯,同時,在 電晶体Q7之基極施加定電壓V,。該電晶体Q7係於基極施加 定電壓Vi,而與電流設定電阻R6,同時作爲定電流源作用, 而由集極輸出定電流基準電流IR。 第2定電流源12,係由連接集極及基極,而將射極接Q 之UPN型電晶體Q8及將基極接於上述電晶體Q8基極,而接 於電晶體TR射極與接地端間之UPN型電晶體Q9所成,而由 電晶體Q 8與Q 9構成電流鏡(c U r r e n t m i r r 〇 r)電路,該等電晶 體Q〆Qs係使用具有配對電晶體(pair transistor)同特性 者。然後,將第1電流源h之定電流之基準電流Ικ,供予 電流鏡電路。 如上述構成之第1定電流源h與第2定電流源12中,係 由第1定電流源L,將依據施加於電晶体〇7基極之定電壓 -i I I 11--II---裝 i — · — ]— 訂·—---I ·線 (請先Μ讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 22 310417 經濟部智慧財產局員工消費合作社印製 448609 A7 ___B7_____ 五、發明說明(23 ) V t及電流設定電阻R 6之電阻値以及電晶体Q7基極·*射極間 電壓等所決定之定電流,爲基準電流U予以輸出。 當該基準電流U,流入第2定電流源12之電晶体Q8時’ 基準電流IR亦向基極分流,自動形成使集極電流略等於基 準電流iR之偏壓,產生對應於電晶体Qs基極•射極間’使 集極流過基準電流IR所須之電壓。該電壓亦施加於電晶体 q9之基極,使具有相同特性之電晶体q9,以相同條件予以 偏壓,故'於電晶体Q9之集極流過與基準電流込同値之電 流,以顯示定電流特性。 上述第1定電流源1之電流設定電阻R6,於所述之前 例水晶振盪電路中,爲成積體電路而使用電晶体微形組件 (transistor module)之一部份。通常係使用利用基極擴散層 之擴散電阻。 利用基極擴散層之該擴散電阻,具有正溫度特性,成 爲對應於周圍溫度變化導致定電流源電流値變化之主因。 而與電流設定電阻R6—起形成定電流源之電晶体,雖有 基•射極間電壓、直流電流放大率等各種參數關係,唯電 晶体全体之溫度係數爲正値,同樣亦對應於周圍溫度之變 化成爲定電流源電流値變化之要因。 利用擴散電阻爲該電流設定電阻R6之前例水晶振盪電 路中,其對應周圍溫度變化。變化定電流源電流値主因的 擴散電阻及電晶体,同時具有正溫度係數》故於周圍溫度 上升時,逐漸減少定電流源之電流値。該結果,使水晶振 盪電路之輸出電壓位準,在高溫時,不可避免地下降。特 (請先Μ讀背面之注意事項再填寫本頁) 裝 - - ------- 訂----------線 本紙張尺度適用中國固家標準(CNS)A4規格(210 X 297公釐) 23 310417 448 609 經濟部智慧財產局員工消f合作社印制^ A7 B7 五、發明說明(24 ) 以第14圖表示該輸出電壓位準與溫度之變化。 、 第14圖係以峯値表示利用擴散電阻的電流設定電阻r6 之前例水晶振盪電路中,對應於溫度變化之輸出位準變化 圖。圖中,電源電壓Vcc係以5·5ν,3.3v,3.0v,及2.7\ 時爲例,表示其實測値。由該圖可知,高溫時,水晶振盪 電路之輸出位準,顯著地降低。 本發明爲解決利用擴散電阻前例的水晶振盪電路輸出 電壓位準對周圍溫度具顯著變化之問題》係以使用負溫度 係數電阻作爲第1定電流源1:之電流設定電阻R6〇使輸出 電壓位準可不因周圍溫度變化,而予以穩定化。具有負溫 度係數之電流設定電阻1,係以噴濺法(sputter),或CVD 法等形成薄膜電阻。薄膜電阻有多種,其中以多晶矽 (polysilicon)電阻爲佳。 若將該具有負溫度係數之多晶矽電阻,使用爲第1定 電流源I,之電流設定電阻R6時與電流設定電阻R6—起構 成定電流源之電晶体係如上述,由基•射極間電壓及直流 電流放大率等各參數之關係,該電晶体全体之溫度係數爲 正値,兩者受周圍溫度變化之影響相互抵消,故可抑制定 電流源之電流變化。該結果,可使水晶振盪電路之輸出電 壓位準,在廣寬溫度範圍中維持其穩定。該狀態表示於第 1 5圖。 第1 5圖爲分別以本發明使用多晶矽電阻之水晶振盪電 路,及使用擴散電阻之前例水晶振盪電路爲電流設定電阻 尺6之輸出位準峯値與溫度變化之相關圖,圖中,係以電源 ·. I----- 衣 i—!1 訂·!--•線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用令國國家標準(CNS)A4規格(210 X 297公釐) 24 310417 448609 A7 B7 五、發明說明(25 ) (請先閱讀背面之注意事項再填寫本頁) 電壓V c c 3.0 V爲例,表示其實測値。由圖可知,以多晶砂 電阻爲電流設定電阻Rs之本發明水晶振盪電路,較前例, 在寬範圍的輸出電壓位準上穩定。以周圍溫度251爲基 準,由低溫側(-40eC )至高溫側(+ll〇°C ),其輸出電壓 位準之變化比率。於使用擴散電阻之前例爲20%,而使用 多晶矽電阻的本發明爲6%,可知改善效果極大。 如於上述第13圖之第7實施例,在水晶振盪電路周圍 溫度變動時,由第1定電流源h之電流設定電阻1{6爲負溫 度係數之電阻,可顯著地減小定電流源電流値對溫度之變 化*較前例,可在寬範圍使輸出電壓位準予以穩定共振盪。 因此,得以使水晶振盪電路之振盪輸出,不受周阖溫度影 響,穩定升起。又,在定電流源電流値對溫度變化顯著減 小時,不需回授(feed back)電路等特別附加電路,可 僅使用負溫度係數之電阻爲電流設定電阻R6,故使電路之 構成簡化。又因,水晶振盪電路之輸出電壓位準,可不受 周圍溫度之影響而穩定,不必預估電路電流値之餘裕,而 使電流源電流値得以爲較小之値。 經濟部智慧財產局員工消費合作社印製 於第13圖之第7實施例中,係以負溫度係數之電阻爲 基準電流用定電流源第1定電流源I,的電流設定電阻R6, 顯著減小定電流源電流値對溫度之變化,以在寬範圍穩定 振盪輸出電壓位準爲例,說明適用於第4實施例之第8圖之 水晶振盪電路。然而,水晶振盪電路之水晶振盪電路穩定 化•並不限於上述之實施例*同樣適用於在電晶体TR射極 與接地間設置定電流源形式之水晶振盪電路,以獲得同樣 本紙張尺度適用t國國家標準(CNS)A4規格(210 X 297公釐) 25 310417 448609 經濟部智慧財產局員工消費合作社印製 A7 B7____ 五、發明說明(26 ) 效果。 1 其次,參照第16圖說明本發明第8實施例如下:該圖係 表示於本發明之水晶振盪電路中電路構成元件’積集於同 —半導體基板內構成爲1C之水晶振盪電路者。 圖中,係將雙點鎖線框內,標記有1C的電晶体,電阻, 電容器等電路構成元件積集於同一半導體基板內’又爲將 各電路元件與第4圖之元件對應,標註相同符號*電晶体 ,電晶'体Q5及定電流源IB,係對應於第4圖之定電流源 I,在電晶体1\射極電路,形成流過直流電流之具體定電 流電路。電晶体q3,電晶体q5,連接成電流鏡,電晶体q3 之電流與電晶体q5之電流成比,電晶体1之電流則等於定 電流源I之電流。定電流源Ii之電流對溫度及電源電壓 無依存性,故於電晶体1\射極電路,供給穩定之直流電流》 電晶体Q4接於二極体,與電阻R2共爲電壓分割用電阻之一 部份。又,E爲接地線。 第16圖中,電容器q,(:2及Cc,不與水晶振盪電路X 成爲積體化對象,乃因,須對應於水晶振盪電路之規格或 負載之狀況,選擇適切之電容器q,<:2及Cc。亦可將電容 器G,(:2及Cc作爲積體化對象積集於同一基板。 該圖係以第2實施例之第4圖中之水晶振盪電路爲對 象1將電路構成元件積集於同一半導體基板以構成1C»亦 可將其他如第1實施例(第1圖),第3實施例(第7圖),第4實 施例(第8圖),第5實施例(第9圖),第6實施例(第11圖), 第7實施例(第13圖)爲對象,將電路構成元件積集於同一 (請先閱讀背面之注意事項再填寫本頁) 装-----II'1 訂---------. 本紙張尺度適用中國0家標準(CNS)A4規格(210 >^97公釐) 26 310417 448609 A7 B7 五、發明說明(27 ) 半導體基板,構成1C之水晶振盪電路。 . (請先閱讀背面之注意事項再填寫本頁) 在第16圖實施例中,係將電路構成元件積集於同一半 導體基板1C構成。取代以個別零件組裝成電路之所謂分立 元件(discret)構成。使水晶振盪電路小型、輕量小型化。 以適用攜帶型電子機器。 本發明能將負性電阻,予以增大。除縮短振盪上升時 間Ts外,尙可獲得各種具有特徵之效果。即如增大負性電 阻可使振盪繼續中的振盪位準及振盪頻率穩定可減少由外 部原因引起之變動》 又於電源電壓變動時,保持電晶体基極偏壓於定値, 可將水晶振擾電路之振邀頻率變化,顯著減少。亦即,得 以改善水晶振盪電路中振盪頻率變化之電源電壓依存性。 又,在水晶振盪電路周圍溫度變動時,可由設置與偏 壓電阻串聯之二極体、電晶体及與該電晶体分別連接之溫 度補償電路,使電晶体TR之集極電壓ve,及射極電壓VE, 排除對溫度變化之變動。確保輸出動態範圍vcc -VQUT,Vc VE standard temperature 1.290 v-0.528 v --- low temperature 1.080 v -16. 28% 0.339 v-3 5.80% high temperature 1.500 v + 16.28% 0.718 v + 36.00% From the above results. Because this embodiment is a resistor R3, R4 connected to the bias resistor 1 in series with the diode Di and the transistor TRC, between the transistor collector and the emitter, between the base and the emitter, and the collector, respectively. R5B becomes a temperature compensation circuit. Therefore, the change of the collector voltage Vc and the emitter voltage VE of the transistor TR to the surrounding temperature is smaller than that of a comparative example without a temperature compensation circuit. In the sixth embodiment of FIG. 11, a temperature compensation circuit is provided so that the collector voltage vc and the emitter voltage VE of the transistor τB do not change the ambient temperature. As an example, the description is applicable to the first embodiment. The fourth embodiment of FIG. 8. However, the bias resistor R2 is connected in series with the diode D, and the transistor TRC, and the resistors R3, R4, and R5 are connected between the transistor collector and the emitter, the base and the emitter, and the collector, respectively, to form temperature compensation. The circuit eliminates changes in the collector voltage Vc and the emitter voltage VE of the transistor TR for changes in the ambient temperature, and is not limited to the above embodiment. It can also be applied to the crystal oscillation where the current source 18 is set in the base bias circuit. Circuit to achieve the same effect. Next, the seventh embodiment of the present invention will be described with reference to FIGS. 13, 14 and 15: FIG. 13 is a circuit diagram of a crystal oscillation circuit of the present invention. The fourth embodiment is a transistor provided in FIG. 8. Constant current source I between TR emitter and ground, and constant current source IB for bias, specifically the first constant current source h, and the second constant current --- II--I--I [I 1 i I ---! | ^ * fllnl — (Please read the note on the back— ¥ item before filling out this page> This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 21 310417 448 6 〇9 Printed by the Ministry of Economic Affairs «. Property Bureau employee consumer cooperative A7 B7 V. Description of the invention (22) Outside the current source 12 is shown, and the current setting resistor has a negative temperature coefficient to improve the temperature characteristics of the transistor TR emitter current. The other points are the same as those in Fig. 8 | The same parts as in Fig. 8 are assigned the same symbols. 6 In this Fig. 13, the first constant current source I includes two constant current sources. A constant current source is connected between the PNP transistor Q6 and the resistor Vcc biasing resistor 1, and a constant voltage V is applied to the base of the transistor Q6. The transistor Q6 It is based on the application of a constant voltage γ1 at the base to function as a constant current source. It is the same as the constant current source IB for the bias voltage shown in Fig. 8. It supplies a constant current to the bias resistors Rt and R2, and the transistors TR The base bias voltage of TRB is set to a constant voltage. The first constant current source I, and the other constant current source is a current setting resistor R6 with a negative temperature characteristic, which is connected in series with a PNP transistor (^ 7, at the same time, in A constant voltage V is applied to the base of the transistor Q7. The transistor Q7 applies a constant voltage Vi to the base and functions as a constant current source at the same time as the current setting resistor R6, and the constant current reference current IR is output from the collector. The second constant current source 12 is connected to the collector and the base, the emitter is connected to the UPN transistor Q8 of Q, the base is connected to the base of the transistor Q8, and the transistor TR is connected to the emitter of the transistor. The UPN transistor Q9 between the ground terminals is formed by the transistors Q 8 and Q 9 to form a current mirror (c Urrentmirror) circuit. These transistors Q〆Qs use pair transistor Those with the same characteristics. Then, the reference current Iκ of the constant current of the first current source h is supplied to the current mirror In the first constant current source h and the second constant current source 12 configured as described above, the first constant current source L is based on the constant voltage -i II 11--II applied to the base of the transistor 07. --- install i — · —] — order · —--- I · line (please read the notes on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 (210x297 mm) 22 310417 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 448609 A7 ___B7_____ V. Description of the invention (23) The resistance of V t and the current setting resistor R 6 6 and the transistor Q7 base and * emitter voltage The current is output as the reference current U. When the reference current U flows into the transistor Q8 of the second constant current source 12, the reference current IR is also shunted to the base, automatically forming a bias that causes the collector current to be slightly equal to the reference current iR, generating a base corresponding to the transistor Qs. The voltage between the emitter and the emitter is required for the collector to flow the reference current IR. This voltage is also applied to the base of transistor q9, so that transistor q9 with the same characteristics is biased under the same conditions. Therefore, a current that is the same as the reference current flows through the collector of transistor Q9 to display the fixed value. Current characteristics. The above-mentioned current setting resistor R6 of the first constant current source 1 uses a transistor module in order to form an integrated circuit in the aforementioned crystal oscillation circuit. Generally, a diffusion resistor using a base diffusion layer is used. The diffusion resistance of the base diffusion layer has a positive temperature characteristic, and becomes a main cause of a constant current source current change corresponding to a change in ambient temperature. The transistor that forms a constant current source with the current setting resistor R6, although there are various parameter relationships such as the base-emitter voltage, the DC current amplification factor, etc., but the temperature coefficient of the entire transistor is positive, which also corresponds to the surroundings. The change in temperature becomes the main cause of the change in the current of the constant current source. In the previous crystal oscillator circuit, a resistor R6 was set for this current using a diffusion resistor, which corresponds to changes in ambient temperature. Diffusion resistors and transistors that change the current of the constant current source 値 have a positive temperature coefficient. Therefore, when the ambient temperature rises, the current of the constant current source 减少 is gradually reduced. As a result, the output voltage level of the crystal oscillator circuit inevitably drops at high temperatures. Special (please read the precautions on the back before filling in this page) Packing--------- Ordering ---------- The paper size of the paper is applicable to the Chinese solid standard (CNS) A4 specification (210 X 297 mm) 23 310417 448 609 Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by a cooperative ^ A7 B7 V. Description of the invention (24) The change in output voltage level and temperature is shown in Figure 14. Fig. 14 is a graph showing the peak value of the current setting resistor r6 using a diffusion resistor. In the previous example crystal oscillator circuit, the output level changes according to temperature changes. In the figure, the power supply voltage Vcc is taken as an example of 5 · 5ν, 3.3v, 3.0v, and 2.7 \, which indicates actual measurement. As can be seen from the figure, the output level of the crystal oscillator circuit decreases significantly at high temperatures. The present invention is to solve the problem that the output voltage level of the crystal oscillation circuit using the previous example of the diffusion resistance significantly changes the ambient temperature. The current setting resistance R6 using a negative temperature coefficient resistor as the first constant current source 1: makes the output voltage level. It must not be stabilized by ambient temperature changes. The current setting resistor 1 having a negative temperature coefficient is formed by a thin film resistor by a sputtering method, a CVD method, or the like. There are many types of thin film resistors, and polysilicon resistors are preferred. If the polycrystalline silicon resistor with a negative temperature coefficient is used as the first constant current source I, the current setting resistor R6 and the current setting resistor R6 together constitute a transistor system that constitutes a constant current source as described above. The relationship between various parameters such as voltage and DC current amplification factor, the temperature coefficient of the entire transistor is positive, and the two cancel each other out due to the influence of the surrounding temperature change, so the current change of the constant current source can be suppressed. As a result, the output voltage level of the crystal oscillator circuit can be maintained stable over a wide temperature range. This state is shown in FIG. 15. Fig. 15 is a correlation diagram of the output level peak value 値 and temperature change of the current setting resistor scale 6 using the crystal oscillation circuit using polycrystalline silicon resistors of the present invention and the crystal oscillation circuit of the previous example using a diffusion resistor as the current. Power supply .. I ----- 衣 i—! 1 Order! -• Line (Please read the precautions on the back before filling this page) This paper size applies the national standard (CNS) A4 (210 X 297 mm) 24 310417 448609 A7 B7 V. Description of the invention (25) ( (Please read the precautions on the back before filling out this page) The voltage V cc 3.0 V is taken as an example to indicate actual measurement. As can be seen from the figure, the crystal oscillation circuit of the present invention using polycrystalline sand resistance as the current setting resistance Rs is more stable than the previous example over a wide range of output voltage levels. Based on the ambient temperature of 251, the change ratio of the output voltage level from the low temperature side (-40eC) to the high temperature side (+ 110 ° C). It is 20% before the example using the diffusion resistor, and 6% of the present invention using the polycrystalline silicon resistor. As in the seventh embodiment of the above-mentioned FIG. 13, when the temperature around the crystal oscillation circuit fluctuates, the current setting resistance 1 {6 of the first constant current source h is a resistance with a negative temperature coefficient, which can significantly reduce the constant current source. The change of the current 値 to the temperature * Compared with the previous example, the output voltage level can be stably co-oscillated over a wide range. Therefore, the oscillating output of the crystal oscillating circuit can be stably raised without being affected by the ambient temperature. In addition, when the constant current source current 小时 significantly reduces the temperature change, there is no need for a special additional circuit such as a feed back circuit, and only a resistor having a negative temperature coefficient can be used as the current setting resistor R6, thereby simplifying the circuit configuration. In addition, the output voltage level of the crystal oscillator circuit can be stabilized without being affected by the ambient temperature. It is not necessary to estimate the margin of the circuit current, so that the current source current can be made smaller. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed in the seventh embodiment of FIG. 13, uses the resistance of the negative temperature coefficient as the reference current, and the current setting resistance R6 of the first constant current source I, which is a significant reduction. The change in the temperature of the small constant current source 値 over temperature is described by taking a stable oscillation output voltage level in a wide range as an example to describe the crystal oscillation circuit applicable to Fig. 8 of the fourth embodiment. However, the crystal oscillation circuit of the crystal oscillation circuit is stable. It is not limited to the above-mentioned embodiment. * It is also applicable to the crystal oscillation circuit in the form of a constant current source between the transistor TR emitter and ground to obtain the same paper size. National Standard (CNS) A4 Specification (210 X 297 mm) 25 310417 448609 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7____ 5. Description of the Invention (26) Effect. 1 Next, an eighth embodiment of the present invention will be described with reference to FIG. 16: This figure shows that the circuit components in the crystal oscillation circuit of the present invention are integrated in the same crystal semiconductor circuit as a 1C crystal oscillation circuit. In the figure, circuit components such as transistors, resistors, and capacitors marked with 1C in a two-point lock wire frame are accumulated in the same semiconductor substrate. In order to correspond to each circuit element and the element in FIG. 4, the same symbols are marked. * Transistor, transistor Q5 and constant current source IB correspond to the constant current source I in Fig. 4. In the transistor 1 \ emitter circuit, a specific constant current circuit flowing a DC current is formed. Transistor q3 and transistor q5 are connected to form a current mirror. The current of transistor q3 is proportional to the current of transistor q5, and the current of transistor 1 is equal to the current of constant current source I. The current of the constant current source Ii has no dependence on the temperature and the power supply voltage. Therefore, the transistor 1 \ emitter circuit provides a stable DC current. The transistor Q4 is connected to the diode, and the resistor R2 is the voltage division resistor. a part. E is a ground line. In Figure 16, the capacitors q, (: 2 and Cc are not integrated with the crystal oscillator circuit X, because the capacitor q must be selected in accordance with the specifications or load conditions of the crystal oscillator circuit, < : 2 and Cc. Capacitors G, (: 2 and Cc can also be accumulated on the same substrate as the object of integration. This figure is based on the crystal oscillator circuit in the fourth embodiment of the second embodiment as the object 1 and the circuit is configured The components are accumulated on the same semiconductor substrate to form 1C. Other embodiments such as the first embodiment (FIG. 1), the third embodiment (FIG. 7), the fourth embodiment (FIG. 8), and the fifth embodiment may also be used. (Fig. 9), 6th embodiment (Fig. 11), 7th embodiment (Fig. 13), the circuit components are integrated in the same (please read the precautions on the back before filling this page) ----- II'1 Order ---------. This paper size is applicable to 0 Chinese standards (CNS) A4 specifications (210 > ^ 97 mm) 26 310417 448609 A7 B7 V. Description of the invention (27) The semiconductor substrate constitutes a 1C crystal oscillator circuit. (Please read the precautions on the back before filling out this page) In the embodiment in Figure 16, the The circuit components are integrated on the same semiconductor substrate 1C. Instead of the so-called discrete components that are assembled with individual parts to form a circuit. The crystal oscillator circuit is small and lightweight. It is suitable for portable electronic equipment. Increase the negative resistance. In addition to shortening the oscillation rise time Ts, 尙 can obtain various characteristic effects. That is, if the increase of the negative resistance can make the oscillation level and oscillation frequency stable during oscillation, it can be reduced by external The change caused by the reason "and when the power supply voltage changes, keeping the base of the transistor biased to a fixed voltage can change the frequency of the crystal oscillator circuit and significantly reduce it. That is, it can improve the oscillation frequency of the crystal oscillator circuit. Dependence of the power supply voltage. When the temperature around the crystal oscillation circuit fluctuates, a diode, a transistor in series with the bias resistor, and a temperature compensation circuit connected to the transistor can be provided to make the collector voltage of the transistor TR. ve, and the emitter voltage VE, to exclude changes in temperature changes. Ensure the output dynamic range vcc -VQUT,

Vc -V0UT,使水晶振盪電路之能力不受限制地有效利用。 經濟部智慧財產局員工消费合作社印製 同理,由該溫度補償電路可對偏壓用定電流源18之 參差及偏壓用分壓電阻器R,,R2之參差引起之變化,減 少對電晶体1\集極電壓vc,及射極電壓VE之變動低減,以 確保由射極電壓νε爲中心的上限電壓,下限電壓Vc -VE I Ο-νΕ*可允許構成水晶振盪電路之定電流源IB,電阻Ri, R2之參差。故構成水晶振盪電路之元件的選擇較易》 又,於水晶振盪電路周圍溫度變動時,係以負溫度特 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 27 310417 448 6 0 9 A7 B7 五、發明說明(28 ) (請先閱讀背面之注意事項再填寫本頁) 性之電阻爲基準電流用定電流源之電流設定電阻R6,使定 電流源之電流値,由溫度發生變化,顯著地減少。其前例 比較,可在寬範圍內穩定輸出電壓位準之振盪《因而,使 水晶振盪電路,得不受周圍溫度之影響穩定升起β又於減 少定電流源之電流値因溫度之變化時,即可不須回授電路 等特別附加電路,僅以負溫度係數之電阻爲電流設定電 阻。故得以簡化電路之構成《又,因爲水晶振盪電路之輸 出電壓位準,不受周圍溫度影饗而穩定,故不必預估電路 電流値之餘裕,而將電流源之電流値,設爲較小値。 又於今後,因水晶振盪元件之小型化,而使其等價串 聯電阻Rx增大,亦可由實質上變大的負性電阻吸收,故 對應於水晶振盪電路之小型化,輕童化。 同理,可由實質上增大之負性電阻,能採用較大參差 之等價串聯電阻的水晶振盪元件。 經濟部智慧財產局員工消費合作社印製 以上係就本發明各實施例,以使用補償頻率溫度特性 之溫度補償型水晶振盪電路TCXO爲例予以說明。但本發 明並不以此爲限,亦可適用於,直接利用水晶振盪元件特 性之封裝(Package)水晶振盪電路SPXO,由外部之控制電 壓變化或調變輸出頻率之電壓控制型水晶振盪電路 VCXO,以及於恆溫槽中控制溫度予以利用之OCXO等各種 水晶振盪電路。 且可於本發明在上述水晶振盪電路待機狀態時進行電 源間歇導通(on),而與基地局通訊後,確定有無來訊,如 有來訊時則切換爲連續通電之所謂間欠動作。使用於如第 本紙張尺度適用中0國家標準(CNS)A4規格(210 X 297公釐) 28 310417 448 6 0 9 A7 B7 五、發明說明(29 ) 19圖所示之攜帶電話機等之振盪電路。 - (請先閱讀背面之注意事項再填寫本頁) 如上,可將本發明各實施例之水晶振盪電路,使用於 攜帶通訊機之振盪電路,以減低攜帶通訊機之電力消耗。 又如上述之本發明各實施例,係以水晶振動元件作爲 振動之元件的水晶振盪電路予以說明。唯該振盪電路之振 動元件,不限於水晶振動元件。亦可使用陶瓷等其他壓電 元件。此時,亦可獲得與各實施例相同效果。 【本發明之效果】 如依本發明申請專利範圍第1項記載之構成,其由施 加電源電壓,至振盪輸出成爲額定輸出電壓位準及額定振 盪頻率之振盪狀態,所需之振盪上升時間1^,係較習用之 使用射極電阻之振盪電路的振盪上升時間Ts爲短》 經濟部智慧財產局員工消費合作社印製 此乃習用水晶振盪電路之振盪上升時間Ts,係較使用 陶瓷振動元件等其他壓電元件之振盪電路長(通常爲4至 5ms)。此種長振盪上升時間Ts,在適用水晶振盪電路時, 尤會產生問題。本發明可在施加電源電磨後,振盪輸出成 爲額定輸出電壓位準及額定振盪頻率之振盪狀態止所需之 振盪上升時間Ts,可特別縮短。故可擴大水晶振盪電路之 可適用範圍》在該振盪上升時間Ts之間,亦可減少無效電 力之消耗。 如依本發明申請專利範圍第2項記載之構成,與申請 專利範圍第1項同理,由施加電源電壓Vcc開始,到振盪輸 出成爲額定輸出電壓位準及額定振盪頻率(±i ppm)之振 盪狀態。所需之振盪上升時間1^,較習用使用射極電阻之 本紙張尺度適用令國國家標準(CNS)A4規格(2】〇x297公釐) 29 310417 448609 A7 B7 五、發明說明(3〇 ) 振盪電路的振盪上升時間Ts爲短》 * (請先閱讀背面之注意事項再填寫本頁) 又於,定狀振盪狀態之振盪位準及振盪頻率均穩定, 且不增加消耗電力。 如依本發明申請專利範圍第3項記載之構成,可獲得 與申請專利範圍第2項相同之效果。更因第1電晶体集極與 第2電晶体疊接,由該第2電晶体集極與集極電阻連接點取 出振盪輸出。可由第2電晶体之緩衝放大機能,在輪出端 連接的貪載變動時,將該負載變動之影響,由具有緩衝放 大器機能之第2電晶体予以緩和。因此,在負載變動時, 亦能使振盪電路之振盪更爲穩定。 如依本發明申請專利範圍第4項記載之構成 > 可獲得 與申請專利範圍第2項相同之效果外,同時,因水晶振盪 電路之輸出信號取出點爲電晶体之射極側,故不須於電晶 体之集極與電源間,設置集極電阻,可使振盪電路小型化 及輕童化。 經濟部智慧財產局員工消费合作社印製 如依本發明申請專利範圍第5項記載之構成,可獲得 與申請專利範圍第3項相同之效果外,同時,於電源電壓 Vcc變動時,亦可將基極偏壓保持於一定値’以使振盪電 路振盪頻率的變化顯著減少,因而可改善振盪電路之電源 電壓依存性。 如依本發明申請專利範圍第6,7項記載之構成’在振 盪電路周圍溫度變化時,因設有與偏壓電阻串聯之二極 体,電晶体,及分別與該電晶体連接之電阻形成之溫度補 償電路。可使電晶体TR之集極電壓Vc及射極電壓VE ’不對 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 30 310417 448609 經濟部智慧財產局員工消费合作杜印製 A7 B7 五、發明說明(3i ) 周圍溫度變化,得以充分確保輸出動態範圍vcc t νουτ, vc - VQUT,而不受限於振盪電路之能力能有效利用》 同理,由溫度補償電路對偏壓定電流源之參差偏壓分 壓電阻之參差產生之變化•能使電晶体1\集極電壓Vc及射 極電壓VE不變動,以確保以射極電壓乂£爲中心之上限電 壓及下限電壓Vc -νΕ,0 ·νΕ。故得容易選擇構成振盪 電路之元件。 如伕本發明申請專利範圍第8,9,10,及11項記載之 構成,在振盪電路周圍溫度變動時,以負溫度特性之電阻 爲基準電流用定電流源之電流設定電阻,得以使定電流源 之電流値變化,對溫度變化顯著減少,故高溫時之輸出電 壓位準穩定,振盪輸出可不受周圍溫度之影響而穩定升 起。 又,在使定電流源電流値因溫度之變化減小時,不須 回授電路等特別之附加電路,僅以負溫度係數之電阻爲電 流設定電阻,故可使電路構成簡化。 又,振盪電路之輸出電壓位準不受周圍溫度影響而穩 定,不必預估電路電流値之餘裕,可使電流源電流値爲較 小之値。 如依本發明申請專利範圍第12項記載之構成,當然可 獲得申請專利範圍第1至第7項記載之效果。且以電路構成 元件積集於同一半導體基板,構成1C,以取代個別零件裝 組構成電路之分立構成。可適用於攜帶型電子機器,使振 盪電路小型,輕量爲袖珍型(compect)。 :----------^*------- 訂--------. (請先閱讀背面之注意事項再填寫本頁) 本紙張又度適用中國國家標準(CNS)A4規格(2〗0 X 297公釐) 31 310417 經濟部智慧財產局員工消费合作社印製 448609 A7 B7 五、發明說明(32 ) 如依本發明申請專利範圍第1 3項記載之構成,係以水 晶振動元件爲振動元件,可使申請專利範圍第1至7項記載 之效果更高。 如依本發明申請專利範圍第14項記載之構成,可在進 行間欠動作之攜帶通訊機,可提早使內藏水晶振盪器之振 盪升起,故能減少無效電力消耗。 【附圖簡單說明】 第1圖'爲表示有關本發明第1實施例之水晶振盪電路 圖。 第2圖爲表示第1圖之水晶振盪電路之交流等價電路 圖。 第3圖爲第2圖之等價電路圖。 第4圖爲表示有關本發明第2實施例之水晶振盪電路 圖* 第5圖(a)( b)爲表示設定各元件具體數値之本發明水晶 振盪電路及其振盪上升特性圖》 第6圖(a)( b)爲表示設定各元件數値具體之習用水晶振 盪電路及其振盪上升特性圖。 第7圖爲表示有關本發明第3實施例之水晶振盪電路 圖。 第8圖爲表示有關本發明第4實施例之水晶振盪電路 圖。 第9圖爲表示有關本發明第5實施例之水晶振盪電路 圖。 ^------------ ^-------訂----------線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 32 310417 448 6 09 經濟部智慧財產局員工消費合作杜印製 A7 B7 五、發明說明(33 ) 第10圖爲表示有關本發明第5實施例之水晶振盪電路之 電源電壓頻率特性圖。 第II圖爲表示有關本發明第6實施例之水晶振盪電路 第12圖爲表示有關本發明第6實例之水晶振盪電路電壓 關係圖》 第13圖爲表示有關本發明第7實施例之水晶振盪電路 圖。 第14圖爲有關本發明第7實施例之前例水晶振盪電路中 對溫度變化之輸出位準關係圖。 第15圖爲有關本發明第7實施例中,對溫度變化之水晶 振盪電路之輸出位準關係圖。 第16圖爲表示有關本發明第8實施例之稹集化水晶振盪 電路圖。 第17圖爲表示習用水晶振盪電路圖。 第18圖爲表示習用水晶振盪電路之振盪上升特性圖。 第19圖爲表示具備水晶振盪電路爲構成要件之攜帶電 話機的構成圖》 【符號說明】 X 水晶振盪元件 tr 電晶体 T r b 電晶体 I 疋電流源 -------II I I I ^ i — u— ^«11----i . (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中园國家標準(CNS)A4規格do X 297公爱) 33 310417Vc -V0UT makes the ability of crystal oscillator circuit to be used effectively without restriction. The same is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The temperature compensation circuit can reduce the variation caused by the bias current constant source 18 and the bias voltage divider resistors R, and R2 to reduce the power consumption. The crystal 1 \ collector voltage vc and the emitter voltage VE are reduced and reduced to ensure that the upper limit voltage is centered on the emitter voltage νε, and the lower limit voltage Vc -VE I Ο-νΕ * allows the constant current source constituting the crystal oscillation circuit. IB, the difference between resistors Ri and R2. Therefore, the selection of the components that make up the crystal oscillation circuit is easier. ”Also, when the temperature around the crystal oscillation circuit fluctuates, the paper standard of the negative temperature applies the Chinese National Standard (CNS) A4 specification (210x297 mm) 27 310417 448 6 0 9 A7 B7 V. Description of the invention (28) (Please read the notes on the back before filling this page) The resistance is based on the current setting resistor R6 of the constant current source for the reference current, so that the current of the constant current source is generated by temperature. Change, significantly reduced. Compared with the previous example, the oscillation of the output voltage level can be stabilized in a wide range. Therefore, when the crystal oscillation circuit is not affected by the ambient temperature, it can rise steadily and reduce the current of the constant current source due to temperature changes. That is, there is no need for special additional circuits such as a feedback circuit, and only a resistor with a negative temperature coefficient is used as the current setting resistance. Therefore, the structure of the circuit can be simplified. Also, because the output voltage level of the crystal oscillation circuit is not affected by the ambient temperature and is stable, it is not necessary to estimate the margin of the circuit current, and the current of the current source is set to be small. value. In the future, due to the miniaturization of the crystal oscillating element, the equivalent series resistance Rx will increase, and it can also be absorbed by a substantially larger negative resistance. Therefore, it corresponds to the miniaturization and lightness of the crystal oscillating circuit. In the same way, it is possible to use a substantially oscillating negative resistance, and a crystal oscillator with an equivalent series resistance with large variations can be used. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The above is a description of each embodiment of the present invention, using a temperature-compensated crystal oscillation circuit TCXO that compensates for frequency-temperature characteristics as an example. However, the present invention is not limited to this, and can also be applied to a package crystal oscillation circuit SPXO that directly utilizes the characteristics of the crystal oscillation element, and a voltage-controlled crystal oscillation circuit VCXO that controls the change of the external voltage or adjusts the output frequency. , And various crystal oscillator circuits such as OCXO, which are controlled in a constant temperature bath for use. In the present invention, the power supply may be intermittently turned on during the standby state of the crystal oscillation circuit, and after communicating with the base station, it is determined whether there is an incoming call, and if there is an incoming call, it is switched to a so-called intermittent action which is continuously energized. Used in the national standard (CNS) A4 specification (210 X 297 mm) as applicable in this paper standard 28 310417 448 6 0 9 A7 B7 V. Description of the invention (29) 19 Oscillation circuits of mobile phones and other devices as shown in Figure 19 . -(Please read the notes on the back before filling this page) As above, the crystal oscillator circuit of each embodiment of the present invention can be used in the oscillator circuit of the portable communication machine to reduce the power consumption of the portable communication machine. As in the above embodiments of the present invention, a crystal oscillation circuit using a crystal oscillation element as a vibration element will be described. The vibration element of this oscillating circuit is not limited to the crystal vibration element. Other piezoelectric elements such as ceramics can also be used. In this case, the same effects as those of the embodiments can be obtained. [Effects of the present invention] According to the structure described in item 1 of the scope of patent application of the present invention, the required oscillation rise time from the application of the power supply voltage to the oscillation state where the oscillation output becomes the rated output voltage level and the rated oscillation frequency 1 ^, It is shorter than the rise time Ts of the conventional oscillation circuit using an emitter resistor. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. This is the rise time Ts of the oscillation circuit of the conventional crystal oscillation circuit. The oscillation circuit of other piezoelectric elements is long (usually 4 to 5ms). Such a long oscillation rise time Ts may cause problems particularly when a crystal oscillation circuit is applied. According to the present invention, the oscillation rise time Ts required for the oscillation output to reach the oscillating state of the rated output voltage level and the rated oscillation frequency after the application of a power source electric mill can be shortened particularly. Therefore, the applicable range of the crystal oscillation circuit can be enlarged. Between this oscillation rise time Ts, the consumption of reactive power can also be reduced. According to the structure described in item 2 of the scope of patent application of the present invention, the same reason as in item 1 of the scope of patent application, starting from the application of the power supply voltage Vcc until the oscillation output becomes the rated output voltage level and the rated oscillation frequency (± i ppm) State of oscillation. The required oscillation rise time is 1 ^. Compared with the conventional paper size of the emitter resistor, the national standard (CNS) A4 specification (2) 0x297 mm is used. 29 310417 448609 A7 B7 V. Description of the invention (3) The oscillation rise time Ts of the oscillation circuit is short "* (Please read the precautions on the back before filling this page) Also, the oscillation level and oscillation frequency of the stationary oscillation state are stable without increasing power consumption. According to the constitution described in item 3 of the patent application scope of the present invention, the same effect as that in item 2 of the patent application scope can be obtained. Furthermore, the first transistor collector is overlapped with the second transistor, and the oscillation output is obtained from the connection point between the second transistor collector and the collector resistor. The buffer amplifier function of the second transistor can mitigate the effect of the load fluctuation when the load connected at the wheel output end is changed by a second transistor with a buffer amplifier function. Therefore, when the load changes, the oscillation of the oscillation circuit can be made more stable. For example, the structure described in item 4 of the scope of patent application of the present invention can obtain the same effect as the item 2 of the scope of patent application. At the same time, the output signal of the crystal oscillation circuit is at the emitter side of the transistor. It is necessary to set a collector resistor between the collector of the transistor and the power supply to make the oscillation circuit compact and lighter. If printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs according to the composition described in item 5 of the patent application scope of the present invention, the same effect as in item 3 of the patent application scope can be obtained. At the same time, when the power supply voltage Vcc changes, the The base bias voltage is kept at a certain value so that the change in the oscillation frequency of the oscillation circuit is significantly reduced, so that the power supply voltage dependency of the oscillation circuit can be improved. For example, according to the constitution described in the claims 6 and 7 of the scope of patent application of the present invention, when the temperature around the oscillating circuit changes, it is formed by providing a diode in series with the bias resistor, a transistor, and a resistor connected to the transistor, respectively. Temperature compensation circuit. The collector voltage Vc and emitter voltage VE of the transistor TR can not be applied to the Chinese paper standard (CNS) A4 (210 X 297 mm) for this paper size. A7 B7 V. Description of the invention (3i) The ambient temperature changes can fully ensure the output dynamic range vcc t νουτ, vc-VQUT, without being limited by the ability of the oscillation circuit to be effectively used. Similarly, the temperature compensation circuit is used to bias the bias voltage. The change caused by the uneven bias of the constant current source bias voltage divider resistor can make the transistor 1 \ collector voltage Vc and the emitter voltage VE not change to ensure the upper and lower voltage centered on the emitter voltage 乂 £ Vc -νΕ, 0 · νΕ. Therefore, it is easy to select the components constituting the oscillation circuit. For example, according to the structure described in items 8, 9, 10, and 11 of the scope of patent application for the present invention, when the temperature around the oscillation circuit fluctuates, the resistance of the negative temperature characteristic is used as the reference current and the current setting resistance of the constant current source is used to make the The change in the current of the current source significantly reduces the change in temperature, so the output voltage level is stable at high temperatures, and the oscillation output can rise steadily without being affected by the surrounding temperature. In addition, when the constant current source current is reduced due to temperature changes, no special additional circuit such as a feedback circuit is required, and only a resistor with a negative temperature coefficient is used as the current setting resistor, so that the circuit configuration can be simplified. In addition, the output voltage level of the oscillating circuit is stable without being affected by the surrounding temperature. It is not necessary to estimate the margin of the circuit current, and the current of the current source can be made smaller. According to the constitution described in item 12 of the patent application scope of the present invention, the effects described in item 1 to 7 of the patent application scope can of course be obtained. In addition, the circuit components are integrated on the same semiconductor substrate to form 1C, which replaces the discrete components of the circuits that are assembled by individual components. It can be applied to portable electronic equipment, making the oscillator circuit compact and light-weight compact. : ------------ ^ * ------- Order --------. (Please read the notes on the back before filling this page) This paper is suitable for China Standard (CNS) A4 specification (2〗 0 X 297 mm) 31 310417 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 448609 A7 B7 V. Description of the invention (32) As described in item 13 of the scope of patent application according to the present invention The structure uses a crystal vibration element as the vibration element, which can make the effects described in the scope of claims 1 to 7 of the patent application higher. According to the structure described in item 14 of the scope of patent application of the present invention, a portable communication device that can be operated infrequently can raise the oscillation of the built-in crystal oscillator earlier, so it can reduce the invalid power consumption. [Brief description of the drawings] Fig. 1 'is a diagram showing a crystal oscillation circuit according to a first embodiment of the present invention. Fig. 2 is an AC equivalent circuit diagram showing the crystal oscillation circuit of Fig. 1; Figure 3 is the equivalent circuit diagram of Figure 2. Fig. 4 is a diagram of a crystal oscillation circuit according to a second embodiment of the present invention * Fig. 5 (a) (b) is a diagram showing the crystal oscillation circuit of the present invention and its oscillation rising characteristics by setting the specific number of each element "Fig. 6 (A) (b) is a graph showing the specific crystal oscillator circuit for setting the number of each element and its oscillation rise characteristics. Fig. 7 is a diagram showing a crystal oscillation circuit according to a third embodiment of the present invention. Fig. 8 is a diagram showing a crystal oscillation circuit according to a fourth embodiment of the present invention. Fig. 9 is a diagram showing a crystal oscillation circuit according to a fifth embodiment of the present invention. ^ ------------ ^ ------- Order ---------- Line (Please read the notes on the back before filling this page) This paper size applies China National Standard (CNS) A4 Specification (210 X 297 mm) 32 310 417 448 6 09 Employee Co-operation, Intellectual Property Bureau, Ministry of Economic Affairs, Du Printed A7 B7 V. Description of Invention (33) Figure 10 shows the fifth aspect of the invention. Power supply voltage frequency characteristic diagram of the crystal oscillation circuit of the embodiment. Fig. II is a diagram showing a crystal oscillation circuit related to a sixth embodiment of the present invention. Fig. 12 is a diagram showing a voltage relation diagram of a crystal oscillation circuit according to a sixth embodiment of the present invention. Circuit diagram. Fig. 14 is a graph showing the relationship between the output levels to temperature changes in the crystal oscillator circuit of the previous example of the seventh embodiment of the present invention. Fig. 15 is a diagram showing the relationship between the output levels of the crystal oscillation circuit for temperature changes in the seventh embodiment of the present invention. Fig. 16 is a circuit diagram showing an integrated crystal oscillator according to an eighth embodiment of the present invention. Fig. 17 is a circuit diagram showing a conventional crystal oscillator. Fig. 18 is a graph showing an oscillation rising characteristic of a conventional crystal oscillation circuit. Figure 19 is a structural diagram of a mobile phone with a crystal oscillator circuit as a constituent element. [Symbol Description] X crystal oscillator element tr transistor T rb transistor I 疋 current source -------- II III ^ i — u— ^ «11 ---- i. (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification do X 297 public love) 33 310417

Claims (1)

H3 經濟部中央標準局員工福利委員會印製 第88HM189號專利申請案 申請專利範圍修正本 (90年3月1日) 1. 一種振盪電路,係具備:壓電振動元件、振盪電容器及 回授放大用電晶体,其特徵在·‘該振盪電路設置有與上 在述電晶体之射極串聯之定電流源者。 2. —種振盪電路,係由:壓電振動元件:該壓電振動元件 連接於其基極之電晶体;連接於電源間,以供給偏壓電 位於上述電晶体之基極的電阻;設於上述電晶体之基極 與射極間的第1電容器;設於上述電晶体之射極與一側 電源端子間的定電流源;與該定電流源並聯設置之第2 電容器;以及設在上述電晶体之集極與另一側電源端間 的輸出電阻所構成者。 3. —種振盪電路,係由:壓電振動元件:該壓電振動元件 連接於其基極之第1電晶体;與該第1電晶体串聯之第 2電晶体;接於電源間,以偏壓電位分別供給上述第1 電晶体之基極及第2電晶体之基極的電阻;設於上述第 1電晶体之基極與射極間的第1電容器;設於上述第1 電晶体之射極與一側電源端間的定電流源;與該定電流 源並聯之第2電容器;以及設在上述第2電晶体之集極 與另一側電源端間的輸出電阻所構成者。 4. 一種振盪電路,係由:壓電振動元件;該壓電振動元件 連接於其基極之電晶体;連接於電源間,以偏壓電位供 給上述電晶体之基極的電阻;設於上述電晶体之基極與 本紙張疋度適用中國國家標準(CNS )A4規格(YlO X 297公爱) 一 1 310417 4 48609 H3 經濟部中央標準局員工福利委員會印製 射極間的第1電容器:設於上述電晶体之射極與一側電 源端間的定電流源;以及與該定電流源並聯設置之第2 電容器所構成,而且由上述電晶体之射極與定電流源之 連接點輸出者β 5. —種振盪電路,係由:壓電振動元件:該壓電振動元件 連接於其基極之第1電晶体;與該第1電晶体串聯之第 2電晶体;設於上述第2電晶体之基極與一側電源端間 的偏壓用定電流源或設於上述第2電晶体之基極與另 一電源端間的偏壓用定電流源;分別設於上述第1電晶 体之基極與上述第2電晶体之基極間及上述第1電晶体 之基極與另一電源端間的偏壓用電阻;設於上述第1電 晶体之基極與射極間的第1電容器:設於上述第1電晶 体之射極與另一電源端間的定電流源;與該定電流源並 聯設置之第2電容器;以及設在上述第2電晶体之集極 與一側電源端間的輸出電阻所構成者° 6. —種振盪電路,係由:壓電振動元件;該壓電振動元件 連接於其基極之第1電晶体;與該第1電晶体串聯之第 2電晶体;設於上述第2電晶体之基極與一側電源端間 的偏壓用定電流源:分別設於上述第1電晶体之基極舆 上述第2電晶体之基極間及上述第1電晶体之基極與另 一側電源端間的偏壓用電阻;設於上述第1電晶体之基 極與射極間的第1電容器;設於前述第1電晶体之射極 與另一側電源端間的定電流源;與該定電流源並聯之第 2電容器;以及設在上述第2電晶体之集極與一電源端 本紙張尺廋適用中國國家標準(CNS)A4規格(210X297公策) 2 310417 448609 Η3 經濟部中央標準局員工福利委員會印製 間的輸出電阻所構成,其特徵在:在上述偏壓用電阻器 與上述第2電晶体之基極係設置有溫度補償電路者。 7. 如申請專利範圍第6項之振盪電路,其中’該溫度補償 電路係由:串聯於設在上述第1電晶体之基極與另一側 電源端間之偏壓用電阻的二極体;設在上述第2電晶体 之基極與上述另一側電源端間,射極則連接於另一側電 源端之電晶体:分別連接於該電晶体之基極與射極間以 及基極與集極間的電阻;以及與該電晶体之集極連接之 電阻所組成者。 8. 如申請專利範圍第1、2、3、4、5、6或7項之振盪電 路,其中,該電路定電流源之電流設定電阻係以具有負 溫度特性之電阻所構成者。 9. 如申請專利範圍第8項之振盪電路,其中,該定電流源 係以:具有電流設定電阻之基準電流用定電流源;及接 受該基準電流用定電流源基準電流的電流鏡電路所構 成者。 1 〇.如申請專利範圍第8項之振盪電路,其中,該電流設定 電阻係以薄膜電阻構成者。 11. 如申請專利範圍第9項之振盪電路,其中,該電流設定 電阻係以薄膜電阻構成者。 12. 如申請專利範圍第丨、2、3、4、5、6或7項之振盪電 路’其中’至少電晶体與定電流源係集設於同一半導體 基板者《 1 3,如申請專利範圍第1、2、3、4、5、6或7項之振Μ電 ϋ張尺度適用中國國家標準(CN S ) Α4規格(210 X 297公寶) 3 310417 448609 H3 路,其中,該壓電振動元件爲水晶振動元件者。 14.如申請專利範圍第〗,2、3* 4、5、6或7項任一項之 振盪電路,其中,該振盪電路係安裝於攜帶用通訊機 者。 經濟部中央標準局員工福利委員會印製 衣紙張尺度適用中圉國家標準(CNS)A4規格(210X297公赞) 4 310417H3 Printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs No. 88HM189 Patent Application Amendment to the Patent Scope (March 1, 1990) 1. An oscillating circuit comprising: a piezoelectric vibration element, an oscillating capacitor and feedback amplification A transistor is characterized in that the oscillation circuit is provided with a constant current source in series with an emitter of the transistor described above. 2. An oscillation circuit consisting of: a piezoelectric vibrating element: the piezoelectric vibrating element is connected to a transistor of its base; it is connected between a power source to supply a bias voltage to the resistor located at the base of the transistor; A first capacitor between the base and the emitter of the transistor; a constant current source provided between the emitter of the transistor and a power terminal on one side; a second capacitor provided in parallel with the constant current source; and The output resistance between the collector of the transistor and the power supply terminal on the other side. 3. An oscillation circuit consisting of: a piezoelectric vibration element: a first transistor connected to the base of the piezoelectric vibration element; a second transistor connected in series with the first transistor; connected between a power source and The bias potential is supplied to the resistance of the base of the first transistor and the base of the second transistor; the first capacitor provided between the base and the emitter of the first transistor; the first capacitor provided between the base and the emitter of the first transistor; A constant current source between the emitter of the crystal and the power supply terminal on one side; a second capacitor connected in parallel with the constant current source; and an output resistance provided between the collector of the second transistor and the power supply terminal on the other side . 4. An oscillating circuit comprising: a piezoelectric vibrating element; the piezoelectric vibrating element is connected to a transistor of its base; connected between a power source and a resistor that supplies a bias potential to the base of the transistor; The base of the above transistor and this paper are in accordance with the Chinese National Standard (CNS) A4 specification (YlO X 297). 1 310417 4 48609 H3 The first capacitor between the emitters printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs : A constant current source provided between the emitter of the transistor and a power supply terminal on one side; and a second capacitor provided in parallel with the constant current source; and the connection point between the emitter of the transistor and the constant current source Output by β 5. An oscillation circuit consisting of: a piezoelectric vibration element: a first transistor connected to the base of the piezoelectric vibration element; a second transistor connected in series with the first transistor; provided in the above A constant current source for bias voltage between the base of the second transistor and one power supply terminal or a constant current source for bias voltage provided between the base of the second transistor and the other power supply terminal; Base of 1 transistor and the above-mentioned second transistor The bias resistor between the base of the first transistor and the base of the first transistor and the other power supply terminal; the first capacitor provided between the base and the emitter of the first transistor: provided in the first transistor A constant current source between the emitter of the crystal and the other power supply terminal; a second capacitor provided in parallel with the constant current source; and an output resistance provided between the collector of the second transistor and the power supply terminal on one side ° 6. An oscillation circuit consisting of: a piezoelectric vibration element; a first transistor connected to the base of the piezoelectric vibration element; a second transistor connected in series with the first transistor; Constant current source for bias voltage between the base of the transistor and the power supply terminal on one side: respectively provided between the base of the first transistor and the base of the second transistor and between the base of the first transistor and the base of the first transistor The bias resistor between the power supply terminal on the other side; the first capacitor provided between the base and the emitter of the first transistor; and the capacitor provided between the emitter and the other power terminal of the first transistor. A current source; a second capacitor connected in parallel with the constant current source; and a collector and a power source provided on the second transistor The size of the original paper is in accordance with China National Standard (CNS) A4 (210X297) 2 310417 448609 Η3 The output resistance of the printing room of the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs is characterized by: And the base of the second transistor are provided with a temperature compensation circuit. 7. If the oscillation circuit of the scope of the patent application No. 6, wherein the temperature compensation circuit is: a diode body connected in series between a bias resistor provided between the base of the first transistor and the power supply terminal on the other side ; Set between the base of the second transistor and the power supply terminal on the other side, and the emitter is connected to the transistor on the other power supply terminal: respectively connected between the base and the emitter of the transistor and the base The resistance between the collector and the resistor connected to the collector of the transistor. 8. For the oscillating circuit with the scope of patent application No. 1, 2, 3, 4, 5, 6, or 7, the current setting resistance of the constant current source of the circuit is constituted by a resistor with negative temperature characteristics. 9. The oscillating circuit according to item 8 of the scope of patent application, wherein the constant current source is: a constant current source for a reference current with a current setting resistor; and a current mirror circuit receiving the reference current of the constant current source for the reference current. Constructor. 10. The oscillation circuit according to item 8 of the scope of patent application, wherein the current setting resistor is formed by a thin film resistor. 11. The oscillating circuit according to item 9 of the patent application scope, wherein the current setting resistor is a thin film resistor. 12. If the oscillating circuit in the scope of patent application No. 丨, 2, 3, 4, 5, 6, or 7 'wherein' is at least the transistor and the constant current source are integrated on the same semiconductor substrate "1 3, if the scope of patent application The vibrating scales of the vibrating plates of items 1, 2, 3, 4, 5, 6, or 7 are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public treasure) 3 310417 448609 H3, where the piezoelectric The vibration element is a crystal vibration element. 14. According to the scope of the patent application, the oscillating circuit of any one of 2, 3 * 4, 5, 6, or 7 wherein the oscillating circuit is installed on a portable communication device. Printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs. Applicable to China National Standard (CNS) A4 (210X297 praise) 4 310417
TW88104189A 1998-09-03 1999-03-18 Oscillation circuit TW448609B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24958098 1998-09-03

Publications (1)

Publication Number Publication Date
TW448609B true TW448609B (en) 2001-08-01

Family

ID=17195130

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88104189A TW448609B (en) 1998-09-03 1999-03-18 Oscillation circuit

Country Status (1)

Country Link
TW (1) TW448609B (en)

Similar Documents

Publication Publication Date Title
US6882835B2 (en) Oscillator and communication apparatus
US6377130B1 (en) Temperature stabilized CMOS oscillator circuit
US6956443B2 (en) Differential oscillator circuit including an electro-mechanical resonator
US6737928B2 (en) Temperature-compensated crystal oscillator
TW448609B (en) Oscillation circuit
JP5034772B2 (en) Temperature compensated piezoelectric oscillator
JP2004320417A (en) Temperature compensated piezoelectric oscillator
JP2001257530A (en) Temperature compensated oscillator, communication equipment and electronic appliance
Jin et al. A 0.8-V low-power low-cost CMOS crystal oscillator with high frequency accuracy
JP4370893B2 (en) Piezoelectric oscillator and manufacturing method
JP3239776B2 (en) Temperature compensated piezoelectric oscillator
JP2002290151A (en) Temperature compensated quartz oscillator with afc
JP2000183648A (en) Piezo-oscillator having frequency correcting function
JPH10270941A (en) Temperature compensated piezoelectric oscillator
JP4314988B2 (en) Temperature compensated piezoelectric oscillator
JPH03126303A (en) Temperature compensation crystal oscillator
JPH0522035A (en) Voltage controlled crystal oscillator and temperature compensated crystal oscillator
WO2006046572A1 (en) Temperature compensation type piezoelectric oscillator
JP3387278B2 (en) Temperature compensated piezoelectric oscillator
JP2000151279A (en) Crystal oscillation circuit
JPH02218231A (en) Radio selective call receiver
JPH04249409A (en) Voltage controlled oscillator
JPH10270942A (en) Temperature compensation crystal oscillator and its adjusting method
JPH07106852A (en) Temperature compensated crystal oscillation circuit
JP2002151957A (en) Piezoelectric oscillator

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees