經濟部智慧財產局員工消費合作杜印製 448566 五、發明說明（/ ) 本發明是有關於一種電容器儲存電極（s to rage node ) 的製造方法，且特別是有關於一種深溝渠（deep trench) 電容儲存電極的製造方法。 動態隨機存取記憶體（DRAM)電容器的結構主要分成兩 種，其一爲堆疊式電容（stack capacitor)，另一則爲溝 渠電容（trench capacitor)，而不論是堆疊式電容或是溝 渠電容，在半導體元件尺寸縮減的要求下，其在製造技術 上均遭遇到越來越多的困難。 對溝渠電容而言，在半導體尺寸爲0.2μηι的製程中， 溝渠的高寬比Uspect ratio)將高達35 : 1，而當設計規 則（des 1 gn 1·u 1 e)往0.18μιη的製程邁進時，溝渠尺寸更需 相對地縮小。於是，如何製造具有大面積的儲存電極以獲 得較大的電容値，則成爲製程上最需要克服的技術。 第1Α-1Ε圖所示，爲習知一種深溝渠電容儲存電極的 製造流程剖面圖。請參照第1Α圖，在一基底100上形成 有墊氧化物層102與硬罩幕層（hard mask)l 04，利用硬罩 幕層104爲罩幕而在基底100上形成一深溝渠106。 接著，請參照第1B圖，在深溝渠106的側壁上形成一 摻雜絕緣層Π2，並在深溝渠106中形成光阻114，其中 光阻1 14不塡滿深溝渠106，且其表面低於基底100的上 表面100a，而摻雜絕緣層112高於光阻114的部分則暴露 出。之後.，將暴露出的摻雜絕緣層112去除，而形成如第 1C圖所示，位於深溝渠106底部，與光阻114同高之摻雜 絕緣層112a。續對基底100與深溝渠106沉積一蓋氧化物 3 ^ Π I 裝· I ----I I ---I I I I ! t 1 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中®國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 448566 5 I 9 l 1 vs i' J c / Ο Ο 6 五、發明說明（> ) 層（cap oxide)，例如爲蓋TEOS氧化物（cap TE0S)，之後 再回鈾刻蓋氧化物層，而在深溝渠106側壁上形成一蓋氧 化物間隙壁丨16，使光阻114暴露出，如第1C圖所示。 之後，請參照第1D圖，在將光阻116剝除後，對基底 100進行一熱製程，使摻雜絕緣層112a中的雜質擴散進入 基底100而形成一摻雜區118，作爲深溝渠電容之儲存電 極。接著，去除深溝渠106底部的摻雜絕緣層112a以及 頂部的蓋氧化物層116，如第1E圖所示。之後，再於儲存 電極上形成一電容介電層120,且於電容介電層120上形 成一上電極（未繪出），則完成深溝渠電容的製作。 當臨限尺寸（critical dimension)逐漸縮小，對深溝 渠106高寬比的要求也將逐漸增加到大於35,然而高寬比 越大，深溝渠106的蝕刻製程將越來越難進行，而深溝渠 106底部的尺寸也會愈來越窄，如第1A圖之深溝渠106底 部107，導致後續形成的儲存電極面積變小，而導致電容 値下降。 有鑑於此，本發明就是在提供一種深溝渠儲存電極的 製造方法，係利用擴大深溝渠底部尺寸，藉以增加儲存電 極的面積而提高深溝渠電容器之電容値。 本發明提供一種深溝渠電容儲存電極的製造方法，適 用在一基底上，係先以一硬罩幕層在基底上定義而形成一 深溝渠，其中基底與硬罩幕層之間具有一墊絕緣層。接 著，在深溝渠中形成一絕緣材料，而絕緣材料並不塡滿深 溝渠，且使深溝渠側壁的頂部表面暴露出，續在深溝渠的 4 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） ------^--I---r 裝·-------訂--------線· 1 (請先M讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 ^48566 Λ 7 5 1 9 i Iwf doc/ΟΟή " ____H7___ 五、發明說明（名） 側壁上形成一硬材料間隙壁。之後，去除絕緣材料，暴露 出深溝渠底部的基底表面，接著在深溝渠中形成一摻雜 層，覆蓋深溝渠底部暴露出的基底表面，再利用一熱處 理，而在溝渠底部的基底形成一摻雜區，而作爲儲存電 極。 本發明再提供一種瓶狀深溝渠電容儲存電極的製造方 法，適用在一基底上，首先在基底上提供一深溝渠，其中 深溝渠係利用一墊氧化物層與一硬罩幕層定義而成。接 著，在深溝渠中形成一絕緣材料，絕緣材料係塡滿深溝渠 至一適當深度，使其表面低於基底之上表面。續在深溝渠 側壁的頂部表面形成一硬材料間隙壁，且暴露出絕緣材料 表面，再進行去除絕緣材料的步驟，使深溝渠底部表面完 全暴露出。之後，氧化深溝渠底部表面而於表面上形成一 氧化物層，再將氧化物層去除後則形成一瓶狀深溝渠，續 在瓶狀深溝渠中形成一摻雜氧化矽層，並使摻雜氧化矽層 中的摻雜擴散進入瓶狀深溝渠的底部，而形成一瓶狀深溝 渠儲存電極。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A-1E圖係顯示一種習知深溝渠儲存電極的製造流 程剖面圖；以及 第2A-2L圖係顯示根據本發明較佳實施例之深溝渠儲 5 本紙張尺度適用中國國家標準（CNS>A4規恪（210 X 297公釐） -------：------ --------訂---------線 (請先間讀背面之注意事項再填寫本頁) 4 006 Λ/ 4 006 Λ/ 經濟部智慧財產局員工消費合作社印製 100、200 :基底 104、202 :硬罩幕層 107 :深溝渠底部 層 114 :光阻 118、216 :摻雜區 層206a、206b :頂部表面 207 :瓶狀深溝渠 210 :硬材料層 220、220a :第一導電層 224、224a :第二導電層 Β7 五、發明說明（y) 存電極之製造流程剖面圖。 其中，各圖標號之簡單說明如下： 102、204 _·墊氧化物層 106、206 :深溝渠 112、112a、214 :摻雜絕緣 116 :蓋氧化物間隙壁 120、218、218a :電容介電 底部表面 208 :絕緣材料 212 :氧化物層 222、222a :領氧化物層 226 :第三導電層 實施例 本發明之較佳實施例係在一深溝渠中塡入適當高度的 絕緣材料，而高於絕緣材料的側壁表面則暴露出，之後， 在暴露出的側壁表面形成一硬材料間隙壁，覆蓋深溝渠頂 部側壁，續再將絕緣材料去除。接著，對深溝渠底部進行 氧化步驟，而在深溝渠底部表面形成一氧化物層，續將氧 化物層去除，而形成一瓶狀深溝渠。接著，再將摻雜氧化 物層形成在瓶狀深溝渠底部，覆蓋暴露出的底部表面，利 用熱處理將摻雜氧化物層中的摻質擴散進入瓶狀深溝渠 底部而形成一摻雜區，作爲一儲存電極。因此，由於作爲 儲存電極的深溝渠面積變大，故可提高電容値。 本紙張尺度適用中國國家標準（CNS)A4規格mo X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --------訂-------— 448 β 經濟部智慧財產局員工消費合作社印製 Λ7 B7 五、發明說明（$ ) 第2A-2L圖所示，爲根據本發明一較佳實施例深溝渠 電容器儲存電極之製造流程剖面圖。請參照第2A圖，在 一基底200上利用微影蝕刻製程定義硬罩幕層202與墊絕 緣層204而形成一深溝渠206。例如在基底200上利用熱 氧化法形成厚度約爲50埃左右的墊氧化物層，接著，在 墊氧化物層上以化學氣相沉積法形成厚度約爲2000埃左 右的氮化矽層或氮化矽/氧化物之組合作爲硬罩幕（h a r d mask)，隨後，再於硬罩幕層202上形成光阻（未繪出）， 定義硬罩幕層202與墊絕緣層204，而形成深溝渠206。 接著，在深溝渠中206形成一絕緣層，塡滿深溝渠206 並延伸至硬罩幕層202上而覆蓋硬罩幕層202，續回蝕刻 絕緣層，將硬罩幕層202上以及深溝渠206頂部的絕緣層 去除，而形成如第2B圖所示，在深溝渠206中塡入一適 當深度d之絕緣材料208。其中，絕緣材料208之表面208a 需低於基底200之一上表面200a，且暴露出深溝渠206頂 部，高於絕緣材料208的側壁206a。而絕緣材料2⑽塡入 的適當深度d係爲後續儲存電極形成的預定高度，其不得 超過後續儲存電極形成的預定高度。絕緣材料208的回蝕 刻可以濕蝕刻法或乾飩刻法進行，在蝕刻時需調整蝕刻劑 對硬罩幕層202與絕緣材料208的蝕刻選擇比（etch selectivity)，使絕緣材料208可以順利蝕刻，而硬罩幕 層202可以保護基底200不受回蝕刻製程的損害。絕緣層 例如以化學氣相沉積法形成的氧化物，沉積的厚度約爲 2000埃左右，而絕緣材料208的高度約低於基底200上表 7 本紙張尺度適用中國S家標準（CNS>A4規格（210 x 297公爱） ---1— I ϊ -I I---'.裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 448566 19 1 iwt. ii〇c/006 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（6) 面200a 13000埃左右的位置。 請參照第2C圖，接著，：^邀)盖？巨+ ®有任彳木溝渠2〇6頂部的側壁206a 上形成-硬材料間隙壁21〇，暴露出絕緣材料表面 緣。硬材料間關2i0的形成例如在基底咖上形成一 共形（C〇nf〇rmal)硬材料層，其係沿基底200表面的輪廓 起獅形成，覆蓋硬罩幕if 202，且沿深溝渠2〇6側壁鳩 並覆蓋絕緣材料裏而形成，接著，再對共形硬材料層進 行回鈾刻’例如以非等向性（anis〇tr〇pic)触刻進行，則 將在硬罩幕層2Q2與絕緣材料施水平面上的硬材料層去 除，而留下深溝渠206側壁的硬材料間隙壁21〇 ,其中硬 材料間隨2關回酬例如以絕緣材料2〇8爲㈣終點 而進行，故共形硬材料層需選擇與絕緣材料2〇8具有較大 時刻;®擇比的材料。共形硬材料層例如以化 沉積厚度約爲2⑻埃左右_化歸。化^相麗 之後，nra參照桌2D圖，將絕緣材料2〇8去除，使深溝 渠206側壁的底部表面206b暴露出，亦即暴露出基底2〇〇 的矽基材，去除絕緣材料208例如以濕蝕刻法進行，以將 涂溝渠206底部的絕緣材料208完全去除。接著，對基底 200進fj 一熱處理，例如利用爐管或快速熱製程（rtp )在氧 氣存在的環境下進行，氧氣在高溫下與深溝渠2〇6中暴露 出的矽基材反應’將暴露出的基底2〇〇表面2〇61)氧化成 一氧化物層212，如第2D圖所示，而在氧化的步驟中，深 溝渠206頂部的側壁206a由於有硬材料間隙壁210的覆 蓋，故頂部側壁206a並不會進行氧化反應。其中，氧化 8 本紙張疋度適用中國國家標準（CNS)A4^格<210x297公g ' --- I . 1--I ^---- ---- --------訂·--------, (請先閱讀背面之注意事項再填寫本頁) 448566 0 6 Λ7 H7 經濟部智慧財產局員工消費合作社印製 •5*、發明說明（/y ) 物層21 2形成的厚度視實際需要而決定，由於氧化反應會 消耗掉暴露出的矽材’使得矽材200-氧化物212的界面將 會往基底200的方向移動，大致上而言’生成1〇〇〇埃左 右的氧化物層212，矽材200-氧化物212的界面會往基底 200的方向移動500埃左右。 由於，上述的氧化反應消耗掉溝渠206底部表面206b 的矽材，故當去除氧化步驟形成的氧化物層212，例如以 濕蝕刻進行，則可形成如第2E圖所示之瓶狀深溝渠207。 在將氧化物層212去除後，暴露出瓶狀深溝渠207底部的 基底200表面206b’，而由於瓶狀深溝渠207頂部側壁206a 以及基底200上表面200a分別具有硬材料間隙壁210以 及硬罩幕層202覆蓋，故去除氧化物層212時並不會損害 到基底200的其他部分。 請參照第2F圖，接著，在基底200上形成一摻雜層 214，例如以臨場（in-situ)摻雜離子的方式，以化學氣相 沉積法形成一摻雜氧化矽層，覆蓋瓶狀深溝渠207的底部 表面206b’，硬材料間隙壁210，並延伸至硬罩幕層202 上，其中摻雜層214中的摻質例如爲砷離子。之後，對基 底200進行一熱製程，使摻雜層214中的摻質獷散進入瓶 狀深溝渠207底部暴露出的基底200表面2U6b，，而在深 溝渠207底部形成一摻雜區216’如第2G圖所示，其中摻 雜區2丨6係作爲深溝渠電容器之一'儲存電極。此外，由於 瓶狀深溝渠207頂部形成有硬材料間隙壁21 〇，故可阻檔 住摻雜層214中摻質的擴散’使摻雜區2丨6不致擴散過 9 I I I- I I ΙΊ I I I I , — — — — — — I— ^ —— — ———I— I <請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） \7 448566Consumption Cooperation by Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 448566 V. Description of the Invention (/) The present invention relates to a method for manufacturing a capacitor storage electrode (s to rage node), and in particular, to a deep trench Manufacturing method of capacitor storage electrode. The structure of dynamic random access memory (DRAM) capacitors is mainly divided into two types, one is a stack capacitor, and the other is a trench capacitor, regardless of whether it is a stacked capacitor or a trench capacitor. Under the requirement of reducing the size of semiconductor elements, they are encountering more and more difficulties in manufacturing technology. For trench capacitors, the trench aspect ratio (Uspect ratio) will be as high as 35: 1 in a process with a semiconductor size of 0.2 μηι, and when the design rule (des 1 gn 1 · u 1 e) moves towards the 0.18 μιη process At the same time, the trench size needs to be relatively reduced. Therefore, how to manufacture a storage electrode with a large area to obtain a larger capacitance 値 has become the most overcoming technology in the manufacturing process. Figures 1A-1E are sectional views of the manufacturing process of a conventional deep trench capacitor storage electrode. Referring to FIG. 1A, a pad oxide layer 102 and a hard mask 104 are formed on a substrate 100, and a deep trench 106 is formed on the substrate 100 by using the hard mask layer 104 as a mask. Next, referring to FIG. 1B, a doped insulating layer Π2 is formed on the side wall of the deep trench 106, and a photoresist 114 is formed in the deep trench 106. The photoresist 1 14 does not fill the deep trench 106 and its surface is low. On the upper surface 100 a of the substrate 100, a portion of the doped insulating layer 112 higher than the photoresist 114 is exposed. After that, the exposed doped insulating layer 112 is removed to form a doped insulating layer 112a located at the bottom of the deep trench 106 as high as the photoresist 114, as shown in FIG. 1C. Continue to deposit a cap oxide 3 on the substrate 100 and the deep trench 106. ^ Π I · I ---- II --- IIII! T 1 (Please read the precautions on the back before filling this page) The paper size is applicable ® National Standard (CNS) A4 Specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 448566 5 I 9 l 1 vs i 'J c / 〇 Ο 6 V. Description of the Invention (>) Layer ( cap oxide), for example, cap TEOS oxide (cap TEOS), and then return to uranium to etch the cap oxide layer, and form a cap oxide spacer on the side wall of the deep trench 106 to expose the photoresist 114, such as Shown in Figure 1C. Then, referring to FIG. 1D, after the photoresist 116 is stripped, a thermal process is performed on the substrate 100 to diffuse the impurities in the doped insulating layer 112a into the substrate 100 to form a doped region 118 as a deep trench capacitor. Its storage electrode. Next, the doped insulating layer 112a at the bottom of the deep trench 106 and the cap oxide layer 116 at the top are removed, as shown in FIG. 1E. After that, a capacitor dielectric layer 120 is formed on the storage electrode, and an upper electrode (not shown) is formed on the capacitor dielectric layer 120 to complete the production of the deep trench capacitor. As the critical dimension gradually decreases, the requirements for the aspect ratio of the deep trench 106 will also gradually increase to greater than 35. However, the larger the aspect ratio, the deeper trench 106's etching process will become more and more difficult, and the deeper The size of the bottom of the trench 106 will also become narrower and narrower, such as the bottom 107 of the deep trench 106 in FIG. 1A, which will cause the area of the storage electrodes to be subsequently formed to become smaller, which will cause the capacitance to decrease. In view of this, the present invention is to provide a method for manufacturing a deep trench storage electrode by increasing the size of the bottom of the deep trench to increase the area of the storage electrode to increase the capacitance of the deep trench capacitor. The invention provides a method for manufacturing a deep trench capacitor storage electrode, which is applicable to a substrate. A deep trench is first defined on the substrate by a hard cover layer, and a pad insulation is provided between the substrate and the hard cover layer. Floor. Next, an insulating material is formed in the deep trench, and the insulating material does not fill the deep trench, and the top surface of the side wall of the deep trench is exposed. The 4 paper standards in the deep trench are applicable to the Chinese National Standard (CNS > A4 specification). (210 X 297 mm) ------ ^-I --- r equipment · ------- order -------- line · 1 (please read the note on the back first Please fill out this page again) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 48566 Λ 7 5 1 9 i Iwf doc / 〇〇ή " ____H7___ V. Description of the invention (name) A hard material gap is formed on the side wall. After that, remove The insulating material exposes the substrate surface at the bottom of the deep trench, and a doped layer is formed in the deep trench to cover the exposed surface of the substrate at the bottom of the deep trench. A heat treatment is then used to form a doped region on the substrate at the bottom of the trench. As a storage electrode, the present invention further provides a method for manufacturing a bottle-shaped deep trench capacitor storage electrode, which is applicable to a substrate. First, a deep trench is provided on the substrate, wherein the deep trench uses a pad oxide layer and a hard cover. The curtain layer is defined. Then, in the deep trench An insulating material is formed in the trench, and the insulating material fills the deep trench to an appropriate depth so that its surface is lower than the upper surface of the substrate. A hard material gap is formed on the top surface of the side wall of the deep trench, and the surface of the insulating material is exposed. Then, the step of removing the insulating material is completely exposed, so that the bottom surface of the deep trench is completely exposed. Then, the bottom surface of the deep trench is oxidized to form an oxide layer on the surface, and the oxide layer is removed to form a bottle-shaped deep trench. A doped silicon oxide layer is continuously formed in the bottle-shaped deep trench, and the dopant in the doped silicon oxide layer is diffused into the bottom of the bottle-shaped deep trench, so as to form a bottle-shaped deep trench storage electrode. The above and other objects, features, and advantages can be more clearly understood. A preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings: Figures 1A-1E show a kind of A cross-sectional view of the manufacturing process of a conventional deep trench storage electrode; and FIGS. 2A-2L show a deep trench storage according to a preferred embodiment of the present invention. CNS > A4 (210 X 297 mm) -------: -------- -------- Order --------- line (please read first Note on the back, please fill in this page again) 4 006 Λ / 4 006 Λ / Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 100, 200: substrate 104, 202: hard cover curtain layer 107: deep trench bottom layer 114: photoresist 118, 216: doped region layers 206a, 206b: top surface 207: bottle-shaped deep trench 210: hard material layer 220, 220a: first conductive layer 224, 224a: second conductive layer B7 5. Description of the invention (y) Cross-sectional view of the manufacturing process of the electrode. Among them, a brief description of each icon number is as follows: 102, 204 _ · pad oxide layers 106, 206: deep trenches 112, 112a, 214: doped insulation 116: cover oxide spacers 120, 218, 218a: capacitor dielectric Bottom surface 208: insulating material 212: oxide layers 222, 222a: collar oxide layer 226: third conductive layer Embodiment A preferred embodiment of the present invention is to insulate an appropriate height of insulating material in a deep trench, and The surface of the side wall of the insulating material is exposed. After that, a hard material gap is formed on the exposed side wall surface to cover the top side wall of the deep trench, and then the insulating material is removed. Next, an oxidation step is performed on the bottom of the deep trench, and an oxide layer is formed on the bottom surface of the deep trench. The oxide layer is continuously removed to form a bottle-shaped deep trench. Next, a doped oxide layer is formed on the bottom of the bottle-shaped deep trench, covering the exposed bottom surface, and the dopant in the doped oxide layer is diffused into the bottom of the bottle-shaped deep trench by heat treatment to form a doped region. As a storage electrode. Therefore, since the area of the deep trench as the storage electrode becomes large, the capacitance 値 can be increased. This paper size applies to Chinese National Standard (CNS) A4 specification mo X 297 mm) (Please read the precautions on the back before filling this page) -------- Order --------- 448 β Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ7 B7 V. Description of the Invention ($) Figures 2A-2L are cross-sectional views of the manufacturing process of a deep trench capacitor storage electrode according to a preferred embodiment of the present invention. Referring to FIG. 2A, a hard mask layer 202 and a pad insulation layer 204 are defined on a substrate 200 by a lithographic etching process to form a deep trench 206. For example, a pad oxide layer having a thickness of about 50 angstroms is formed on the substrate 200 by a thermal oxidation method, and then a silicon nitride layer or nitrogen having a thickness of about 2000 angstroms is formed on the pad oxide layer by a chemical vapor deposition method. The silicon / oxide combination is used as a hard mask. Then, a photoresist (not shown) is formed on the hard mask layer 202, and the hard mask layer 202 and the pad insulation layer 204 are defined to form a deep mask. Ditch 206. Next, an insulating layer is formed in the deep trench 206, which fills the deep trench 206 and extends to the hard mask layer 202 to cover the hard mask layer 202, and then continues to etch the insulating layer to place the hard mask layer 202 on the deep trench and the deep trench. The insulating layer on the top of 206 is removed, and as shown in FIG. 2B, an insulating material 208 of a proper depth d is inserted into the deep trench 206. The surface 208a of the insulating material 208 needs to be lower than one of the upper surfaces 200a of the substrate 200, and the top of the deep trench 206 is exposed, which is higher than the sidewall 206a of the insulating material 208. The proper depth d of the insulating material 2 is a predetermined height formed by the subsequent storage electrode, which must not exceed the predetermined height formed by the subsequent storage electrode. The etch back of the insulating material 208 can be performed by wet etching or dry etching. During the etching, the etch selectivity of the hard mask layer 202 and the insulating material 208 by the etchant needs to be adjusted so that the insulating material 208 can be etched smoothly. The hard mask layer 202 can protect the substrate 200 from being damaged by the etch-back process. The insulating layer is, for example, an oxide formed by a chemical vapor deposition method. The thickness of the insulating layer is about 2000 Angstroms, and the height of the insulating material 208 is lower than that of the substrate 200. Table 7 This paper size is applicable to China S Standards (CNS > A4 specifications (210 x 297 public love) --- 1— I ϊ -I I --- '. Install -------- order --------- line (Please read the precautions on the back first (Fill in this page again) 448566 19 1 iwt. Ii〇c / 006 Printed B7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (6) 200a 13000 angstroms. Please refer to Figure 2C, then: ^ Invite) cover? Giant + ® has a hard material spacer 21 formed on the side wall 206a at the top of any 彳 mu trench 206, exposing the surface edge of the insulating material. The formation of the hard material barrier 2i0, for example, forms a conformal (hard-layered) hard material layer on the base coffee, which is formed along the contour of the surface of the base 200 to lion, covering the hard curtain if 202, and along the deep trench 2 〇6 sidewall dove is formed by covering the insulating material, and then, the conformal hard material layer is etched back to the uranium. For example, the anisotropic (anistropic) touch engraving is performed on the hard cover curtain layer. The hard material layer on the horizontal plane between 2Q2 and the insulating material is removed, leaving a hard material gap 21o on the side wall of the deep trench 206. The hard material is performed with the return of the second pass, for example, using the insulating material 208 as the end point. Therefore, the conformal hard material layer needs to choose a material that has a larger moment than the insulating material 208; The conformal hard material layer is reduced to a thickness of about 2 Angstroms, for example. After the photo is made, nra refers to the 2D drawing of the table, and removes the insulating material 208, so that the bottom surface 206b of the side wall of the deep trench 206 is exposed, that is, the silicon substrate of the substrate 200 is exposed. The wet etching method is performed to completely remove the insulating material 208 at the bottom of the coating trench 206. Next, the substrate 200 is subjected to a fj heat treatment, for example, using a furnace tube or a rapid thermal process (rtp) in the presence of oxygen. The oxygen reacts with the silicon substrate exposed in the deep trench 206 at a high temperature. The surface of the substrate 200 (the surface 206) is oxidized into an oxide layer 212, as shown in FIG. 2D. In the oxidation step, the side wall 206a on the top of the deep trench 206 is covered by the hard material spacer 210, so The top sidewall 206a does not undergo an oxidation reaction. Among them, the degree of oxidation of 8 papers conforms to the Chinese National Standard (CNS) A4 ^ grid < 210x297g g '--- I. 1--I ^ ---- ---- -------- Order · --------, (Please read the notes on the back before filling out this page) 448566 0 6 Λ7 H7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs • 5 *, invention description (/ y) The thickness of the layer 21 2 is determined according to actual needs. The exposed silicon material will be consumed by the oxidation reaction, so that the interface of the silicon material 200 to the oxide 212 will move toward the substrate 200. Generally speaking, the generation 1 For the oxide layer 212 of about 00 angstroms, the interface between the silicon material 200 and the oxide 212 moves about 500 angstroms toward the substrate 200. Since the above-mentioned oxidation reaction consumes the silicon material on the bottom surface 206b of the trench 206, when the oxide layer 212 formed in the oxidation step is removed, for example, by wet etching, a bottle-shaped deep trench 207 as shown in FIG. 2E can be formed. . After the oxide layer 212 is removed, the surface 206b 'of the substrate 200 at the bottom of the bottle-shaped deep trench 207 is exposed, and the top side wall 206a of the bottle-shaped deep trench 207 and the upper surface 200a of the substrate 200 have hard material barriers 210 and hard covers, respectively. The curtain layer 202 is covered, so the other parts of the substrate 200 are not damaged when the oxide layer 212 is removed. Please refer to FIG. 2F. Next, a doped layer 214 is formed on the substrate 200. For example, a doped silicon oxide layer is formed by in-situ doping ions by chemical vapor deposition to cover the bottle shape. The bottom surface 206b 'of the deep trench 207, the hard material partition wall 210, and extends onto the hard mask layer 202, wherein the dopant in the doping layer 214 is, for example, arsenic ions. Thereafter, a thermal process is performed on the substrate 200 to allow the dopants in the doped layer 214 to disperse into the surface 2U6b of the substrate 200 exposed at the bottom of the bottle-shaped deep trench 207, and a doped region 216 'is formed at the bottom of the deep trench 207. As shown in FIG. 2G, the doped regions 2 and 6 serve as one of the deep trench capacitors' storage electrodes. In addition, since a hard material spacer 21 is formed on the top of the bottle-shaped deep trench 207, the diffusion of the dopant in the doped layer 214 can be blocked, so that the doped region 2 丨 6 will not diffuse through 9 II I- II ΙΊ IIII , — — — — — — — I— ^ —— — ——— I— I < Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297) Centimeters) \ 7 448566
> 19uwi-.tu)t；/a〇6 ^ J ___B7__ 五、發明說明（S' ) 大，而可限制在包圍住瓶狀深溝渠207的範圍內。 利用上述步驟形成瓶狀深溝渠207,使儲存電極216 儲存電荷的面積可增加約爲50%-100%的比例’因此在儲 存電荷面積大幅增加之下，儲存電容量亦成正比而增加， 故可提高電容値。 接著，在完成儲存電極216後，進行去除摻雜層214 與硬材料間隙壁210的步驟，摻雜層214例如以 BHF(buffer HF)或DHF(dUuted HF)的濕蝕刻法去除，暴 露出瓶狀深溝渠207的側壁，如第2G圖所示。續在儲存 電極216上形成一電容介電層與一下電極，而完成深溝渠 電容器之結構，其中，電容介電層與下電極之製程如第 2H-2L圖所示。 請參照第2H圖，接著，在瓶狀深溝渠207與基底200 上形成一電容介電層218，例如爲氮化物/氧化物，續在電 容介電層218上形成一第一導電層220，第一導電層220 例如爲複晶矽層，塡滿瓶狀深溝渠207且延伸至硬罩幕層 202上。接著，去除硬罩幕層202上與瓶狀深溝渠中部分 的第一導電層220與電容介電層218，使第一導電層220 至少塡滿到儲存電極216的高度。例如先回蝕刻第一導電 層220,而回蝕刻的步驟可先利用化學機械硏磨法將硬罩 幕層202上的第一導電層220去除，再對瓶狀深溝渠207 中的第一導電層220進行濕蝕刻或乾蝕刻，而蝕刻第一導 電層220時需調整蝕刻選擇比，使蝕刻進行時不致破壞硬 罩幕層202,之後再將未被第一導電層220a暴露出的電容 {請先閱讀背面之注意事項再填寫本頁) "芦裝--------訂·-------I - 經濟部智慧財產局員工消費合作社印數 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） 4 48 56 6 5 f.doc/006 Al _B7______ 五、發明說明（/ϋ ) 220a可藉此作爲深溝渠電容器之一上電極，其中領氧化物 層222a係防止儲存電極216與上電極經由基底200深溝 渠頂部表面206a直接導通而造成短路= 本發明之較佳實施例係利用形成一瓶狀深溝渠作爲一 儲存電極，而利用較爲擴大的深溝渠底部面積增加儲存電 極的面積，使深溝渠電容器具有較大的電容値，故得以因 應操作上的需求。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ---,t.--III------裝--------訂---------' (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印56； 本紙張尺度適用中國國家標準（CNS)A·!規格（210 X 297公釐〉> 19uwi-.tu) t; / a〇6 ^ J ___B7__ 5. The description of the invention (S ') is large, but can be limited to the range surrounding the bottle-shaped deep trench 207. Using the above steps to form a bottle-shaped deep trench 207, the area where the storage electrode 216 can store charge can be increased by a ratio of about 50% to 100%. Therefore, under the substantial increase in the area of stored charge, the storage capacitance also increases in proportion to Capacitance can be increased. Next, after the storage electrode 216 is completed, a step of removing the doped layer 214 and the hard material spacer 210 is performed. The doped layer 214 is removed by, for example, wet etching of BHF (buffer HF) or DHF (dUuted HF) to expose the bottle. The side wall of the deep trench 207 is shown in FIG. 2G. A capacitor dielectric layer and a lower electrode are continuously formed on the storage electrode 216 to complete the structure of the deep trench capacitor. The process of the capacitor dielectric layer and the lower electrode is shown in Figures 2H-2L. Referring to FIG. 2H, a capacitor dielectric layer 218, such as a nitride / oxide, is formed on the bottle-shaped deep trench 207 and the substrate 200, and a first conductive layer 220 is formed on the capacitor dielectric layer 218. The first conductive layer 220 is, for example, a polycrystalline silicon layer. The first conductive layer 220 is filled with a bottle-shaped deep trench 207 and extends to the hard mask layer 202. Next, the first conductive layer 220 and the capacitor dielectric layer 218 on the hard mask layer 202 and in the middle of the bottle-shaped deep trench are removed, so that the first conductive layer 220 is at least full to the height of the storage electrode 216. For example, the first conductive layer 220 is etched back first, and the etch back step may first remove the first conductive layer 220 on the hard cover curtain layer 202 by using a chemical mechanical honing method, and then conduct the first conductive layer 220 in the bottle-shaped deep trench 207 The layer 220 is wet-etched or dry-etched, and the etching selection ratio needs to be adjusted when the first conductive layer 220 is etched, so that the hard mask layer 202 is not damaged during the etching, and then the capacitor not exposed by the first conductive layer 220a is { (Please read the precautions on the back before filling out this page) " Lu Zhuang -------- Order · ------- I-Printed paper size for employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, China Paper size applies to China National standard (CNS > A4 specification (210 X 297 mm) 4 48 56 6 5 f.doc / 006 Al _B7______ V. Description of the invention (/ ϋ) 220a can be used as one of the upper electrodes of deep trench capacitors, which leads to oxidation The physical layer 222a prevents the storage electrode 216 and the upper electrode from being electrically connected via the top surface 206a of the deep trench of the substrate 200 to cause a short circuit. The preferred embodiment of the present invention uses the formation of a bottle-shaped deep trench as a storage electrode, and the utilization is expanded. Increased storage area at the bottom of deep trenches The area of the deep trench capacitor has a large capacitance, so it can meet the needs of operation. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art, Various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. ---, t .-- III- ----- Equipment -------- Order --------- '(Please read the precautions on the back before filling out this page) Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economics, printed 56; this Paper size applies to China National Standard (CNS) A ·! Specifications (210 X 297 mm>