447126 A7 6704twf.doc/008 β? 五、發明說明（I) 本發明是有關一種製造半導體元件的方法，特別是有 關於一種製造絕緣層上有矽（Silicon On Insulator，SOI) (請先閱讀背面之注意事項再填寫本頁) 半導體元件的方法。 第1A圖是習知一種SOI半導體元件的剖面圖。 一埋入氧化層25形成於一半導體基底24上。P型與 N型重摻雜多晶矽層23a與23b形成於埋入氧化層25上， 且利用形成於埋入氧化層25上之隔離氧化層26來作隔 離。接著，形成個別分開的埋入氧化層22a於P型與N型 重摻雜多晶矽層23a與23b中。 一 P型半導體層20b與一第一主動區形成於第一埋入 氧化層22a上，且個別以P型重摻雜多晶矽層23a作爲分 隔。第一氧化層21形成於P型半導體層2〇b與第一主動 區之間。 一 N型半導體層20c與一第二主動區形成於第一埋入 氧化層22a上，且個別以N型重摻雜多晶矽層23b作爲分 隔。第一氧化層21形成於N型半導體層20c與第二主動 區之間。 經濟部智慧財產局員工消費合作社印製 一閘氧化層29與一第一閘極電極30a相繼形成於P型 重摻雜多晶矽層23a上的第一主動區上。源/汲極區34a/34b 形成於第一閘極電極30a的兩側之第一主動區內。 另一閘氧化層29與第二閘極電極30b相繼形成於N 型重摻雜多晶矽層23b上的第二主動區上。源/汲極區 32a/32b形成於第二閘極電極30b的兩側之第二主動區內。 形成一含有接觸洞之內層絕緣層35於P型與N型半導體 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 447126 A7 6704twf.doc/008 所 五、發明說明（η/) 層20b，20c以及源/汲極區32a/32b，34a/34b上。接觸墊 36a，36f與線形層36b，36c，36d，36e均形成於接觸洞 中且形成於鄰接接觸洞的內層絕緣層上。 第一與第二主動區穿過P型與N型重摻雜多晶矽層23a 與23b分別與P型以及N型半導體層20b，20c相連結。 第1B圖至第1H圖是習知一種製造第1A圖之SOI元 件的流程剖面圖。首先請參照第1B圖，提供一第一半導 體基底20。蝕刻第一基底20以形成複數個溝渠。一氧化 層沉積於基底20與溝渠上。隨後，執行一化學機械硏磨 製程以形成一塡滿溝渠之第一氧化層21。 接著，利用化學氣相沉積法形成一第一埋入氧化層22 於第一半導體基底20上。 形成一光阻層於第一埋入氧化層22上，並且定義出第 一埋入氧化層22上的曝光區域。使用已曝光之光阻層作 爲罩幕，將第一埋入氧化層22去除以暴露出第一基底20。 然後沉積一未摻雜的多晶矽層於第一埋入氧化層22與第 一基底20上。對未摻雜的多晶矽層進行回蝕以形成一未 摻雜的厚多晶矽層23。 提供一第二半導體基底24,且沉積一第二埋入氧化層 25於第二基底24上。接著，利用一高溫製程將第二基底 24上的第二埋入氧化層25與第一基底20上之未摻雜的多 晶矽層23相互結合。 請參照第1C圖。以第一氧化層21爲蝕刻終止層，將 第一基底20硏磨至第一氧化層21。在第一氧化層21，第 4 <請先閱讀背面之生意事項再填寫本頁) 一裝---Jl·!·訂—-- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 447 1 2 6 A7 6704twf.doc/008 五、發明說明（> ) —埋入氧化層22與未摻雜的多晶矽層23之間的半導體層 20a被鈾刻以形成溝渠隔離區。一氧化層沉積於第一氧化 層21、半導體層20a與溝渠隔離區上，然後平坦化此氧化 層以形成一隔離氧化層26。 接著，以一光阻層27覆蓋於第一氧化層21、半導體 層20a與隔離氧化層26上。定義此光阻層27且去除之以 暴露出部分的隔離氧化層26。使用已定義之光阻層27作 爲罩幕，對未摻雜的多晶矽層23植入硼離子以產生一 P 型重摻雜多晶政層23a。 請參照第1D圖。接著，以另一光阻層28覆蓋於第一 氧化層21、半導體層20a與隔離氧化層26上，且定義此 光阻層28。去除光阻層28以暴露出於前步驟被光阻層27 所覆蓋之部分隔離氧化層。使用已定義之光阻層28作爲 罩幕，對未摻雜的多晶矽層23植入磷離子以產生一 N型 重摻雜多晶矽層23b。 請參照第1E圖。沉積一氧化層與一矽層並蝕刻。結 果在半導體層20a上形成一閘氧化層29和一第一閘極電 極30a作爲NMOS電晶體，以及一閘氧化層29和一第二 閘極電極30b作爲PMOS電晶體。 請參照第1F圖。形成一光阻層31並定義之以暴露出 第二閘極電極30b兩側之半導體層20a，且第一閘極電極 30a沒有被暴露出來。使用已定義之光阻層31作爲罩幕， 對P型半導體層20b植入P型硼離子以形成淺摻雜源/汲 極區 32a，32b。 5 ----------裝 -------J 訂·--------· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） 447126 A7 B7 6704twf.doc/008 五、發明說明（屮） <請先閲讀背面之注意事項再填寫本頁) 請參照第1G圖。形成一光阻層33並定義之以暴露出 第一閘極電極30a兩側之半導體層20a，且第二閘極電極 30b沒有被暴露出來。使用已定義之光阻層33作爲罩幕， 對N型半導體層20c植入N型砷離子以形成淺摻雜源/汲 極區 34a，34b。 請參照第1H圖。沉積並去除一絕緣層35以暴露出P 型半導體層20b、N型半導體層20c、P型源/汲極區32a， 32b，與N型源/汲極區34a，34b以及形成接觸洞。形成 一傳導層以塡滿該些接觸洞。然後蝕刻此傳導層以形成P 型與N型半導體層20b，20c上的接觸墊36a，36f以及P 型與N型源/汲極區32a/32b與34a/34b上的線形層36b， 36c » 36d » 36e ° 上述之習知製造SOI半導體元件的方法包括植入P型 離子以形成區域20b，32a，32b。此外，習知方法需要植 入N型離子以形成區域20c，34a，34b。因爲光阻層被用 以作爲離子植入之罩幕，所以需要經過兩次微影製程與兩 次離子植入步驟，因此增加製程之複雜性及其成本。 經濟部智慧財產局員工消費合作社印製 本發明提供一種製造絕緣層上有矽（SOI)半導體元 件的方法，此方法可以克服習知SOI元件的缺點。 蝕刻一第一半導體基底以形成複數個溝渠。一氧化層 沉積於基底與溝渠上。沉積一塡滿溝渠之第一氧化層。形 成一第一埋入氧化層於第一半導體基底上。形成一光阻層 於第一埋入氧化層上且定義之，以暴露出第一埋入氧化 層。使用已曝光之光阻層作爲罩幕，將第一埋入氧化層去 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 447 12 6 6704twf.doc/008 五、發明說明) 除以暴露出第一基底。然後沉積一未摻雜的多晶矽層於第 一埋入氧化層與第一基底上。然後對未摻雜的多晶矽層進 行回蝕。 沉積一第二埋入氧化層於一第二基底上。接著，利用 一高溫製程將第二基底上的第二埋入氧化層與第一基底上 之未慘雜的多晶砂層相互結合。 以第一氧化層爲触刻終止層，將第一基底硏磨至暴露 出第一氧化層。在第一氧化層，第一埋入氧化層與未摻雜 的多晶矽層之間的半導體層被蝕刻以形成溝渠隔離區。一 氧化層沉積於第一氧化層、半導體層與溝渠隔離區上，然 後平坦化此氧化層以形成一隔離氧化層。 接著，以一光阻層覆蓋於第一氧化層、半導體層與隔 離氧化層上。定義此光阻層且去除之以暴露出部分的隔離 氧化層。使用已定義之光阻層作爲罩幕，對未摻雜的多晶 矽層植入，例如是，硼離子以產生一 P型重摻雜多晶矽 層。 然後，以另一光阻層覆蓋於第一氧化層、半導體層與 隔離氧化層上，且定義此光阻層。然後去除光阻層以暴露 出於前步驟被光阻層所覆蓋之部分隔離氧化層β使用已定 義之光阻層作爲罩幕，對未摻雜的多晶矽層植入，例如是， 磷離子以成爲一Ν型重摻雜多晶矽層。 沉積一氧化層與一矽層並蝕刻之。結果在半導體層上 形成一閘氧化層和一第一閘極電極作爲NMOS電晶體，以 及一閘氧化層和一第二閘極電極作爲PMOS電晶體。形成 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝-----^! —訂·！ AUT. 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 47 彳 2 6 A7447126 A7 6704twf.doc / 008 β? 5. Description of the Invention (I) The present invention relates to a method for manufacturing semiconductor components, and in particular, to a method for manufacturing silicon on insulator (SOI) (please read the back first) (Notes on this page, please fill out this page). FIG. 1A is a cross-sectional view of a conventional SOI semiconductor device. A buried oxide layer 25 is formed on a semiconductor substrate 24. P-type and N-type heavily doped polycrystalline silicon layers 23a and 23b are formed on the buried oxide layer 25, and an isolation oxide layer 26 formed on the buried oxide layer 25 is used for isolation. Next, separate buried oxide layers 22a are formed in the P-type and N-type heavily doped polycrystalline silicon layers 23a and 23b. A P-type semiconductor layer 20b and a first active region are formed on the first buried oxide layer 22a, and each is separated by a P-type heavily doped polycrystalline silicon layer 23a. The first oxide layer 21 is formed between the P-type semiconductor layer 20b and the first active region. An N-type semiconductor layer 20c and a second active region are formed on the first buried oxide layer 22a, and each is separated by an N-type heavily doped polycrystalline silicon layer 23b. The first oxide layer 21 is formed between the N-type semiconductor layer 20c and the second active region. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a gate oxide layer 29 and a first gate electrode 30a are successively formed on the first active region on the P-type heavily doped polycrystalline silicon layer 23a. The source / drain regions 34a / 34b are formed in a first active region on both sides of the first gate electrode 30a. Another gate oxide layer 29 and a second gate electrode 30b are sequentially formed on the second active region on the N-type heavily doped polycrystalline silicon layer 23b. The source / drain regions 32a / 32b are formed in the second active region on both sides of the second gate electrode 30b. Form an inner insulating layer containing contact holes 35 on P-type and N-type semiconductors 3 This paper is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 447126 A7 6704twf.doc / 008 (Η /) layers 20b, 20c and source / drain regions 32a / 32b, 34a / 34b. The contact pads 36a, 36f and the linear layers 36b, 36c, 36d, 36e are all formed in the contact hole and formed on the inner insulating layer adjacent to the contact hole. The first and second active regions pass through the P-type and N-type heavily doped polycrystalline silicon layers 23a and 23b and are respectively connected to the P-type and N-type semiconductor layers 20b and 20c. Figures 1B to 1H are cross-sectional views of a conventional process for manufacturing the SOI element of Figure 1A. First, referring to FIG. 1B, a first semiconductor substrate 20 is provided. The first substrate 20 is etched to form a plurality of trenches. An oxide layer is deposited on the substrate 20 and the trench. Subsequently, a chemical mechanical honing process is performed to form a trench-filled first oxide layer 21. Next, a first buried oxide layer 22 is formed on the first semiconductor substrate 20 by a chemical vapor deposition method. A photoresist layer is formed on the first buried oxide layer 22, and an exposed area on the first buried oxide layer 22 is defined. Using the exposed photoresist layer as a mask, the first buried oxide layer 22 is removed to expose the first substrate 20. An undoped polycrystalline silicon layer is then deposited on the first buried oxide layer 22 and the first substrate 20. The undoped polycrystalline silicon layer is etched back to form an undoped thick polycrystalline silicon layer 23. A second semiconductor substrate 24 is provided, and a second buried oxide layer 25 is deposited on the second substrate 24. Next, the second buried oxide layer 25 on the second substrate 24 and the undoped polycrystalline silicon layer 23 on the first substrate 20 are combined with each other by a high temperature process. Please refer to Figure 1C. Using the first oxide layer 21 as an etch stop layer, the first substrate 20 is honed to the first oxide layer 21. In the first oxide layer 21, the 4th < Please read the business matters on the back before filling out this page) One Pack --- Jl ·! · Order --- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 447 1 2 6 A7 6704twf.doc / 008 V. Description of the invention (>) —Buried oxide layer 22 and The semiconductor layer 20a between the undoped polycrystalline silicon layers 23 is etched with uranium to form a trench isolation region. An oxide layer is deposited on the isolation region of the first oxide layer 21, the semiconductor layer 20a and the trench, and then the oxide layer is planarized to form an isolation oxide layer 26. Next, a photoresist layer 27 is covered on the first oxide layer 21, the semiconductor layer 20a and the isolation oxide layer 26. This photoresist layer 27 is defined and removed to expose a portion of the isolation oxide layer 26. Using the defined photoresist layer 27 as a mask, boron ions are implanted into the undoped polycrystalline silicon layer 23 to generate a P-type heavily doped polycrystalline layer 23a. Please refer to Figure 1D. Next, another photoresist layer 28 covers the first oxide layer 21, the semiconductor layer 20a, and the isolation oxide layer 26, and the photoresist layer 28 is defined. The photoresist layer 28 is removed to expose a portion of the isolation oxide layer covered by the photoresist layer 27 from the previous step. Using the defined photoresist layer 28 as a mask, phosphorus ions are implanted into the undoped polycrystalline silicon layer 23 to generate an N-type heavily doped polycrystalline silicon layer 23b. Please refer to Figure 1E. An oxide layer and a silicon layer are deposited and etched. As a result, a gate oxide layer 29 and a first gate electrode 30a are formed on the semiconductor layer 20a as an NMOS transistor, and a gate oxide layer 29 and a second gate electrode 30b are formed as a PMOS transistor. Please refer to Figure 1F. A photoresist layer 31 is formed and defined to expose the semiconductor layers 20a on both sides of the second gate electrode 30b, and the first gate electrode 30a is not exposed. Using the defined photoresist layer 31 as a mask, P-type boron ions are implanted into the P-type semiconductor layer 20b to form shallowly doped source / drain regions 32a, 32b. 5 ---------- Loading ------- J Orders ------------ (Please read the precautions on the back before filling this page) This paper size is applicable to the country National Standard (CNS) A4 Specification (210 X 297 mm) 447126 A7 B7 6704twf.doc / 008 V. Description of Invention (屮) < Please read the notes on the back before filling this page) Please refer to Figure 1G. A photoresist layer 33 is formed and defined to expose the semiconductor layers 20a on both sides of the first gate electrode 30a, and the second gate electrode 30b is not exposed. Using the defined photoresist layer 33 as a mask, the N-type semiconductor layer 20c is implanted with N-type arsenic ions to form shallowly doped source / drain regions 34a, 34b. Please refer to Figure 1H. An insulating layer 35 is deposited and removed to expose the P-type semiconductor layer 20b, the N-type semiconductor layer 20c, the P-type source / drain regions 32a, 32b, the N-type source / drain regions 34a, 34b, and a contact hole. A conductive layer is formed to fill the contact holes. This conductive layer is then etched to form the contact pads 36a, 36f on the P-type and N-type semiconductor layers 20b, 20c and the linear layers 36b, 36c on the P-type and N-type source / drain regions 32a / 32b and 34a / 34b » 36d »36e ° The conventional method for manufacturing an SOI semiconductor device includes implanting P-type ions to form regions 20b, 32a, and 32b. In addition, conventional methods require implanting N-type ions to form regions 20c, 34a, 34b. Since the photoresist layer is used as a mask for ion implantation, it needs to go through two lithography processes and two ion implantation steps, thereby increasing the complexity of the process and its cost. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention provides a method for manufacturing a silicon (SOI) semiconductor element with an insulating layer, which can overcome the shortcomings of the conventional SOI element. A first semiconductor substrate is etched to form a plurality of trenches. An oxide layer is deposited on the substrate and the trench. A first oxide layer is deposited over the trench. A first buried oxide layer is formed on the first semiconductor substrate. A photoresist layer is formed on the first buried oxide layer and defined to expose the first buried oxide layer. Use the exposed photoresist layer as a mask to remove the first buried oxide layer. 6 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) A7 B7 447 12 6 6704twf.doc / 008 5 2. Description of the invention) divided by to expose the first substrate. An undoped polycrystalline silicon layer is then deposited on the first buried oxide layer and the first substrate. The undoped polycrystalline silicon layer is then etched back. A second buried oxide layer is deposited on a second substrate. Next, a high-temperature process is used to combine the second buried oxide layer on the second substrate with the non-miscellaneous polycrystalline sand layer on the first substrate. The first oxide layer is used as a contact stop layer, and the first substrate is honed until the first oxide layer is exposed. In the first oxide layer, a semiconductor layer between the first buried oxide layer and the undoped polycrystalline silicon layer is etched to form a trench isolation region. An oxide layer is deposited on the first oxide layer, the semiconductor layer and the trench isolation area, and then the oxide layer is planarized to form an isolation oxide layer. Then, a photoresist layer is covered on the first oxide layer, the semiconductor layer and the isolation oxide layer. Define this photoresist layer and remove it to expose part of the isolation oxide layer. Using a defined photoresist layer as a mask, an undoped polycrystalline silicon layer is implanted, for example, boron ions to produce a P-type heavily doped polycrystalline silicon layer. Then, another photoresist layer is covered on the first oxide layer, the semiconductor layer and the isolation oxide layer, and the photoresist layer is defined. Then remove the photoresist layer to expose the part of the isolation oxide layer covered by the photoresist layer in the previous step. Β Use the defined photoresist layer as a mask to implant the undoped polycrystalline silicon layer. For example, It becomes an N-type heavily doped polycrystalline silicon layer. An oxide layer and a silicon layer are deposited and etched. As a result, a gate oxide layer and a first gate electrode are formed on the semiconductor layer as an NMOS transistor, and a gate oxide layer and a second gate electrode are formed as a PMOS transistor. Form 7 This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Loading ----- ^! —Order ·! AUT. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 47 彳 2 6 A7
6704tw£doc/00S _H7_ 五、發明說明（（） 一摻雜介電層覆蓋於基底，此摻雜介電層的材質例如是N 型摻雜磷矽玻璃，其形成方法例如是化學氣相沉積法。 形成一光阻層覆蓋於介電層且定義之。去除部分摻雜介電 層以暴露出第二閘極電極兩側之半導體層，且第一閘極電 極沒有被暴露出來。使用已定義之光阻層作爲罩幕，對P 型半導體層植入P型硼離子以形成淺摻雜源/汲極區。然 後去除光阻層。 接著，將摻雜介電層內的η型摻質輸入N型半導體層 內以形成淺摻雜源/汲極區。 沉積並去除一絕緣層以暴露出Ρ型半導體層、Ν型半 導體層、Ρ型源/汲極區，與Ν型源/汲極區以及形成接觸 洞。形成一傳導層以塡滿該些接觸洞。然後蝕刻此傳導層 以形成Ρ型與Ν型半導體層上的接觸墊以及Ρ型與Ν型 源/汲極區上的線形層。 爲譲本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1Α圖是習知一種SOI半導體元件的剖面圖； 第1B圖至第1H圖是習知一種製造第1A圖之SOI元件的 流程剖面圖； 第2A圖至第2L圖是依照本發明一較佳實施例一種製造 SOI半導體元件的流程剖面圖；以及 第31圖至第3L圖是依照本發明另一較佳實施例一種製造 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (靖先閲讀背面之注意事項再填窝本頁〕 裝-----r---訂------丨！^ 47126 五、發明說明（9 ) SOI半導體元件的流程剖面圖。 標記之簡單說明： (請先閱讀背面之注意事項再填寫本頁) 20，20a，24，220，220a，224，320a，320b，324 :半導 體基底 20b，220b，320b P 型半導體層 20c，220c，320c : N型半導體層 21，221 :氧化層 22，22a，25，222，225 :埋入氧化層 23，223 :未摻雜的厚多晶矽層 23a，223a: P型重摻雜多晶矽層 23b，223b : N型重摻雜多晶矽層 26，226 :隔離氧化層 27，28，31，33，227，228，231，233，331，333 :光阻 層 29，229，329 :閘氧化層 30a，30b，230a，230b，330a，330b :閘極電極 32a/32b，34 a/34b，232a/232b，234a/234b，332a/332b， 334a/334b :源/汲極區 經濟部智慧財產局員工消費合作社印製 35，235，335 :內層絕緣層 36 a，36f ’ 236a，236f，336a，336f :接觸墊 36b ， 36c ， 36d ， 36e ， 236b ， 236c ， 236d ， 236e ， 336b ， 336c，336d，336e :線形層 250，350‘：摻雜介電層 實施例 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 4 7 12 6 A7 B7 6704twf.doc/008 五、發明說明（3 ) 第2A圖至第2L圖是依照本發明一較佳實施例一種製 造SOI半導體元件的流程剖面圖 (請先閱讀背面之注意事項再填窝本頁) 請參照第2A圖。蝕刻一第一半導體基底220以形成 複數個溝渠。沉積一塡滿溝渠之第一氧化層221。 請參照第2B圖，形成一第一埋入氧化層222於第一半導 體基底上220。 請參照第2C圖，形成一光阻層於第一埋入氧化層222 上且定義之，以暴露出第一埋入氧化層222。使用已曝光 之光阻層作爲罩幕，將第一埋入氧化層222去除以暴露出 第一基底220。然後沉積一未摻雜的多晶砂層於第一埋入 氧化層222與第一基底220上。然後對未摻雜的多晶矽層 進行回蝕以形成一未摻雜的多晶矽層223。 沉積一第二埋入氧化層225於一第二基底224上。 請參照第2D圖，利用一高溫製程將第二基底224上 的第二埋入氧化層2M與第一基底220上之未摻雜的多晶 矽層223相互結合。 經濟部智慧財產局員工消費合作社印製 請參照第2E圖，以第一氧化層221爲蝕刻終止層’ 將第一基底220硏磨至暴露出第一氧化層221。在第一氧 化層221，第一埋入氧化層222與未摻雜的多晶矽層223 之間的半導體層220a被蝕刻以形成溝渠隔離區。一氧化 層沉積於第一氧化層221、半導體層220a與溝渠隔離區 上，然後平坦化此氧化層以形成一隔離氧化層226 ° 請參照第2F圖，以一光阻層227覆蓋於第一氧化層 221、半導體層220a與隔離氧化層226上。定義此光阻層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 447126 6704twf,doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（吁） 2W且去除之以暴露出部分的隔離氧化層226。使用已定 義之光阻層22"7作爲罩幕，對未摻雜的多晶砂層223植入 硼離子以產生一 P型重摻雜多晶矽層223a。 請參照第2G圖，.以另一光阻層228覆蓋於第一氧化 層221、半導體層i20a與隔離氧化層226上，且定義此光 阻層228。然後去除光阻層228以暴露出於前步驟被光阻 層227所覆蓋之部分隔離氧化層。使用已定義之光阻層228 作爲罩幕，對未摻雜的多晶矽層223a植入磷離子以成爲 一 N型重摻雜多晶矽層223b。 請參照第2H圖，沉積一氧化層與一矽層並蝕刻之。 結果在半導體層220a上形成一閘氧化層229和一第一閘 極電極230a作爲NMOS電晶體，以及一閘氧化層229和 一第二閘極電極230b作爲PMOS電晶體。 請參照第21圖，形成一摻雜介電層250覆蓋於基底224 的表面，此摻雜介電層的材質例如是N型摻雜磷矽玻璃 (Phosphosilicate Glass)或 N 型摻雜旋塗式玻璃（Spin-On-Glass)，其形成方法例如是化學氣相沉積法。 請參照第2J圖，形成一光阻層231覆蓋於摻雜介電層 250且定義之。去除部分摻雜介電層250以暴露出第二閘 極電極230b兩側之半導體層220a和除了第一閘極電極 230a之外的半導體層220b，此處除了第二閘極電極230b 外之第一閘極電極230a與半導體層220a都沒有暴露出 來。使用已定義之光阻層231作爲罩幕’對P型半導體層 220b植入P型硼離子以形成淺摻雜源/汲極區232a/232b。 (ϊ閱讀背面之注意事項再填寫本頁) 裝 訂---- ο 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公爱〉 A7 B7 ^ 447126 6704twf.doc/008 五、發明說明（) 然後去除光阻層231。 請參照第2K圖，將摻雜介電層250內的η型摻質在 高溫鈍氣的環境下輸入Ν型半導體層內，以形成η+摻雜源 /汲極區234a/234b。和第2Κ圖中的η+摻雜半導體層220c 一樣。 請參照第2L圖，沉積並去除一絕緣層235以暴露出P 型半導體層220b、N型半導體層220c、P型源/汲極區 232a/232b，與N型源/汲極區234a/234b以及形成接觸洞。 形成一傳導層以塡滿該些接觸洞。然後鈾刻此傳導層以形 成P型與N型半導體層220b，220c上的接觸墊236a，236f 以及η與p源/汲極區232a/232b，234a/234b上的線形層 236b，236c，236d，236e ° 第31圖至第3L圖是依照本發明另一較佳實施例一種 製造SOI半導體元件的流程剖面圖。 本實施例之步驟和第2A圖至第2L圖形成SOI的步驟 一樣，然後參照第31圖。在半導體層320a上形成閘氧化 層329與第一閘極電極330a作爲NM0S電晶體，以及一 閘氧化層329和一第二閘極電極330b作爲PM0S電晶體。 請參照第31圖，形成一摻雜介電層350覆蓋於基底324 的表面，此摻雜介電層的材質例如是P型摻雜硼矽玻璃 (Boronsilicate Glass)或 P 型摻雜旋塗式玻璃（Spin-On-Glass)，其形成方法例如是化學氣相沉積法。 請參照第3J圖，形成一光阻層331覆蓋於摻雜介電層 350且定義之。去除部分摻雜介電層350以暴露出第二閘 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------(/....:-裝-----！----訂------1!^1WT (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 44712 6 A7 6704^〇〇/008 B7 — 11 — 五、發明說明（ll ) 極電極330b兩側之半導體層32〇a和除了第二閘極電極 330b之外的半導體層32〇b，此處除了第—閘極電極33〇a 外之第二閣極電極330b與半導體層32〇b都沒有暴露出 來。使用已定義之光阻層331作爲罩幕，對n型半導體層 320c植入N型砷離子以形成摻雜源/汲極區334a/334b。然 後去除光阻層3 3 1。 請參照第3K圖，將摻雜介電層350內的p型摻質輸 入除了第一閘極電極330b之外的P型半導體層內，以形 成摻雜源/汲極區332a/332b。 第3L圖是依照本發明一較佳實施例—種s〇I半導體 元件的剖面圖。請參照第3L圖，沉積並去除一絕緣層335 以暴露出N型半導體層320a、P型半導體層320c、P型源 /汲極區332a/332b，與N型源/汲極區334a/334b以及形成 接觸洞。形成一傳導層以塡滿該些接觸洞。然後蝕刻此傳 導層以形成P型與N型半導體層320b，320c上的接觸墊 336a，336f 以及 η 與 p 源/汲極區 332a/332b，334a/334b 上的線形層 336b，336c，336d，336e。 本發明之優點在於只需要一層微影罩幕就可以代替習 知形成摻雜區時所需的兩個步驟。本發明的另一個優點是 NMOS與PMOS電晶體的通道區域，分別利用穿過第一、 第二傳導型多晶矽層的接觸墊與第一、第二傳導型半導體 層相連結，因此降低浮置體效應（Floating Body Effects) 並且增進操作特性。 雖然本發明已以一較佳實施例揭露如上，然其並非用 13 (請先閲讀背面之注意事項再填寫本頁) 裝----l· — !訂-I! ο. 經濟部智慧財產局員Η消費合作社印製 本紙張尺度適用1f1國國家標準（CNS)A4規格（2】〇χ 297公釐） A7 B7 447126 6704twf.doc/008 五、發明說明（\〜） 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (諳先閲讀背面之#一意事項再填窝本頁) 經濟部智慧財產局員工消費合作社印製 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）6704tw £ doc / 00S _H7_ V. Description of the Invention (() A doped dielectric layer covers the substrate. The material of this doped dielectric layer is, for example, N-type doped phosphosilicate glass, and its formation method is, for example, chemical vapor deposition. A photoresist layer is formed to cover the dielectric layer and is defined. A part of the doped dielectric layer is removed to expose the semiconductor layers on both sides of the second gate electrode, and the first gate electrode is not exposed. The defined photoresist layer is used as a mask. The P-type semiconductor layer is implanted with P-type boron ions to form a shallow doped source / drain region. Then the photoresist layer is removed. Next, the n-type dopant in the doped dielectric layer is doped. Into the N-type semiconductor layer to form a shallow doped source / drain region. An insulating layer is deposited and removed to expose the P-type semiconductor layer, the N-type semiconductor layer, the P-type source / drain region, and the N-type source / drain region. The drain region and a contact hole are formed. A conductive layer is formed to fill the contact holes. The conductive layer is then etched to form contact pads on the P-type and N-type semiconductor layers and P-type and N-type source / drain regions For the above and other objects, features and advantages of the present invention, Obviously easy to understand, the following is a detailed description of a preferred embodiment in conjunction with the accompanying drawings: Detailed description of the drawings: Figure 1A is a cross-sectional view of a conventional SOI semiconductor element; Figures 1B to 1 FIG. 1H is a cross-sectional view of a conventional process for manufacturing an SOI device of FIG. 1A; FIGS. 2A to 2L are cross-sectional views of a process for manufacturing an SOI semiconductor device according to a preferred embodiment of the present invention; The 3L drawing is made in accordance with another preferred embodiment of the present invention. 8 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Jing first read the precautions on the back and then fill the nest page). ---- r --- Order ------ 丨! ^ 47126 V. Description of the invention (9) Process cross-sectional view of the SOI semiconductor element. Brief description of the mark: (Please read the precautions on the back before filling in this Page) 20, 20a, 24, 220, 220a, 224, 320a, 320b, 324: semiconductor substrates 20b, 220b, 320b P-type semiconductor layers 20c, 220c, 320c: N-type semiconductor layers 21, 221: oxide layers 22, 22a 25, 222, 225: buried oxide layer 23, 223: undoped thick polycrystalline silicon Layers 23a, 223a: P-type heavily doped polycrystalline silicon layers 23b, 223b: N-type heavily doped polycrystalline silicon layers 26, 226: isolation oxide layers 27, 28, 31, 33, 227, 228, 231, 233, 331, 333: Photoresist layers 29, 229, 329: gate oxide layers 30a, 30b, 230a, 230b, 330a, 330b: gate electrodes 32a / 32b, 34 a / 34b, 232a / 232b, 234a / 234b, 332a / 332b, 334a / 334b: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Source / Drain Region. 35,235,335: Insulation layers 36a, 36f '236a, 236f, 336a, 336f: Contact pads 36b, 36c, 36d, 36e, 236b, 236c, 236d, 236e, 336b, 336c, 336d, 336e: Linear layer 250, 350 ': Doped dielectric layer Example 9 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 4 4 7 12 6 A7 B7 6704twf.doc / 008 V. Description of the invention (3) Figures 2A to 2L are cross-sectional views of a process for manufacturing an SOI semiconductor device according to a preferred embodiment of the present invention (please read the back Note for refilling this page) Please refer to Figure 2A. A first semiconductor substrate 220 is etched to form a plurality of trenches. A first oxide layer 221 is deposited over the trench. Referring to FIG. 2B, a first buried oxide layer 222 is formed on the first semiconductor substrate 220. Referring to FIG. 2C, a photoresist layer is formed on the first buried oxide layer 222 and defined to expose the first buried oxide layer 222. Using the exposed photoresist layer as a mask, the first buried oxide layer 222 is removed to expose the first substrate 220. An undoped polycrystalline sand layer is then deposited on the first buried oxide layer 222 and the first substrate 220. The undoped polycrystalline silicon layer is then etched back to form an undoped polycrystalline silicon layer 223. A second buried oxide layer 225 is deposited on a second substrate 224. Referring to FIG. 2D, the second buried oxide layer 2M on the second substrate 224 and the undoped polycrystalline silicon layer 223 on the first substrate 220 are combined with each other by a high temperature process. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to FIG. 2E, using the first oxide layer 221 as an etching stopper layer, and honing the first substrate 220 to expose the first oxide layer 221. In the first oxide layer 221, the semiconductor layer 220a between the first buried oxide layer 222 and the undoped polycrystalline silicon layer 223 is etched to form a trench isolation region. An oxide layer is deposited on the first oxide layer 221, the semiconductor layer 220a and the trench isolation area, and then the oxide layer is planarized to form an isolated oxide layer 226 °. Please refer to FIG. 2F, and cover the first with a photoresist layer 227 The oxide layer 221, the semiconductor layer 220a, and the isolation oxide layer 226 are formed. Definition of this photoresist layer This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 447126 6704twf, doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (call) 2W And it is removed to expose a part of the isolation oxide layer 226. Using the defined photoresist layer 22 " 7 as a mask, boron ions are implanted into the undoped polycrystalline sand layer 223 to generate a P-type heavily doped polycrystalline silicon layer 223a. Referring to FIG. 2G, the first oxide layer 221, the semiconductor layer i20a, and the isolation oxide layer 226 are covered with another photoresist layer 228, and the photoresist layer 228 is defined. The photoresist layer 228 is then removed to expose a portion of the isolation oxide layer covered by the photoresist layer 227 from the previous step. Using the defined photoresist layer 228 as a mask, phosphorus ions are implanted into the undoped polycrystalline silicon layer 223a to become an N-type heavily doped polycrystalline silicon layer 223b. Referring to FIG. 2H, an oxide layer and a silicon layer are deposited and etched. As a result, a gate oxide layer 229 and a first gate electrode 230a are formed on the semiconductor layer 220a as NMOS transistors, and a gate oxide layer 229 and a second gate electrode 230b are formed as PMOS transistors. Referring to FIG. 21, a doped dielectric layer 250 is formed to cover the surface of the substrate 224. The material of the doped dielectric layer is, for example, N-type doped phosphosilicate glass or N-type doped spin-on coating. Glass (Spin-On-Glass) is formed by, for example, a chemical vapor deposition method. Referring to FIG. 2J, a photoresist layer 231 is formed to cover the doped dielectric layer 250 and is defined. A part of the doped dielectric layer 250 is removed to expose the semiconductor layer 220a on both sides of the second gate electrode 230b and the semiconductor layer 220b other than the first gate electrode 230a. Neither a gate electrode 230a nor the semiconductor layer 220a is exposed. The P-type semiconductor layer 220b is implanted with P-type boron ions to form a shallowly doped source / drain region 232a / 232b using the defined photoresist layer 231 as a mask. (ϊPlease read the notes on the back and fill in this page again) Binding ---- ο This paper size applies to China National Standard (CNS) A4 specifications (2) 0 X 297 public love> A7 B7 ^ 447126 6704twf.doc / 008 V. Description of the invention () Then the photoresist layer 231 is removed. Referring to FIG. 2K, the n-type dopant in the doped dielectric layer 250 is input into the N-type semiconductor layer under a high-temperature inert gas environment to form an η + dopant. Source / drain regions 234a / 234b. Same as η + doped semiconductor layer 220c in Fig. 2K. Please refer to Fig. 2L, deposit and remove an insulating layer 235 to expose P-type semiconductor layer 220b, N-type semiconductor layer 220c, P-type source / drain regions 232a / 232b, and N-type source / drain regions 234a / 234b, and contact holes are formed. A conductive layer is formed to fill the contact holes. Then the conductive layer is engraved to form P Contact pads 236a, 236f on N-type and N-type semiconductor layers 220b, 220c and linear layers 236b, 236c, 236d, 236e on n and p source / drain regions 232a / 232b, 234a / 234b ° Figures 31 to 3L FIG. Is a cross-sectional view of a process for manufacturing an SOI semiconductor device according to another preferred embodiment of the present invention. Steps of this embodiment and 2A The steps for forming the SOI to FIG. 2L are the same, and then refer to FIG. 31. A gate oxide layer 329 and a first gate electrode 330a are formed on the semiconductor layer 320a as NMOS transistors, and a gate oxide layer 329 and a second gate electrode are formed. The electrode 330b is a PMOS transistor. Referring to FIG. 31, a doped dielectric layer 350 is formed to cover the surface of the substrate 324. The material of the doped dielectric layer is, for example, P-type doped borosilicate glass (Boronsilicate Glass) or The P-type doped spin-on glass (Spin-On-Glass) is formed by, for example, a chemical vapor deposition method. Referring to FIG. 3J, a photoresist layer 331 is formed to cover the doped dielectric layer 350 and is defined .Remove part of the doped dielectric layer 350 to expose the second gate 12 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----------- (/ .. ..:-Installation -----! ---- Order ------ 1! ^ 1WT (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 44712 6 A7 6704 ^ 〇〇 / 008 B7 — 11 — V. Description of the Invention (11) The semiconductor layers 32 oa on both sides of the electrode 330b and other than the second gate electrode 330b The semiconductor layer 32b, except the first gate electrode 330a, and the second grid electrode 330b and the semiconductor layer 32b are not exposed. Using the defined photoresist layer 331 as a mask, the The n-type semiconductor layer 320c is implanted with N-type arsenic ions to form doped source / drain regions 334a / 334b. Then, the photoresist layer 3 3 1 is removed. Referring to FIG. 3K, a p-type dopant in the doped dielectric layer 350 is input into a P-type semiconductor layer other than the first gate electrode 330b to form a doped source / drain region 332a / 332b. FIG. 3L is a cross-sectional view of a SOI semiconductor device according to a preferred embodiment of the present invention. Referring to FIG. 3L, an insulating layer 335 is deposited and removed to expose the N-type semiconductor layer 320a, the P-type semiconductor layer 320c, the P-type source / drain regions 332a / 332b, and the N-type source / drain regions 334a / 334b. And forming contact holes. A conductive layer is formed to fill the contact holes. This conductive layer is then etched to form contact pads 336a, 336f on P-type and N-type semiconductor layers 320b, 320c and linear layers 336b, 336c, 336d on n and p source / drain regions 332a / 332b, 334a / 334b, 336e. The advantage of the present invention is that only one lithographic mask is required to replace the two steps required to form the doped region as is conventionally known. Another advantage of the present invention is that the channel regions of the NMOS and PMOS transistors are connected to the first and second conductive semiconductor layers by using contact pads passing through the first and second conductive polycrystalline silicon layers, respectively, thereby reducing the floating body. Effects (Floating Body Effects) and improve operating characteristics. Although the present invention has been disclosed as above with a preferred embodiment, it is not used 13 (please read the precautions on the back before filling out this page). ---- l · —! Order-I! Ο. Intellectual Property of the Ministry of Economic Affairs Bureaux / Consumer Cooperative Co., Ltd. Print this paper to apply the 1f1 National Standard (CNS) A4 specification (2) 0 × 297 mm. A7 B7 447126 6704twf.doc / 008 5. Description of the invention (\ ~) To limit the invention, any Those skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the # 一 意 项 on the back before filling in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 14 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)