TW447115B - Storage electrode with porous, rough inner wall and the DRAM capacitor - Google Patents

Abstract

The capacitor in accordance with the present invention comprises: a storage electrode, a plurality of semi-spherical silicon grains, the dielectric and the conductive layer; in which the storage electrode is located on the semiconductor substrate that the storage electrode and the conductive area on the substrate are formed as electrical connections; the storage electrode comprises porous structure with a plurality of holes extending from the upper surface of the storage electrode downwardly, and there are rough surfaces in the plurality of holes; the semi-spherical silicon grains are located on the sidewall of the storage electrode; the dielectric is covering the porous structure, the storage electrode and a plurality of semi-spherical silicon grains; the conductive layer is located on the dielectric layer.

Description

447115 A7 B7 V. Description of the invention () 5-1 Field of the invention: The present invention relates to a dynamic random access memory capacitor, in particular, to a dynamic random access memory capacitor having a porous shape and a thick seam. Storage electrode on inner wall, and method for forming the same. 5-2 Background of the Invention: Due to the popularity of electronic products and computer-related products, the demand for semiconductor memory components has increased rapidly. The first figure shows a schematic diagram of the memory 14 and related tissue systems. The memory storage units of the memory 14 are arranged in an array structure having horizontal columns and vertical rows. All the wires connecting the memory in the horizontal direction are called word line U, and the wires connecting the memory in the vertical direction are called bit line 1 3, and data enters and exits through these bit lines 13 〇Column address 10 and row address 12 are used to select one of the many memories 1 4. The column address buffer 15 and the row address buffer 17 are used to temporarily store the column address 10 signal and the row address 12 signal, respectively. Then, the column address buffer 15 and the row address buffer 17 send these signals to the column decoder 16 and the row decoder 18 ', respectively, to generate a word line (wordiine) ii and a bit line (bit 1 ine) 1 3, this decoder is used to reduce access to many memories. 2 This paper size is applicable to China National Standard (CNS) A4 specifications (210X297 mm). —— \] / (# 先 读-# 面Note ¾ One thing ^ Fill in this page)-447115 A7 __B7_ printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention () Number of address signal lines. The signals generated by the column decoder 16 and the row decoder 18 are used to select one of the memory storage units. The array structure of the above-mentioned memory system 14 (such as dynamic random access memory) is very suitable for the ultra-large integrated circuit. Regular structure required during design and manufacture. Figure 2A shows a schematic circuit diagram of the memory storage unit. The gate of the transistor 20 is controlled by a word line signal. The capacitor 22 for storing data is connected to the source of the transistor 20 and passes through the drain of the transistor 20 and the bit line.丨 ine) to read or write data to the capacitor 22 ° Due to its low cost per bit, high density feasibility, and flexible use of reading and writing, dynamic random access memory has become the main component of semiconductor memory elements 1 ° However, as the density of dynamic random access memory becomes higher and higher, the area of its capacitance becomes smaller, and its capacitance also becomes smaller. Figure 2B shows a sectional view of a conventional dynamic random access memory capacitor. The capacitor is composed of a storage electrode 24 and a dielectric layer 26. As the size of the memory gradually decreases with the advancement of technology and the increase in demand for high-density memory components, the area of its capacitance will then decrease, resulting in a smaller capacitance. However, in order to reduce memory reading errors caused by external radiation interference, memory elements must maintain a certain capacitance. Therefore, how to reduce the size of the memory components and get a high-capacity electricity at the same time — I-- (Please read the note on 4 sides 彳 1 2 write this page) Order _ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs System 1 2 This paper size is applicable to the national standard (CNS) A2 specification (210X297 mm) t 447 1 15 A7 B7 V. Description of the invention () Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has become an important and urgent need To solve the current task, in order to increase the capacitance and maintain the high integration of the storage cells, it has been proposed to form finger-shaped, cylindrical or rectangular multi-layer structures or spacers in the polycrystalline silicon layer to increase the capacitor. Surface area of the electrode. However, the increase in capacitance obtained by increasing the surface area of such conventional capacitors is still not enough to make up for the decrease in capacitance caused by the reduction in the size of memory cells. 5-3 Purpose and Summary of the Invention: In the context of the above-mentioned invention, the disadvantages of the conventional dynamic random access memory capacitors, the present invention proposes a storage electrode for forming a dynamic random access memory valley with porous and rough inner walls, And its formation method is used to increase the electric capacity and maintain the high integration of the storage unit. The capacitor structure provided by the present invention may mainly include: a storage electrode, a plurality of hemispherical particles, a dielectric layer, and a conductive layer; the storage electrode is located on a semiconductor substrate, and the storage electrode and the conductive region on the substrate form an electrical circuit. The storage electrode is sexually connected and has a porous structure. The porous structure includes a plurality of recessed holes extending downward from the upper surface of the storage electrode, and a plurality of recessed holes and a surface with a thick seam; the hemispherical silicon particles are located on the storage electrode. On the side wall; the dielectric layer of private paper is applicable to China @ 家 标准 (CNS) 八 4Touch_ (2IGx297 公 酱)

Hi .in HI (Please read the notes on the back page first) Order 447 1 1 5

V. Description of the invention (they are covered on the porous structure and stored (please read this note to fill in this page first); the conductive layer is on the dielectric layer. And several hemispherical silicon particles are taught in the present invention The order of the embodiment ^ Firstly, the first dielectric layer is formed on half, and the steps of forming the capacitor are as follows: first on the first dielectric layer; then forming the cage = 7 substrate; and forming the second dielectric layer on the case. The three dielectric layers and the second dielectric layer are formed on the second dielectric layer, and then a doped first-dielectric layer is formed to form a contact hole. Ran De # 忐 ® 人 多 ^ 夕Layer in the contact hole and on the third dielectric layer, 'depleted, reconstituted as a fourth dielectric thundershower thermal connection layer on the doped polycrystalline silicon layer; and then patterning the fourth dielectric layer and the polysilicon layer' to define Storage electrode; and forming a hemispherical particle layer (HSG) on the fourth dielectric layer, the doped polycrystalline silicon and the third ordered dielectric layer Jl to etch a half 5 bracket-shaped particle layer to define a plurality of holes in the hemispherical particles The fourth dielectric layer is exposed between the particles of the layer through a plurality of holes; and the fourth dielectric layer etched under the plurality of holes is etched under the fourth dielectric layer. And doped polycrystalline silicon layer to form a porous electrode; then a wet etching process is performed to remove the fourth dielectric layer and the third dielectric layer, and to etch the sidewalls of the recessed holes in the porous electrode to form the roughness in the recessed holes; The surface is formed; and a fifth dielectric layer is formed on the storage electrode; and finally, a conductive layer is formed on the fifth layer. Group photo and body memory display diagram

Centimeter 97 2 X 447115 A7 B7 V. Description of the invention

Show the picture AB Show the picture of the electric power of the single-storage system of the system and the special method of the mixed method, according to the layer of the electric display of the third picture of the third, the first layer of the dielectric and the second picture of the crystal capacity Mindfulness, the first and first layers of the dielectric layer, the dielectric layer, the silicon layer, and the silicon layer are shown on the basis of the root section. The material layer is shown in the figure. Miscellaneous layers and diagrams show the granular layered balls of the Mingfa layer in the fourth layer of the dielectric layer of this layer. 9 The half-map Chengyi 2 cuts of the Mingming layer of the Mingfa layer (please read the back page first) Note 1 ^, write this page)-Mounting-(HSG) A schematic cross-sectional view of the fourth dielectric layer, the side wall of the doped polycrystalline silicon layer, and the third dielectric layer. The sixth figure shows a schematic cross-sectional view of a fourth dielectric layer and a doped polycrystalline silicon layer etched underneath it through a plurality of holes according to the method of the present invention. The seventh figure shows a wet etching process to remove the fourth dielectric layer and the third dielectric layer according to the method of the present invention, and to etch the sidewalls of the recessed holes in the porous electrode to form a roughening in the recessed holes. Surface and cross-section schematic diagram of capacitor production. 5-5 Detailed description of the invention: The embodiments of the present invention can be introduced by the following steps. The third and sixth paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (2I0X297 public change). Printed 447 1 1 5 A7 B7 V. Description of the invention () (Please read the back, note $ item on the front \ ^ write this page} The cross-sectional view shows a schematic cross-sectional view of the semiconductor substrate 110. First, the traditional method A first dielectric layer 112 is formed on the material 110: the first dielectric layer 112 can be formed by depositing tetrahexyl silicate (TEOS) as a reactive gas on the substrate 110 ', or depositing borophosphosilicate glass (BPS G), etc. as the main material for insulation between different conductive areas. Next, a second dielectric layer 113 is formed on the first dielectric layer 112; in this example, the second dielectric layer 113 is oxidized. The silicon layer is used to match the different processes in the second embodiment, and is used as an etching stop layer in subsequent processes. The coded silicon nitride layer can use traditional low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical gas. Phase deposition (PECVD). Form a third dielectric layer 114 on top of the second dielectric layer 113 'The third dielectric layer U 4 in this example is a silicon nitride layer and can be formed by a conventional chemical vapor deposition (CVD) method 》 After that, the third dielectric layer 114 ', the second dielectric layer 113, and the first dielectric layer 112' are filed to define a contact hole therein to communicate with a conductive region on the underlying substrate 110, such as a source Polar regions, etc. to provide the space needed to form an electrical connection. ”Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and then forming a doped polycrystalline silicon layer 118 on the third dielectric layer 114 and filling the contact hole 1 160. In this embodiment, the doped polycrystalline silicon layer n 8 is formed using a conventional chemical vapor deposition method, and the thickness of the doped polycrystalline silicon layer n 8 on the surface of the oxide dream layer 1 14 is about 3,000-7000 angstroms. A fourth dielectric layer 119 is formed on this paper scale. It is used in the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 447 1 1 5 A7 B7 V. Description of the invention () Doped polycrystalline silicon layer 118 In a preferred embodiment, the fourth dielectric layer 1 1 9 may be a silicon nitride layer, and may use conventional chemical vapor deposition. It is formed by CVD method. In this example, the thickness of the fourth dielectric layer 119 is between about 500,000 and 50,000 Angstroms' β, and then a photolithography process is used to form and pattern the photoresist layer 丨 2 〇 On the fourth dielectric layer 119, the formation shape and area of the storage capacitor are defined. As shown in the fourth figure, using the photoresist layer 120 as a mask, the fourth dielectric layer 119 and the doped polycrystalline silicon layer are etched. 1 1 8. After a single or multiple etching process, a storage electrode can be formed as shown in the figure, and the photoresist layer 12 can be removed. See FIG. I and form hemispherical particles ( hemi_ spherical grain (HSG) layer 124 is deposited on the fourth dielectric layer, the sidewalls of the polycrystalline dream layer 118, and the third dielectric layer 114. In this example, a hemispherical granular silicon layer 124 is deposited. The thickness is about 200 to 1000 Angstroms, and the particle size is about 200 to 100 Angstroms. (# 先 闻 读 '^ 面 之 注 ¾ 事 产 4'Fill in this page}-装 、 -ιτ.

--V Printed I sheet by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-Examples of la in paper on the paper (S solid layer Jiazi compares to the granular granules and semi-granular granules before entering the force) Yu • Mi above layer 4 Electrical 11 Dielectric four dielectrics are between 30% and 30% of nitrogen on the side of the upper layer 8 1 Use 1 to make the layer silicon like crystal polysilicon 11 layered silicon Combined with the use of mixed to make the line standard | Suitable for use in countries and countries 29 447 115 A7 _B7_ 5 'Description of the invention (such as low pressure chemical vapor deposition (LPCVD) to form this titanium nitride layer to about 100 -300 Angstrom thickness, this thickness range can be between 50-1,000 Angstrom according to different needs. In this embodiment, the titanium nitride layer provides a nucleation area (HSG) 124 forming a hemispherical particle layer (HSG) 124 ( nucleationsite), and when the seed layer of the vaporized titanium layer is not applied, the nucleation area can be directly provided by the material or particles on the surface of the fourth dielectric layer 119, the doped polycrystalline silicon layer 118, and the third dielectric layer H4. Hemisphere Polycrystalline silicon (HSG) 124 gradually forms a majority from the gas phase Hemispherical particles, thus forming the structure shown in the fifth circle (for the technique of the hemispherical particle layer, refer to US Patent No. 5,612,558). The hemispherical particle layer is formed by using plasma enhanced chemical vapor deposition (PECVD) (HSG) I24 on the titanium nitride layer 122 can reduce the reaction temperature to 250. (: to 350 eC, or to about 300 ° C; and if the traditional low pressure chemical vapor deposition (LPCVD) method is used The temperature range of the semi-spherical particle layer can be about 500 ° C to 6500 ° C. »Then, the hemispherical particle layer (HSG) 124 is etched to form many exposures between the particles of the hemispherical particle layer (HSG) 124. The holes of the fourth dielectric layer 119 below are shown as shown in the fifth figure. Then, the lower fourth dielectric layer 1 1 9 and the doped polycrystalline silicon layer Π 8 are etched downward through these holes to form the first dielectric layer 119. The porous structure in the sixth figure, in the preferred embodiment, can be used in two 9-paper scales applicable to the national standard (CNS) A4 grid (210X297 mm).: ~ — .S) · (Please First read the note of the table $ 15 ^, fill out this page), 1T. Employees ’intellectual property bureau consumption Cooperative prints 447115 A7 B7 V. Description of the invention (The dry μ-etching process is performed with #etching of the fourth dielectric layer n 9 and the doped polycrystalline silicon layer u 8 to form a plurality of holes extending downward from the surface of the storage electrode; In a preferred embodiment, the depth of the formed hole is about 300 Angstroms to 3,000 Angstroms to increase the capacitance value of the capacitor by substantially increasing the surface area. During the etching process, most of the hemispherical particle layer (HSG) 124 on the surface of the fourth dielectric layer 119 is removed. In addition, the rectangular electrode shown in the sixth figure is only an introductory embodiment. * When the electrode is formed in various shapes, such as a round or oval shape, as required. Referring to FIG. 8, the fourth dielectric layer 119 and the third dielectric layer Π 4 are to be removed later. In the preferred embodiment, a wet etching process is used, and an etchant such as hot phosphoric acid is used to The fourth dielectric layer 119 and the third dielectric layer η4 composed of silicon nitride are removed, and the exposed polycrystalline silicon surface is etched to roughen it into a rough surface, thereby providing a porous storage hen pole inner wall The roughened surface is increased to increase its surface area, and the polycrystalline silicon exposed between the silicon particles on the side wall of the storage electrode will also be etched by hot phosphoric acid to form the surface of the concave Fa, forming a side wall as shown in the figure. Undulating shapes. In the above-mentioned wet etching process, the second dielectric layer I below. It can be used as an etching stop layer. In this example, due to the change of the wet etching time, the third dielectric layer 114 of the nitride nitride can not be completely removed, but a portion of the third dielectric can be left under the storage electrode. Layer 114, which is formed as the eighth Chinese paper standard applicable to Chinese National Standards (CNS) A4 specifications (210X297 mm)-\ ... ί (please read # 面 之 NOTICE first to write this page), tl Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 447 1 1 5 Α7 Β7 V. Description of the Invention () (Please read the notes on the back side and write this page first) The undercut shown in the figure. The effect of the staggered electrodes is provided, and a larger surface area is provided by the exposure of the lower surface. Next, a thin dielectric latent 136, such as an oxygen-nitrogen-oxygen (ONO) stacked layer on the polycrystalline hard layer 118 and The surface of the oxidized stone layer 114. Since the gas-nitrogen-oxygen (ONO) stacked layer 136 can be formed stably and with good coverage on a polycrystalline silicon surface having a surface shape change, it is often used as a capacitor dielectric. Here, the oxygen-nitrogen-oxygen (NO) stack layer is 136 t, and its bottom layer (and silicon oxide layer) is formed by a conventional thermal oxidation method, and then a low-pressure chemical vapor deposition method is used to deposit a silicon argon layer as an intermediate layer. The top oxide stone is formed by a conventional thermal oxidation method. Other materials, such as BST (BaSiTi03), PZT (lead zirconate titanate), Ta20s, Ti02 or NO (oxidation-nitriding dream) or other materials with better dielectric constant can also be used instead of oxygen-nitrogen -Oxygen (ΟΝΟ) »Finally, a conductive layer 138 is formed on the surface of the thin dielectric layer U6 as the electrode plate of the dynamic random access memory capacitor. The conductive layer 138 can also be a metal layer or a gold shoulder Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Therefore, by the above method, the capacitor structure of the second embodiment of the present invention can be formed, which can mainly include: storage electrode U8, a plurality of hemispheres The silicon particles 124, the dielectric layer 136, and the conductive layer 138; the storage electrode 118 is located on the semiconductor substrate 110. The storage electrode 118 is electrically connected to a conductive region on the substrate u0, and the storage electrode 118 has a porous junction The dimensions of this paper are in accordance with Chinese National Standard (CNS) 8-4 specifications (210 > < 297 mm) 447 彳 彳 5 A7 B7 V. Description of the invention ί! Teach a Πί ? · Shu ritr # ^ the more indisputable " a plurality of

The concave hole m has a plurality of concave holes and a surface with a thick chain; I is located on the storage electrode u δ ^ | € $ '· .. Structure, storage electrode m, and a plurality of hemispherical silicon particles 124; conductive The layer 138 is on the dielectric layer I%. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of the patent application. _I II n I (please note ## π4 write this page) Order the printed sheet of the WC Industry Consumer Cooperation Agreement of the Intellectual Property Bureau of the Ministry of Economic Affairs; paper 4 A) / s N c Use I suitable centimeter I male i 7 9 2

Claims (1)

447115 A8 B8 C8 D8 patent application domain 1 A memory capacitor at least includes: a storage electrode on a semiconductor substrate, the storage electrode is electrically connected to a conductive region on the substrate, the storage electrode has a porous structure, The porous structure includes a plurality of recessed holes 纟 自 肖 下 延 # from above the surviving electrode, and the plurality of recessed holes have a rough surface; a plurality of hemispherical broken particles #yo 1 'particles are stored in the storage On the sidewall of the electrode; a dielectric layer is connected to the dopene varnish, a porous structure, the storage electrode, and the plurality of hemispherical stone particles; and a conductive layer is on the dielectric layer. Please read Note I 2 · For example, Lei Jia, the first item in the patent application scope, contends 6 ^ ^ ^ further includes a stacked silicon nitride layer and a silicon nitride layer between the storage electrode and the substrate. 3. The capacitor according to the W range of the patent application, wherein the storage electrode has a recessed surface on the side wall of the storage electrode, between the hemispherical silicon particles. 4. The capacitor according to item 丨 of the patent application range, wherein the storage electrode mentioned above includes at least doped polycrystalline silicon. Order > Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed the environ- ment gas, Li Si specialization, please apply for oxygen, including as little as the description of the Tang Dianji. The middle layer is stacked, and the storage silicon is converted to oxygen. I 1 silicon 0 This paper size is based on the Chinese standard (CNS) A4 size (210X297 mm) 447 彳 彳 5 A8 B8 C8 DS 6. Application scope 6. The capacitor according to item 1 of the scope of patent application, wherein the above-mentioned dielectric layer is silicon oxide, silicon nitride, oxide button, titanium oxide, PZT, and BST. Printing 7. The capacitor according to item 1 of the scope of patent application, wherein the plurality of hemispherical silicon particles are formed by a plasma enhanced chemical vapor deposition method. 8. For the capacitor in the scope of the first patent application, the thickness of the above-mentioned plurality of hemispherical silicon particles is between about 200 and 1000 Angstroms. 9. For the capacitor in the scope of the first patent application, the above-mentioned multiple The depth of the recessed holes is between about 300 and 3000 Angstroms. 10. The capacitor according to item 1 of the scope of the patent application, wherein the rough surface in the plurality of 'cavities of the porous structure described above is engraved with hot phosphoric acid. 11 ' The capacitor according to item 1 of the patent application range, wherein the conductive layer includes at least a second doped polycrystalline silicon layer. 12. A memory capacitor including at least: a storage electrode on a semiconductor substrate, the storage electrode forming an electrical connection with a conductive region on the substrate, the storage electrode having a porous crusted stomach, please read the back, Note I: The paper size of the revised version is in Chinese National Standard (CNS) A4 format (210 X 297 mm) Α8 Β8 CS D8 Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 447115 6. The scope of patent application is porous The structure includes a recessed hole extending downward from the upper surface of the two electrodes, the plurality of recessed holes having a rough surface inside; a plurality of hemispherical dream particles on the side wall of the storage electrode; The wall has a recessed surface on the hemispherical dream particle core. A dielectric layer is on the porous structure, the storage electrode, and the plurality of hemispherical silicon particles; and a conductive layer is on the dielectric layer. 13. The capacitor according to item 12 of the patent application, further comprising a stacked silicon oxide layer and a silicon nitride layer between the storage electrode and the substrate β 14. The electric device according to item 12 of the patent application Wherein said electrode contains at least the storage of polysilicon doped. 15. The capacitor according to item 12 of the patent application, wherein the above-mentioned dielectric layer includes at least a silicon oxide-silicon nitride-silicon oxide stacked layer. 16. For the capacitor with the scope of patent application No. 12, in which the above dielectric layer is silicon oxide-silicon nitride, tantalum oxide, titanium oxide, PZT 'and BST among which " 〇17. For the scope of patent application No. 12 Capacitance, in which the above-mentioned plurality of hemispherical silicon particles are formed by plasma enhanced chemical vapor deposition method * The paper size is in accordance with China National Standard (CNS) A4 (2 丨 0 × 297 mm) 4 4 5 8 8 8 8 ABCD 6. Application for patent scope 18. For the capacitor with the scope of patent application No. 12, in which the thickness of the above-mentioned plurality of hemispherical silicon particles is between about 200 and 1000 Angstroms. The capacitor of 12 items, wherein the depth of the plurality of recesses is about 300 to 3000 angstroms. 20. The capacitor according to item 12 of the scope of patent application, wherein the rough surfaces in the plurality of recessed holes of the porous structure described above are formed by etching with hot phosphoric acid. 21. The capacitor according to item 12 of the patent application, wherein the aforementioned conductive layer includes at least a second doped polycrystalline silicon layer. J 3-pack ----------- ^-X '_'-. .V: y (please pay attention to ^ items before filling in this page) Staff of Central Bureau of Standards, Ministry of Economic Affairs Printed on a paper by a consumer cooperative, using China's national kneading rate (CNS) A4 (210X297 mm)