444403 A7 B7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 其電電導值 極壓極使 電但訊便 化晶厚配 B一 及 f 通種値輯 η]*電電閘會 種不資以 式電定述 置TS導一二邏 極種式茼 一此取， 程 C固上 配(J3之加述出 U厂閘此動電 至因讀高 可體有質 胞體同施上讀 1間用-浮之 接極來提 式晶具電 億 憶不須於而 1之制降此同 連電用可 子電種介 記 記個則介體 _區控壓由不 須極可度 電値一 一 之之二，壓晶 h道之電或種 不閛亦密。種一，第 化 化少訊電電 f 通體生中各 其式且裝率一有面在 式式至資此經 極和晶産極之。和制而封速述設側 ， 程 程之出，流 電極電間電極壓是控 ，之之描胞之中 可 可體讀極流 極電在之極電電此。行置路中億口口 式式晶中電電 閘極會.)_ 閛極通因的進配電64記凹凹 子 子電體極有 S 閘此 g 式閘導稱式之路高 5 一於此 1 蔭 1 電 電以晶閘否 .1用因 U 勤式之名動化電提 1 每接於 種之是電用是 a 制 。/'-浮動同之浮式求及1中郯置 一 主訊由制據10控壓 1 至浮不極是程力本件其區配 Ffi 關為資 了控依 t 之電 — 透。種電其種中成文，極質 有體，為之, 式體通 f 穿來各極，一術之利置汲電 或 是。.導中 C 體間 動晶導ί 子出有閘即制技上專配 \ 介 明法半S)存晶之 浮電之區電透體式，控SI程本胞極一 發方以^('儲電壓1,由在體道使穿晶動關來^製日億源第 本诰在RO來至電或藉置晶通可極電浮有用在低在記之之 製ΕΡ歷壓通 ο 配電和降電此 位可 降 之體度 ------τ--I--,ΙΛ -------—訂--------* {請先吼讀背®'之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4444 03 A7444403 A7 B7 V. Description of the Invention (The Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed its electric conductance, extreme pressure and extreme electricity, but the information is convenient. It is equipped with B and f general types.)] Based on the electrical specifications, the TS guide, two logic poles, and other methods are taken. Cheng C is fixed on the distribution (J3 plus the U plant gate. This power is applied to the high cell body and the plastid body. Read 1 with -floating terminal to lift the crystal device. The battery is not necessary, and the 1 system is not required. This is the same as the connection of the sub-type electricity. The mediator _ zone control voltage is not necessary. The electric power is one-two-two, and the electricity or the type of the h channel of the die crystal is not too sparse. The first one is that the Huahua Shaoxin electric power f has a variety of different types in the whole body and the installation rate is face-to-face. The poles and crystals are extremely polarized. In the process of making and sealing, the speed is described on the side. The process voltage is controlled by the current electrode, and the cocoa body reads the current in the cell. In the row of the road, the Yikou mouth-type crystal Zhongdian electric gate will be.) _ 閛 pole through the power supply and distribution 64 points concave sub-sub-electrode poles have S-gate This g-type gate guide type road is 5 high here 1 shade 1 electricity Electricity is based on the thyristor No.1. It is activated by the name of U-type. Electricity is a system each time it is connected. / '-Floating with the same floating system and a main signal system in 1 According to the 10 control voltage 1 to the floating pole is Cheng Li's part, which is equipped with the Ffi switch to control the electric power of the control t. The electric power is written in the book, the quality is physical, for this, the style body f f For each pole, you can draw electricity for the benefit of one operation .. In the middle of the C body, the crystal guide is made. When the brake is released, it is specially equipped in the manufacturing technology. The control side of the SI process will send the battery to ^ ('storage voltage 1, which will be turned off by moving the crystal through the body track. It is useful to make a low-memory system of ep calendar pressure through power distribution and power reduction. This position can be reduced to -------- τ--I--, ΙΛ --------- order --- ----- * {Please read the precautions of “Read Back®” before filling out this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 4444 03 A7
I B7_ 五、發明說明（2 ) 置一種浮動式閘極電梗，其上配置第二介電質且再其上 則配置一種控制用閘極電極。由於在凹η邊緣處之電場 變形現象，則雖然第一介電質有均勻之厚度但在寫入資 訊時電子只穿透至凹口之上部邊緣。在寫入時電子穿透 至凹口之下部邊緣。在此二種倩況下電子穿透於源極/ 汲極區和浮動式閘極電極之間。待別是有以下之缺點： 由源極/汲極區及浮動式閘極電極形成一種電容。特別 此種電容會使切換速率變慢且使程式化電壓變大。源極 /汲極區分別具有一種高摻雜之部份及低摻雜之部份（其 配置在高摻雜部份之下方）。為了産生源極/汲極區區， 則須在凹口産生之前藉由植入法産生第一摻雜層且藉由 磊晶法（Epitaxy)而度生第二摻雜層。源極/汲極區是 在産生此凹口時藉由此二層之結構化而産生。源極/汲 極區之高摻雜之部份鄰接於凹口之上部邊緣，源極/汲 極區之低摻雜之部份鄰接於凹口之下部邊緣。 在US5486714中描逑一種電子式可程式化之記億胞配置 ，其電晶體之源極/汲極區配置在凹口之互相面對之二個 側面之上部。電晶體之通道區是U形的且沿箸此二値側面 及沿著此二個側面及沿箸凹口之底部而延伸。藉由此種 配置方式，則在較高之封裝密度時可達到一種較長之通 道長度。浮動式閘極電極鄰接於凹口之4個Μ面及底部 。在通道區中此凹口設有熱生長之第一介電質》為了減 -4 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 11---1訂·------— 嘩· 經濟部智慧財產局員工消費合作社印製 A7 4444 03 B7 五、發明說明（3 ) 〈請先閱讀背面之注意事項再填寫本頁) 少電容（其是由浮動式閛極電極和通道區所形成），則在 凹口之二個刨面上之第一介電質較凹口底部上者略厚。 在#除資訊時電子只穿透至凹口之底部。在浮動式閛極 雷極上方配置一種控制式閘極電極，其藉由第二介電質 而與浮動式閫極電極相隔開。控制式閘極電極是字元線 之一部份，其垂直於源極/汲極區之間的連接線而延伸 浮動式閘極電極在凹口外部重疊於基板之表面上。源 極/汲極區中之一經由一値接觸區而與位元線相連接。 其缺點是由：由於一部份較厚之第一介電質，因此只有 非常小之讀出電流可供使用。 本發明之目的提供一種電子式可程式化之記億胞配置 ,可避免上述之缺點。此外，本發明亦提供此種.電子式 可程式化之記億胞配置之製造方法。 經濟部智慧財產局員工消費合作社印製 此種目的是藉由一種電子式可程式化之記憶胞配置來 逹成，其中在基板中配置記億胞，記憶胞含有一痼平面 式電晶體。在電晶體之通道區上方配置第一介電質。在 第一介電質上方配置一種浮動式閘極電極。浮動式閘極 電櫥具有一値下部，此下部鄰接於第一介電質。此外， 浮勖式閛極電極具有一 ί固側面部份，其配置在浮動式蘭 極電極下部之邊緣上。此種側面部份和浮動式閘極電極 之下部形成一種厚度均勻之層，使得浮動式閘極電極之 側而部份之水平尺寸等於浮動式閘極電極下部之垂直尺 寸。浮動式閘極電極之側面部份之上部平面所在位置因 此較浮動式閘極電極下部之上部平面還高。浮動式閘極 一 5 一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4444 03 A7 B7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 區介極 平電 胞産記之，U 對極，字Ρ上二置 極這 極一一電 部極 億上個口極 ί 須閘質條凹部第配 電。 汲 極 上閘 記面一凹電-4,且式電此二底生份 極伸 / 閘 之式 之表 C 一極動介使第之産部。閘延 極置用 卩動 化之體第閘ai中浮二且生 口須一區式中 源配制 ♦浮 式板晶在式a口之第線産凹。此道動向 之上控 下於 程基電少動 —凹胞生元中二區之通浮方 體極,°極直 可在式至浮«一億産字板第極接之使直 晶® 極 電垂 式須面。種 第記而生基在汲鄰髖而垂 電電 極寸 子中平用一t入同極産在 。\ 相晶份在 較極極 閛尺 電其有使生 Μ填不電深極區電部亦 置閲閛 式直 種，具供産.丨不使極極接樣源極此面面 位式用 動垂。一成別以須rm但，閘電連一之汲作側界 在動制 浮。伸由達分口 .：fo面化式極相口 體 \ 用之的 所浮控 與伸延藉來胞凹質on側構動閘極凹晶極合極間 面在種。種延而是法億一電(C各結浮用電一電源適電之 平。一接一中面的方記第介形之行由制極第生與且極極 部高置連在而平目生些痼一共口進。控閘與産之方閘電 上還配相是平部述産這一第以凹料開種用是而板下式極 之面上線寸之上上之，生生須 一材隔 | 制上法基口 動閘 部平其元尺行之，用胞産産中第性相生控本入使凹浮用 下部且字平平部外所億須上程蓋電互産與基植 ，一 於制 極上質與水相下此置記胞部過覆導極上線.其由口第由控 電之電是 而極 配生億底此便此電其元，藉凹於 和 ------r---— I 裝 il — i— 訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4444 03 經濟部智慧財產局員工消費合作社印製 A7 B7_ 五、發明說明（5 ) 樣可使電容（其由浮動式閘極電極和控制用閘極電極所 形成）變大而不會使記億胞配置之封装密度變小。若此 穉電容較大，刖這樣是有利的，因為電子可在較低之操 作電κ時達成穿透作用。 相較於U S 5 4 8 β 7 1 4而言，本發明之通道區不是U形的 而是平坦的，-此外，不只在記億胞拭除資訊時而旦在寫 入眘訊時電子會由通道區穿透而出或穿透至通道區中。 由於本發明之通道區較U S 5 4 8 6 7 1 4中者還小.則為了降低 由通道區和浮動式閘極電極所形成之電容此第一介電質 不必有一呰較厚之位置。第一介電質珂具有一種均勻之 厚度，這樣在産生記億胞配置時可減少製程上之費用。 由於源.極/汲極區較浮動式閘極電極下部之上部平面 還深，則可能存在之電容（其形成於源極/汲極區和浮 動式閘極電極之間）是可忽略的，使此種電子式可程式 化之記億胞配置具有一種持別快之切換速率，因此就其 程式化而言只需很小之程式化電壓。若源極/汲極區之上 部平面位於浮動式閛極電極之下部平面之下，則此種電 容待別小C. 比種電晶體基本上就像傳統上配置在基板表面上之平 而式電晶體一樣的方式來構成·· 通道區是平坦的且配置在二痼源極/汲極區之間。第 一介電質（'其用作閘極介電質）具有一種均勻之厚度。由 浮動式閘極電極（其用作閘極電極）和源極/汲極區所形 成之電容是可忽略的。 -7 - 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） ------------}-裝--------訂--------I (請先閱讀背面之注意事項再填寫本頁) 444403 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 6 ) 若 第 二 凹 P 和 第 凹 P 同 樣 深 1 則 源 極 / 汲 極 區 之 上 部 平 面 在 浮 動 式 閘 極 電 極 之 下 部 平 面 之 下 0 就 像 産 生 傳 統 平 面 式 電 晶 體 時 —* 樣 源 極 / 汲 極 區 疋 在 閛 極 電 極 産 生 之 後 f 産 生 0 因 此 » 電 子 式 可 程 式 化 之 記 億 胞 配 置 或 蓮 輯 電 路 之 周 邊 之 平 面 式 電 晶 體 可 同 時 與 記 憶 胞 之 電 晶 體 起 産 生 > 這 表 示 —> 種 製 程 上 之 簡 化 〇 藉 由 第 — 凹 P 之 産 生 而 使 基 板 之 - 部 份 被 去 除 Ϊ 這 樣 可 使 基 板 和 浮 動 式 閘 極 電 極 之 間 的 電 容 大 大 地 降 低 0 此 外 第 二 凹 可 藉 由 傳 統 平 面 式 電 晶 體 用 之 典 型 能 量 (即， 摻雜用之離子之典型能量範圍） 來 進 行 之 植 入 法 而 在 正 確 的 位 置 中 産 生 源 極 / 汲 極 區 〇 利 用 此 種 平 面 式 棺 入 法 相 對 於 深 入 式 植 入 法 而 言 可 達 成 一 種 尖 鋭 之 摻 雜 物 質 外 型 (P Γ 0 f i 1 e )， 使源極/汲極區在與浮動式閘極 電 極 直 接 相 鄱 之 處 産 生 而 不 會 污 染 通 道 區 0 % 垣 樣 即 可 使 電 晶 體 具 有 特 別 低 之 電 阻 C 因 此 以 和 第 —11 凹 Π 相 同 之 深 度 來 産 生 第 二 凹 P 〇 下 述 情 況 是 有 利 的 ； 若 基 板 具 有 —* 種 摻 雜 層 I 其 鄰 接 於 基 板 之 表 面 且 其 攘 雜 物 質 濃 度 較 其 下 方 之 基 板 部 份 還 高 低 〇 洹 樣 在 進 行 蝕 刻 過 程 以 産 生 第 —* 凹 P 和 第 二 凹 η 時 卽 可 辨 認 ; 何 時 可 到 達 基 板 之 位 於 摻 雜 層 下 方 之 之 此 部 份 t 苴- W—程 -gjr可-在- 此- 種 深 —度 ¥ 止 a 第 一 凹 P 和 第 二 凹 P 具 有 相 同 之 深 度 且 切 割 此 摻 雜 層 〇 若 摻 雜 物 質 濃 度 之 間 的 差 別 越 大 1 則 越 容 易 辨 認 何 時 到 逹 基 板 之 位 於 摻 雜 層 下 方 之 此 部 份 〇 由 於 通 道 區 曰 疋 基 板 之 位 於 摻 雜 層 下 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 >= 297公釐） -----Ί — I —裝—I---f 訂-------—^ly (請先閱讀背面之注意事項再填寫本頁) 4444 03 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（) 方之此部份的一部份且較佳是具有一種介於1 0 i7 c m-3和 5 X 1 0 d c nr3之間的低的摻雜物質濃度，則摻雜層具有 較高之摻雜物質濃度（例如，介於5 X 1 0 17 c nr3和5 X 1 0 E c nr3之間）是有利的。但摻雜層之摻雜物質濃度亦 可小於通道區者，，擦雜層之摻雜物質的導電型式較佳是 餌通道區者相反。但通道區和摻雜層亦可具有相同之導 電型式。 若控制式閘極電極不是一部份配置在浮動式閛極電極 之制面部份之與浮勖式閛極電極相遠離之外部側面上， 刖隔離結構配置在源極/汲極區上方是有利的，隔離結 構之上部平面至少和浮動式閛極電極之側面部份之上部 平而一樣高。此種隔離結構可遮住導電性材料。否則在 浮動式閙極電極和導電性材料之間會形成一種電容，這 會使切換速率變慢。 隔離結構可鄰接於浮動式閘極電極。 為了産生這呰隔離結構，須沈積一種絶緣材料且將之 整平言至字元線裸露為止。這些隔離結構之上部平面在 此種情況下和字元線之上郃平面一樣高。 本發明之範圍包活：在浮動式閘極電極之側面部份之 外部邊緣和這些隔離結構（或隔離區）之間設置一種由絶 緣材料所構成之間隔層（s p a C e r )。此種間隔層較佳是在 第一介電質産生之前即已産生。於是在産生第一凹口之 後沈積一種絶緣材料且進行回蝕刻，以便在第一凹口側 而上商生該間隔層。然後第一介電質可藉由熱氣化作用 ™ 9 一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------I la- — — — — — — II ^ --------- ί請先晛讀背卧之注意事項再填寫本頁) 4444 03 經濟部智慧財產局員工消費合作社印製 A7 B7_ 五、發明說明（s ) 而産生，使第一介電質在第一凹口中只産生於底部上。 這®間隔層然後又可被去除。 為了去除這呰在産生第一凹口時在通道區中所産生之 蝕刻殘渣，則在第一介電質産生之前進行一種熱氣化作 用是有利的目.因此而可使所産生之氧化物隨後即被去除 間隔曆在去除氣化物時可保護各隔離區，:， 為了簡化製程旦使封裝密度提高，則控制用閘極電極 是字元線之一部份時是有利的。 各記億胞之第一凹口 .可互相連貫而形成一種溝渠。 各記億胞之第一凹口較佳是互相隔開，因為相互隔開 之浮動式閛極電極卽能以自動對準（即，不需使用可對 準之遮罩）之方式而産生於第一凹口中c·此外，可提高 此種由浮動式閘極電極和控制用閘極電極所形成之電容 ,這是因為浮動式閘極電極可覆蓋較大之面積，5第一凹 口例如具有4値側面，而第一凹口可只具有二値側面以 作為溝渠之一部份。為了以自我對準之方式來産生浮動 式閙極電極，則浮動式閘極電極之導電性材料須以異向 性（an iso tropic)方式在與基板表面相垂直之方向中去 除茛至導電性材料之一部份（其位於第一凹口之外部）被 去除為lh 這例如可ϋ由化學-機槭式之拋光法來逹成·： 亦可以異向性方式來對此導電性材料進行回蝕刻。為了 防It第一凹口底部上之材料因此而被去除，則本發明之 範圍亦包括：以另一種材料埴入第一凹口中，此種材料 在回蝕刻時可倮護此浮動式閘極電極之位於第一凹口底 -1 0 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------r-----裝--------訂"i — — ！· (請先閱讀背面之注意事項再填寫本頁) 444403 A7 ___B7五、發明說明（9 )I B7_ V. Description of the Invention (2) A floating gate electric stem is provided, and a second dielectric is disposed thereon and a gate electrode for control is disposed thereon. Due to the deformation of the electric field at the edge of the recess η, although the first dielectric has a uniform thickness, electrons only penetrate to the upper edge of the recess when writing information. Electrons penetrate to the lower edge of the notch during writing. Under these two conditions, electrons penetrate between the source / drain region and the floating gate electrode. It has the following disadvantages: a capacitor is formed by the source / drain region and the floating gate electrode. In particular, this type of capacitor will slow down the switching rate and increase the programmed voltage. The source / drain regions each have a highly doped portion and a lowly doped portion (which are disposed below the highly doped portion). In order to generate the source / drain region, a first doped layer must be generated by implantation and a second doped layer must be generated by epitaxy before the recess is created. The source / drain region is created by this two-layer structure when this notch is created. The highly doped portion of the source / drain region is adjacent to the upper edge of the notch, and the less doped portion of the source / drain region is adjacent to the lower edge of the notch. In US5486714, an electronically programmable battery cell configuration is described. The source / drain region of the transistor is arranged on the two sides of the notch facing each other. The channel region of the transistor is U-shaped and extends along the two sides and along the two sides and along the bottom of the notch. With this configuration, a longer channel length can be achieved at higher package densities. The floating gate electrode is adjacent to the four M faces and the bottom of the notch. In the channel area, this notch is provided with the first dielectric of thermal growth. "In order to reduce -4-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back first) (Fill in this page again.) 11 --- 1 Orders ---------- Wah · Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 4444 03 B7 V. Invention Description (3) 〈Please read the notes on the back first (Fill in this page again) Low capacitance (which is formed by the floating electrode and the channel area), the first dielectric on the two planing surfaces of the notch is slightly thicker than the one on the bottom of the notch. When the information is removed, the electrons only penetrate to the bottom of the notch. A control gate electrode is disposed above the floating dynode, and is separated from the floating dynode by a second dielectric. The control gate electrode is part of the word line, which extends perpendicular to the connection line between the source / drain regions. The floating gate electrode overlaps the surface of the substrate outside the recess. One of the source / drain regions is connected to the bit line via a stack of contact regions. The disadvantage is that because of the thicker first dielectric, only a very small read current is available. The purpose of the present invention is to provide an electronic programmable memory cell configuration, which can avoid the disadvantages mentioned above. In addition, the present invention also provides a manufacturing method for such an electronic programmable battery configuration. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. This purpose is achieved through an electronically programmable memory cell configuration, in which a billion cells are arranged in a substrate, and the memory cell contains a flat-type transistor. A first dielectric is disposed above the channel region of the transistor. A floating gate electrode is disposed above the first dielectric. The floating gate cabinet has a lower portion, which is adjacent to the first dielectric. In addition, the floating type electrode has a solid side portion, which is arranged on the lower edge of the floating type blue electrode. This side part and the lower part of the floating gate electrode form a layer of uniform thickness, so that the horizontal size of the side and part of the floating gate electrode is equal to the vertical size of the lower part of the floating gate electrode. The position of the upper plane of the side portion of the floating gate electrode is therefore higher than the upper plane of the lower portion of the floating gate electrode. Floating gate 1 5 This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 4444 03 A7 B7 V. Description of the invention (Printed by Jieping Pingdian, Consumer Cooperative, Intellectual Property Bureau, Ministry of Economic Affairs It is written by the cell, U counter pole, two poles on the word P, one pole on the pole, one pole on the pole, and the power distribution on the concave part of the brake strip. A concave electricity on the gate surface of the drain electrode -4, and Table C of the two-element raw pole extension / gate type C. The first pole moves the production department. The gate extension pole is placed with the automatic body. The gate ai is floating in the middle, and the raw mouth must be prepared by one-zone Zhongyuan. The floating plate crystal is recessed on the second line of the mouth of the type a. This movement is controlled by the Cheng Jidian and moves less-the floating floating pole of the second area in the concave cell cell, the pole can be straight to the floating «The first pole of the 100-million-character plate is connected to the Straight Crystal® Electrode Vertical Whisker Surface. This kind of recorder is based on the electrode adjacent to the hip and the electric electrode is inserted into the same pole in one t. \ Phase The crystals can be used for production in the electrode department of the deep pole area, which can make the electrode fill the electric pole in the deeper area, and it is for production. 丨 Do not use the pole electrode to sample the source surface. Vertical. Do not need to be rm, but the brake and electric power is used as a side boundary in the floating system. Extending by up to the mouth .: Fo surface type polar phase port body \ The borrowed floating control and extension are borrowed On the cell concave side, the gate-concave pole-electrode interface is planted. The seed extension is equivalent to one billion electricity (C each junction floats electricity and a power source is suitable for electricity. One by one in the middle of the side The trip of the metamorphosis consists of the first generation of the poles and the high poles are connected to the top of the poles. The flat gates are opened together. The control gate and the square gate of the production are also electrically matched with the first phase of the production. This kind of application is on the upper surface of the plate-type pole, and the product must be separated by a material | The upper part of the moving gate of the method is made by its own ruler. The lower part of the concave and floating part is covered by the electric power generation and planting, which is covered by the outer part of the word flat part. Once the electrode topography and water phase are covered, the cell is overlaid with the lead. It is controlled by the power of the mouth. Yes, it ’s a perfect match, so it ’s worth it, and it is recessed and ------ r ----- I install il-i-- order --------- (Please read the back first Please note this page, please fill in this page) This paper size applies Chinese National Standard (CNS) A4 Grid (210 X 297 mm) 4444 03 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7_ 5. Description of the invention (5) Sample capacitor (which is formed by floating gate electrode and control gate electrode) Make it larger without reducing the packaging density of the megacell configuration. If this 穉 capacitor is large, 刖 this is advantageous, because electrons can achieve penetration at lower operating κ. Compared to US 5 In terms of 4 8 β 7 1 4, the channel area of the present invention is not U-shaped but flat. In addition, not only when the information is recorded by the billion cells, but the electrons will penetrate the channel area when the caution is written. And out or penetrate into the channel area. Since the channel region of the present invention is smaller than the one of US 5 4 8 6 7 1 4, in order to reduce the capacitance formed by the channel region and the floating gate electrode, the first dielectric does not need to have a thicker location. The first dielectric material has a uniform thickness, which can reduce the manufacturing cost when generating a billion-cell configuration. Since the source / drain region is deeper than the plane above the lower portion of the floating gate electrode, the possible capacitance (which is formed between the source / drain region and the floating gate electrode) is negligible. This kind of electronically programmable memory cell configuration has a very fast switching rate, so only a small programming voltage is required in terms of its programming. If the upper plane of the source / drain region is located below the lower plane of the floating 电极 electrode, this capacitor should be small. The transistor is basically like a flat type traditionally arranged on the substrate surface. The transistor is constructed in the same way. The channel region is flat and is arranged between the source / drain regions. The first dielectric ('which acts as a gate dielectric) has a uniform thickness. The capacitance formed by the floating gate electrode (which is used as the gate electrode) and the source / drain region is negligible. -7-The size of this paper is applicable to the National Standard (CNS) A4 (210 X 297 mm) ------------}-Packing -------- Order --- ----- I (Please read the notes on the back before filling this page) 444403 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (6) If the second concave P and the concave P are equally deep 1 then the upper plane of the source / drain region is below the lower plane of the floating gate electrode 0 like when a traditional planar transistor is produced— * sample source / drain region f is generated after the 电极 electrode is generated 0 Therefore »The electronically programmable planar cell configuration or peripheral circuit of the lotus circuit can be generated simultaneously with the memory cell transistor > This means— > the simplification of the process. — The concave P is generated and the-part of the substrate is removed. This can greatly reduce the capacitance between the substrate and the floating gate electrode. 0 In addition, the second recess can be used to generate a source / drain region in the correct position by implantation using the typical energy of a conventional planar transistor (ie, the typical energy range of the doped ion). Compared with the in-depth implantation method, this planar coffin method can achieve a sharp doped material appearance (P Γ 0 fi 1 e), so that the source / drain region is in direct contact with the floating gate electrode. The 0% sample generated at the point where it does not contaminate the channel area can make the transistor have a particularly low resistance C. Therefore, it is advantageous to generate the second depression P at the same depth as the -11th depression 〇 The following situation is advantageous; If the substrate has-* kinds of doped layers I, which are adjacent to the surface of the substrate and whose impurity concentration is higher or lower than the portion of the substrate below it, an etching process is performed to produce the first-* concave P and the second concave η Time identifiable; Ho This part of the substrate that can be reached below the doped layer t 苴-W-process-gjr can-in- this- kind of depth-degree ¥ aa The first concave P and the second concave P have the same depth and cut This doped layer. If the difference between the dopant concentration is greater, it is easier to identify when the part of the ytterbium substrate is located below the doped layer. Paper size applies to China National Standard (CNS) A4 specification (210 > = 297 mm) ----- Ί — I — 装 —I --- f Order -------— ^ ly (please first Read the notes on the back and fill in this page) 4444 03 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description () Part of this part and preferably has a type between 1 0 i7 c m-3 and 5 X 1 0 dc nr3 low dopant substance concentration, the doped layer has a higher dopant substance concentration (for example, between 5 X 1 0 17 c nr3 and 5 X 1 0 E c nr3) is advantageous. However, the doping material concentration of the doping layer may be smaller than that of the channel region. The conductivity type of the doping material of the doping layer is preferably the opposite of the bait channel region. However, the channel region and the doped layer may have the same conductivity type. If the control gate electrode is not partly arranged on the outer side of the surface of the floating 电极 electrode and away from the floating 閛 electrode, the 刖 isolation structure is arranged above the source / drain region. Advantageously, the plane of the upper portion of the isolation structure is at least as high as the plane of the upper portion of the side of the floating electrode. This isolation structure can shield the conductive material. Otherwise, a capacitance will be formed between the floating electrode and the conductive material, which will slow down the switching rate. The isolation structure may be adjacent to the floating gate electrode. In order to create this isolating structure, an insulating material must be deposited and leveled until the word lines are exposed. The upper planes of these isolation structures are in this case as high as the planes above the word lines. The scope of the present invention includes the following: a spacer layer (s p a c e r) made of an insulating material is provided between the outer edge of the side portion of the floating gate electrode and the isolation structures (or isolation regions). Such a spacer layer is preferably produced before the first dielectric is produced. An insulating material is then deposited after the first notch is created and etched back to produce the spacer layer on the side of the first notch. Then the first dielectric can be made by thermal gasification ™ 9 A paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------- I la- — — — — — — II ^ --------- ί Please read the precautions for lying on your back before filling out this page) 4444 03 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7_ V. Description of the invention (s ), So that the first dielectric is generated only on the bottom in the first recess. This ® spacer layer can then be removed again. In order to remove the etching residue generated in the channel region when the first notch is generated, it is advantageous to perform a thermal gasification before the first dielectric is generated. Therefore, the generated oxide can be subsequently That is, the removed interval can protect each isolation region when removing gaseous substances. In order to simplify the manufacturing process and increase the package density, it is advantageous when the control gate electrode is part of the word line. The first notch of each billion cell can be connected to each other to form a ditch. The first notches of each billion cell are preferably spaced from each other, because the spaced-apart floating electrode electrodes can be generated in an automatic alignment (ie, without the need for an alignable mask). In the first notch, c. In addition, the capacitance formed by the floating gate electrode and the control gate electrode can be increased. This is because the floating gate electrode can cover a larger area. It has a 4 値 side, and the first notch may only have a 2 値 side as part of the trench. In order to generate a floating 閙 electrode in a self-aligned manner, the conductive material of the floating gate electrode must be anisotropic in an direction perpendicular to the surface of the substrate to remove the buttercup to conductivity. A part of the material (which is located outside the first notch) is removed as lh. This can be formed, for example, by a chemical-mechanical maple polishing method: This conductive material can also be made anisotropically. Etching back. In order to prevent the material on the bottom of the first notch from being removed as a result, the scope of the present invention also includes: inserting another material into the first notch, which can protect the floating gate when it is etched back The electrode is located at the bottom of the first notch-1 0-This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------ r ----- installation ------ --Order " i-! · (Please read the notes on the back before filling this page) 444403 A7 ___B7 V. Description of the invention (9)
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(_請先閱讀背S·之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 444 4 03 ____B7_ 五、發明說明（1Q ) 離區之後須産生一種輔助層。在産生第一凹口時，輔助 層須對應於條形之遮罩以條形方式而被結構化，使隔離 區之一部份裸露出來，輔肋層在去除浮動式閘極電極-和 另一材料（其偽棺入第一凹口中）之導電性材料時作為蝕 刻停出靥用。然後對該另一材料進行回蝕刻，直至其在 隔離區，_h方之部份被去除為止。然後選擇性地對該另一 材料而對上述導電性材料進行回蝕刻，直至隔離區裸露 為lh 由導電性材料而産生浮動式閘極電極。該另一材 料然後被去除。字元線在産生第二介電質之後才産生， 此藓程中須沈積導電性材料且將之整平直至輔肋層裸露 為！.1：字元線是條形的且具有一呰外翻區（其可到達第 一凹口中）。字元線由上方重簦於隔離區。 較佳是該另一材料可選擇性地對這些隔離區而被蝕刻 。這些隔離區例如含有S i 0 2且該另一材料例如是由光 漆所構成 字元線之導電性材料例如由慘雜之多晶矽所溝成。為 了提高宇元線之導電性，多晶矽可以較高導電性之材料 (例如，金靨或金屬矽化物，例如，T i S ί 2 )來覆蓋。字 元線之導電性材料可含有金屬或金屬矽化物。 若字元線以自我對準之方式産生，則以熱氣化作用而 産生此種覆蓋上述控制用閘極電極時整®字元線是由遮 覃所覆蓋，-. 若記億胞配置具有一種NAND -結構（architecture), 刖這樣是有利的。在N A N D -結構中，垂直於字元線而相 -1 2 - 本紙張尺度適用ΐ國國家標準（CNS)A4規格（210 X 297公釐） ------------裝---I ----訂 -------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4444 Oa A7 __B7_五、發明說明（U ) 鄱之各記億胞是串聯的且形成一條位元線。 經濟部智慧財產局員工消費合作社印製 垂極相線區摻 汲晶産之輯後側側生源雜 式 之 {S汲値元極低 \ 電在胞邏然之之産之攮。。圖 區 二 \ 二位汲。 極各。億或 。口極而體低份緒據 離 則極在使/份 源之的記邊份凹電入晶之部或依 隔 ，源置時極部 之邊利各周部二極檀電區的\將 和3-高之配同源之 體固有生及之第閘次之極雜及下 渠-1 提同別且各雜 晶之是産以雜在之二路汲摻矽以 溝 度共分流..摻 電路樣便份摻便體第雷 / 高有例 生 密個口 電是低 之雷這以部低以晶由輯極之含施：産 裝一H漏式種 胞輯刖，的之，電藉邏源區可實明在 封有二!h方一 億邏，入雜區刻各。或使極如之説 使具第防之及 記或時植摻極蝕之Γ)邊，汲例明單圖 了 胞下了 利份 各詈生次低汲回路ce固份 \ 板發簡1 為億況為有部。若配産 一之 \ 行電pa及部極基本式第 記情 則之區 朐同第區極進輯(S以的源 圖 之種。，雜道 億共行極源且邏層，雜繞 此 鄰此間性摻通 記區進汲之料或隔體摻圍 。 相在之電高於 此極後 \ 體材邊間晶低上 圖 而 。口 導種接 與汲之極晶緣周它電之面 視 線的凹之一鄰 間 \ 口源電絶在其之區側 俯 元利一高有份 時極凹之各種及生胞極在 。 之 字有第較具部 區源二體之一以産億汲份 述 板 於是之有別之 區之第晶路積上上記 \ 部 詳 基 直區鄱具分雜 極體生電電沈面面各極的 來 後 ------------^]. ----—---訂—I----— C請先酊讀背®·之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 Γ4444 03 Α7 ___ Β7 1 ο 五、發明說明（） 外.亦顯示一種由光漆所構成之條形之遮罩。 第2 a圈 在産生一層輔肋層，第一凹口，間隔曾，第 -介電踅，浮動式閘極雷極和第一隔離結構之後基板之 错切而。 第2 b圖 在第2 a圖之各步驟之後此基板之與第2 a圖之 橫切而相锯直之橫切面。 笔3圖 在去除第一隔離結構且産生第二介電質，控 制用閛極電極和遮罩之後第2圖之橫切面。 第4 _ 在産生第二Μ 口，源極/汲極區之低摻雜的 部份，其它間隔餍和源極/汲極區之高摻雜的部份之後 第3圖之橫切而。 笔5 a圖 在産生第二隔離結構之後第4圖之橫切面。 第5 b圖 在第5 a圖之各步驟之後第1圖之俯視圖。 這呰圖式未依比例繪製。 在此奮施例中，基板S由矽構成。基板S具有一層η -掇雜層ί).其鄰接於基板S之表面0且其摻雜物質濃度 是〗0 13 c nr3。基板S之位於此慘雜層D下方之部份W a是 P -攆雜的目.所具有之摻雜物質濃度大約是1 0 17 c nr3 (第 2 a和2 h圖）. ..摻雜層D大約3 0 0 n m厚，其下方之部份W a大 约3 00 nm厚。 然後藉助於光漆所構成之第一遮覃（未顯示）而産生一 些互相平行而延伸之溝渠G。其可切割該摻雜層D c·溝渠 G大約5 0 0 n ni深。去除此種由光漆所構成之第一遮罩。 藉由沈積一種厚度大約是500ntn之Si02且以化學-機槭 -14- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------ 裝 ί--- 訂·--ϊ 11-- (請先閱讀背^之注意事項再填寫本頁> 444403 A7 B7 五、發明說明（ 13 隔 些 一 生 産 中 G 渠 溝 在 而 止 為 露 裸 ο 而 表2b 至和 言 1 光第 抛 T 式區 方離 是 約 大 度 寛 之 Ϊ 區 翻 隔 些 這 G 圖 是 是 約約 大大 離度 距厚 之稹 間沈 π 後 相然 0Κ 種 1 生 産 便 以 矽 化 氮 之 第 圖 其 圖 1 第 /fv P 章 遮 二 第 之 成 棱 漆 光 由 之 形 條 S <:·. Η 方 層肋 肋薛 輔 區2C 離是 隔約 於大 1 離 垂 钜 -3. 形之 條間 是 約 大 度 寬 伸 延 而 區 離 隔 對 地 性 擇 選 互輔 相此 且對 ntE來 下凹 D i 層第 雜生 摻産 於可 位即 之間 S 之 板 ΐ 基區 至離 直隔 刻在 蝕 ο 一7fc /-Λ— r— 進為 S 露 板裸 基ya 和份 S β Η ώα 層之 肋方 Ρ 第 和 圖 度 厚 積 沈 後 然 0 Ρ 罩 遮 二 第 之 成 構 所 漆 光 由 Γ-3·-· 0 此 除 去 一㉟熱 除 第 b 種 在* 一 便}0行 以圖進 ,2 須 刻 a 中 0 ^程 行瞧過 進層此 且隔 C 矽間渣 化之殘 氮述匆 之上蝕 η 生之 1.0産上 是上部 約而底 大 M y 之 11 MV 口 凹 Ρ 用 作 化 氧 (+請先閱讀背©-之注意事項再填寫本頁) 裝--------訂----- ο Π 物凹 化 i 氣第 熱在 之而 生用D1 産作質 所化電 除氣介 去熱 一 後由第 隨 _ 之 a厚 第 画 約 大 生. 産 上 部 底 之 經濟部智慧財產局員工消費合作社印製 吧摻罾 共W化 以 t 由 後 w 籍 然 n c Π阳 次光 同之 ί 0 之 η 肋 輔 至 直 η ο 夕 2 圮 5 約晶 約大多 大度及 度厚阻 厚積光 積沈除 沈上去 式其來 方，光 m)矽拋 ΟΓ晶式 nf多械 C0之機 /1. J 隹 0 口2Ϊ第 凹約生 一 大産 第至而 於刻阻 位蝕光 之回由 阳 行 。 光進阻 和阻光 矽光在 晶對存 多後再 使然不 便。方 以除上 ， 去 I [h被區 為份離 露部隔 裸之使 fls部， 層外深 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4444 03 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 隔離結構Π ,其配置在第一凹口中（第2 a和2 b圖）。 由多晶矽而産生浮動式閘極電極G f ,此過程中例如以 H R r來對多晶矽谁行回蝕刻，直至隔離區I之未被輔助 雇H S所覆蓋之部份裸露為止（第2 a和2 b圖）。第一隔離結 構Π因眈用來保護浮動式閘極電極G f之下部，G f之下部 所具有之厚度和浮動式閜極電極之側面部份之寬度相同。 然後例如以C F 4來去除第一隔離結構I 1。 産生第二介電質D2以作為ΟΝΟ層，此過程中須沈積厚度 大約1 0 r, m之氮化矽旦氮化矽之一部份須被氣化（第3圖） 為了産生控制用閛極電極g k (其是宇元線y之一部份） ，刖須沈積厚度大約2 0 0 n m之同次摻雜之多晶矽且藉由 化學-機槭式拋光法而整平直至輔肋層H S裸露為止。字 元缩W因此以自我對準之方式垂直於隔離區]而産生且 位於第一凹口 V 1上方（第5 b圖）。 藕由熱氣化作用而使字元線W之一部份被氧化，字元 線W因此可由遮覃Μ所覆蓋（第3圖）。 然後例如以熱Η 3 Ρ 0 4來去除該輔助層H S。 為了産生第二凹口 V 2 (其分別配置於二阔相鄰之第一 凹口 VI之間以及二個相鄱之隔離區I之間），則須選擇 件地對遮罩Η和隔離區I來對基板S進行蝕刻直至基板 S之位於禊雜層D下方之此部份Wa裸露為止。第二凹口 V 2因此具有第一凹口 V 1相同之深度ί第4圖）。利用此種 步驟可完令去除該摻雜層D。 藉由以η -揍雜之離子來進行之植入法而在第二凹口 V 2 -1 6 - 本紙張尺度適用f國國家標準（CNS)A4規格（210 X 297公釐） 11----- 1----裝 ----— II 訂·！--- (請先閱_讀背6之注意事項再填寫本頁) 4444 03 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 之底部上産生各電晶體之源極/汲極區之低摻雜的部份 L (第4圖）。 然後沈稽厚度大約是3 Ο η 1C之S i 0 2且進行回蝕刻，使 笔二凹口 V 2之側而上産生其它間隔層S p 1 (第4圖）。 韃由以η -揍雜之離子來進行之另一檀入法而在第二凹 口 V 2之底部上産生源極/汲極區之高摻雜之部份H ,其 制而是由源極/汲極區之低撻雜之部份L所圍繞（第4 圖）,， 然後沈穑厚度大約3 0 0 n m之S i 0 2且藉由化學-機械式 抛光法而整平，直至字元線Ιί裸露為止。Si02與其它 間隔層S P ’ 一起形成第二隔離結構I 2 , I 2配置於電晶體 之源極/汲極區上方（'第5 a圖）。 基板S之此一部份（其配置在二個源極/汲極區之間 目.位於第一凹口 VI下方）作為電晶體之通道區ka用。二 阔分別垂直於字元線W而相鄰之電晶體分別佔有一個共 同之源極/汲極區。垂直於字元線W而相鄰之各電晶體 是串聯相接巨形成一種位元線。 所産生之電子式可程式化之記億胞配置具有一種NAND-結構Λ每一記億胞之空間需求大約是4 F 2 ,其中F是以 所使用之技術可製成之最小之結構大小，F在本實施例 中之值是200nm。 本實施例可有許多變型，其同樣在本發明之範圍中。 上述各層，凹口和間隔層之大小因此可嵌據各別之需求 來調整。同樣情況亦適用於摻雜物質濃度以及各種材料 -17- ----- Ί-----^ *------- (請先閱'讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 五、發明說明（ 16 A7 B7 雜· 摻- Π 是 以 可 區 道 通 而 的 雜 0 I Ρ 是 以 可 區 極 汲 ,\ 取極 撰源 之的 種接 一 連 有相 具線 可元 置位 ΊΟ UU.· Ρδϋ uTK 胞是 憶區 記極伸 之汲延 ih\ 而 式極線 稃源元 可之字 式體於 子晶苜明 爾電垂説 揮各線之 構位符 ο 些 這Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, M. The second source of the recession is the second source. Pingkou septum < 1 Littan area is used in pairs. . Various shapes and billions of people can be in the middle-one or two cover each other, 4 more isolated pole control hoods to create jppj strips from the area where they are separated from each other, some are absorbed in the production of the delay, some belong to the , Every other. One . Yu shape li is in the ditch. It must be lined in? Sira, and this can be connected to the gap. If you set some poles, you will enter the line so that the same canal is adjacent to (1- Matching this source, raw board, and yuan and this # 200 million and the middle Mizoguchi to help iL compared, the production baseline is high between words, heavy, and the notation board some concavities and convulsions to improve the yuan In the description, some of the bases can be exogenously used, and Kou Ping Yi Er is used to characterize the direct line of the siblings. This plantation is based on the fact that the first part of the mouth is written as the first production area. The origin of the biochemical off-loading area in the fH one can be described above as the word above, which is borrowed from the production, and the second channel can be separated by oxygen production, so that the mouth can be compatible, and the interval is the same. Hot styles make the neighbors away, and the straight and straight lines of the distance are connected. The two-line shields from this side and some separated lines are more prolonged from the separated areas. We need to separate the yuan, and we must leave the canal to be more accurate than the yuan. Cheng, the line of the word in the word requires some canals to separate the grooves. A little bit away from each other The second character of the eclipse of Lizi is the second one of this eclipse. This is the second edge of the eclipse. The second edge is on the ground. Since then, there is a ######################### The mouth is drawn from Yansheng and goes straight in between, π electricity chose t as the hM mouth on each pole of the plaque, and the reason for the vertical plate of the production area is to open the pole, and the mouth is to be separated from the mouth of the source. The base area can be separated after the gate ------ T ----- installation -------- order --------- bee. (_Please read the back S · 之Note: Please fill in this page again.) This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) A7 444 4 03 ____B7_ 5. Description of the invention (1Q) An auxiliary layer must be created after leaving the zone. In a notch, the auxiliary layer must be structured in a stripe manner corresponding to the stripe mask, so that a part of the isolation area is exposed, and the auxiliary rib layer is removing the floating gate electrode-and another material ( The pseudo-coffin is used as an etching stop when the conductive material is used. Then, the other material is etched back until it is in the isolation area, and the _h part is removed. Then selectively To One material is used to etch back the conductive material until the isolation region is exposed as lh. The floating gate electrode is generated from the conductive material. The other material is then removed. The character line is not formed until the second dielectric is generated. In this process, a conductive material must be deposited and leveled until the auxiliary ribs are exposed as! .1: the character line is stripe and has a valgus area (which can reach the first recess). The element line is re-emphasized to the isolation areas from above. Preferably, the other material can be selectively etched to the isolation areas. These isolation areas contain, for example, Si 02, and the other material is composed of, for example, varnish. The conductive material of the word line is formed of, for example, miscellaneous polycrystalline silicon. In order to improve the conductivity of the U-ray wire, polycrystalline silicon can be covered with a highly conductive material (for example, gold tin or metal silicide, for example, T i S ί 2). The conductive material of the word line may contain a metal or a metal silicide. If the character line is generated in a self-aligned manner, the thermal control is used to cover the above-mentioned control gate electrode. The character line is covered by the cover. NAND-architecture, which is advantageous. In the NAND-structure, it is perpendicular to the character line and phase-1 2-This paper size applies the national standard (CNS) A4 specification (210 X 297 mm) ------------ --- I ---- Order ------- Line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4444 Oa A7 __B7_ V. Description of the invention ( U) Each of the billion cells is connected in series and forms a bit line. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The vertical source line area is mixed with the crystal source of the rear side of the source and the source is a hybrid type {S 値 値 元 极低 \ Electricity is the product of cell logic. . Figure area two \ two digits. Very different. Billion or The mouth is very low, the body is very low, and the pole is in the part of the electrode, or separated from the source. When the source is set, the edge of the pole is located in the two poles of the two poles. It is inherently related to the 3-high-matching homologous body, and the first order is extremely heterogeneous and the lower channel-1 is different from each other, and the heterogeneous crystals are produced by the heterogeneous two-channel dip-doped with silicon and shunted by the groove. .The circuit sample is mixed with the body of the thigh / the high density of the case is a low thunder. This is based on the low and low crystals. It contains: an H leak type cell, and The source area of the telegraph by logic can be seen as sealed! There are two hundred million logics in each side, each of which enters the miscellaneous area. Or let it be said that it has the defense of the time, or the time of planting with the 蚀) edge of the polar eclipse, and the example of the example shows the lower part of the circuit, the lower part of the circuit, the solid component, and the board. For the state of the Ministry. If the production of the first line of the power line and the basic style of the first chapter is different from the first series of the series (the source map of the seed.), There are a total of 100 million polar sources and logical layers, mixed around The adjacent material is filled with the material or the spacer. The phase electricity is higher than this pole. \ The edge of the material edge is lower than the picture above. The seeding is connected with the edge of the pole crystal. One of the concavities in the surface of electricity is adjacent to one another \ The mouth source electricity must be on the side of its area. When Yuan Liyi has a high share, all kinds of concavities and cells are present. The zigzag has one of the two most detailed sources. Based on the output of 100 million yuan, the first crystal road product of the different area is described above. The detailed area of the base is equipped with a heteropolar body and an electric current sink surface .-------- ---- ^]. ----—--- Order—I ----— C Please read the precautions before reading this page and fill in this page.) This paper size applies to China National Standard (CNS) A4. Specifications (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy Γ4444 03 Α7 ___ Β7 1 ο 5. Description of the invention () In addition, a strip-shaped mask made of light paint is also displayed. Loop 2a After a layer of auxiliary ribs, a first notch, a gap, a -dielectric chirp, a floating gate lightning rod, and a first isolation structure are cut off the substrate. Fig. 2b After each step of Fig. 2a, the cross-section of the substrate cross-cut with Fig. 2a is straight. Figure 3 Figure 2 is a cross-section of Figure 2 after removing the first isolation structure and generating a second dielectric, control electrode and mask. 4_ After the second M port is generated, the low-doped portion of the source / drain region, other spacers, and the highly-doped portion of the source / drain region are generated after the cross-section of FIG. 3. Figure 5a. Cross-section of Figure 4 after the second isolation structure was created. Figure 5b Top view of Figure 1 after the steps of Figure 5a. The diagram is not drawn to scale. In this embodiment, the substrate S is made of silicon. The substrate S has a η-doped layer)). It is adjacent to the surface 0 of the substrate S and its doping concentration is [0 13 c nr3]. The portion Wa of the substrate S below the miscellaneous layer D is the target of P-doping. It has a dopant concentration of about 1017 c nr3 (Figures 2a and 2h) .. Doping The impurity layer D is about 300 nm thick, and the portion Wa below it is about 300 nm thick. Then by means of the first shade (not shown) formed by the varnish, a plurality of trenches G extending parallel to each other are generated. It can cut the doped layer D c · ditch G to a depth of about 50 n n. Remove the first mask made of such varnish. By depositing a Si02 with a thickness of about 500ntn and using chemical-mechanical maple-14- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------ Packing --- Order · --Ϊ 11-- (Please read the precautions on the back ^ before filling in this page> 444403 A7 B7 V. Description of the invention (13 G Gutters are only exposed in some productions, and Table 2b to He Yan 1 The light-throwing T-type area is about the distance between the large and small areas. The G area is separated by some G. The figure is about the large distance and the thick space is settled. After that, the 0K species 1 is produced by silicon silicide. Figure 1 Figure 1 / fv P Covering the 2nd section of the prismatic lacquered light strip S <: .. Η Square layer ribs Xue Fu area 2C is separated by about 1 big from the vertical 3-. The space between the strips is approximately broadly extended, and the separation is ground-to-ground selection. They complement each other and recess the Di layer for ntE. The second layer is intermixed with the slab base area of the S. Immediately etched in the etch ο a 7fc / -Λ— r— into the exposed bare ya and S β Ηα α of the ribbed layer of the first layer After the thickness is thick and thick, 0 Ρ covers the second structure, the light is from Γ-3 ·-· 0. This removes the heat and removes the b type in *. ^ Cheng Xing has looked at the residual nitrogen that is slagging between the silicon and silicon. The 1.0 is produced on the top and the bottom is large. The 11 MV cavity P is used for oxygenation (+ Please (Read the precautions of the back ©-and then fill out this page) Install -------- Order ----- ο 凹 凹 i i 第 第 热 热 生 生 生 D D D D D 1 1 1 1 1 1 1 1 1 1 1 D 质 D 所 电 电 电 电After the air is removed, it will be drawn by the first _ of a thick and thin picture. It is printed by the employee ’s consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, which is mixed with a total of t and then by w. Same as ί 0 η ribs to straight η xi 2 圮 5 Most of the crystals are large and thick, thick, thick, thick, thick, thick, light, thick, thick, light, thick, light, deep, and so on. The light is m. The machine of C0 / 1. J 隹 0 口 2Ϊ The recess is about to produce a large amount of product, and the resistance of the etched light is returned by the sun. The light advancement resistance and the light-blocking silicon light are not allowed after the crystal pairs are stored. Poop. In addition to the above, go to I [h the area as a part of the exposed part to separate the fls part, the depth of the outer layer of this paper applies the Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 4444 03 A7 B7 Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau. 5. Description of the Invention () The isolation structure Π is arranged in the first notch (Figures 2a and 2b). The floating gate electrode G f is generated from polycrystalline silicon. In this process, for example, HR r is used to etch back the polycrystalline silicon until the part of the isolation area I that is not covered by the auxiliary employment HS is exposed (2a and 2). b)). The first isolation structure Π is used to protect the lower portion of the floating gate electrode Gf. The thickness of the lower portion of Gf is the same as the width of the side portion of the floating gate electrode. The first isolation structure I 1 is then removed, for example with C F 4. A second dielectric D2 is generated as an ONO layer. During this process, a portion of silicon nitride silicon nitride with a thickness of about 10 r, m must be deposited (Figure 3). The electrode gk (which is part of the y-line) is deposited with the same doped polycrystalline silicon with a thickness of about 200 nm and leveled by chemical-mechanical maple polishing until the auxiliary rib layer HS is exposed. until. The character shrinkage W is thus generated in a self-aligning manner perpendicular to the isolation region] and is located above the first notch V 1 (Fig. 5b).藕 A part of the character line W is oxidized by thermal gasification, so the character line W can be covered by the cover M (Fig. 3). The auxiliary layer H S is then removed, for example, with hot Y 3 P 0 4. In order to generate the second notch V 2 (which is respectively disposed between two wide adjacent first notches VI and between two adjacent isolation regions I), it is necessary to select a pair of masks and isolation regions. I to etch the substrate S until the portion Wa of the substrate S below the doped layer D is exposed. The second notch V 2 therefore has the same depth as the first notch V 1 (Fig. 4). With this step, the doped layer D can be completely removed. The second notch is V 2 -1 6 by the implantation method using η-doped ions.-This paper size applies the national standard (CNS) A4 specification (210 X 297 mm) 11-- --- 1 ---- Install -------- II Order! --- (Please read _ Read the 6 notes before filling out this page) 4444 03 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention description () The source of each transistor is generated on the bottom / Low-doped portion L of the drain region (Figure 4). Then the thickness of Shen Ji is about 3 0 η 1C S i 0 2 and etch-back is performed, so that another spacer layer S p 1 is generated on the side of the pen two notch V 2 (Fig. 4).鞑 Another doping method using η-doped ions produces a highly doped portion H of the source / drain region on the bottom of the second recess V 2, which is produced by the source The low / different part L of the pole / drain region is surrounded (Figure 4), and then S i 0 2 with a thickness of about 300 nm is flattened and leveled by chemical-mechanical polishing until The character line Ιί is bare. SiO2 and other spacer layers SP 'together form a second isolation structure I2, and I2 is disposed above the source / drain region of the transistor (' FIG. 5a). This part of the substrate S (which is arranged between the two source / drain regions and located below the first recess VI) is used as a channel region ka of the transistor. The two lines are perpendicular to the word line W and adjacent transistors each occupy a common source / drain region. The adjacent transistors which are perpendicular to the word line W are connected in series to form a bit line. The generated electronically programmable cell configuration has a NAND structure. The space requirement of each cell is approximately 4 F 2, where F is the smallest structure size that can be made using the technology used. The value of F in this example is 200 nm. There are many variations to this embodiment, which are also within the scope of the invention. The sizes of the above-mentioned layers, notches and spacers can therefore be adjusted according to individual needs. The same situation also applies to the concentration of doping substances and various materials -17- ----- Ί ----- ^ * ------- (Please read the 'Notes on the back side before filling in this page') This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm). 5. Description of the invention , \ Take the seeds of the polar origin one after another with the corresponding line can be set ΊΟ UU. · Ρδϋ uTK cells are the extension of the memory extension of the pole extension ih \, and the epipolar line is the source element can be zigzag style Crystal clover Minger Ding said the structure of each line ο some of this
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V 電 構極 層 .結閘 雜 .區 層 口離式 板摻面離渠助罩凹隔動 基Π-表隔溝輔遮：：浮 質 電 介 (請先閒讀背面之注音？事項再填寫本頁)V Electric structure electrode layer. Junction gate. Area layer open-type plate mixed with surface-drain channel-assisted recessed movable base Π-surface partition trench auxiliary cover :: aerosol dielectric (please read the note on the back first? Matters then (Fill in this page)
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UW 0 Κ 用線雜雜區 制元摻糝道 捽字低高通 極 電 極 閛 分 分 /1 /Ί 5. β. 0 ώα ή. 白 本紙張尺度適用中國國家標準（CNS)A4規格（2丨0>< 297公釐）UW 0 Κ Doped with low and high pass electrode electrodes in a hybrid system with a linear hybrid area system / 1 // 1 5. β. 0 ώα ή. The paper size applies to China National Standard (CNS) A4 specifications (2 丨0 > < 297 mm)