44294 7 經濟部中央標準局舅工消費合作社印製 A7 B7 五、發明説明（1 ) 本發明係有關於積體電路，如同步動態隨機存取記 憶體（S D R A Μ)中内部時脈信號與外部時脈信號之同步電 路，且特別是有關於一種可在外部時脈之單周期内將内 部時脈信號與外部時脈信號對齊之同步電路。 在習知積體電路中，大部分數位邏輯電路均屬於計 時同步循序邏輯電路（Clocked synchronous sequential logic)，且，外部系統時鐘通常是由輸入缓衝器接收，再 以内部緩衝器整形後重新驅動内部電路。因此，輸入緩 衝器及内部緩衝器的時間延遲會使内部時鐘及外部時鐘 彼此偏移，造成積體電路之傳遞信號與外部系統時鐘不 同步之現象。以SDRAM為例，這種偏移可能會使其最 小資料存取時間（Minimum data access time)花費至少兩 個周期之外部系統時鐘，不過若偏移得以去除，則最小 資料存取時間只需要一個周期之外部系統時鐘。 通常，兩個時序信號可以鎖相迴路（Phase locked loop，PLL)或鎖延遲迴路（Delay locked loop，DLL)同 步化 β T. Lee et al.在"A 2.5V Delay Locked Loop For An 18Mb » 500MB/s DRAM" » IEEE International Solid State Circuit Conference，Paper#FAl 8.6，p300，1994 中提 出的鎖相迴路及鎖延遲迴路需要50個周期以上之外部 系統時鐘才能得到同步的結果。又，由於内部時鐘需經 常啟動/關閉以控制積體電路之活動及功率消耗，因此 PLL及DLL需要50個外部系統時鐘周期以達同步實無法 快速關閉以保存功率。而這亦會在積體電路’如上述 本紙張尺度it用中國國家標準（CNS ) A4规格（210X297公t ) (讀先閱讀背面之注$項再填寫本頁) ;裝. 訂 經濟部中央橾隼局員工消費合作杜印製 4 429 4 7 A7 87 五、發明説明（2 ) SDRAM上造成意想不到之功率消粍。 有鑑於此，閂鎖式時脈同步延遲電路（CSD)與同步鏡 延遲電路（SMD)這兩種時脈同步電路便被提出。閂鎖式 時脈同步延遲電路，如τ. Saeki，H. Nakamura，J. Shimizu 之"A lps Jitter 2 Clock Cycle Lock Time CMOS Digital Clock Generator Based On An Interleaved Synchronous Mirror Delay Scheme" > Digest of Technical Paper-Symposium on VLSI Circuit 1 IEEE ’ 1997 係不於 第1圖。其中，輸入緩衝器10係用以接收外部系統時鐘 XCLK 5。輸入緩衝器10之延遲因數為山。輸入緩衝器 10的輸出15則是輸入固定延遲線20之第·-時序時鐘 X〇。固定延遲線20之延遲為山+(12，即第二延遲因數。 固定延遲線20之延遲通常由複數串連之反相器決定。反 相器之延遲則通常在10-20ps級。 固定延遲線20之輸出25係第二時序時鐘Χι且輸入 量測延遲線30。量測延遲線30包括複數延遲元件30a、 3〇b、、30x、…、30η，其通常是閘控移位暫存器各 級。每個延遲元件30a、30b、…、30χ、…、30η之輸 出35則連接至閂鎖陣列40。閂鎖陣列40具有複數平行 閂鎖40a、40b、...、40χ、…、40η。當來自量測延遲 線30之延遲信號對齊第一時序時鐘15之第二脈衝時’ 閂鎖40χ會觸發。 複數平行閂鎖40a、40b、…、40χ、…、40η之輸 出45係連接至可變延遲線5〇 ^可變延遲線50具有複數 5 本紙張尺度適用中國國家標準（CNS )八4規格（2HX297公麓） (請先閱請背面之注意事項再填寫本頁) '袈- -5 44294 7 經濟部中央標隼扃K工消費合作社印製 A7 _____ B7 五、發明説明（3 ) 串連延遲元件50a、50b、…、50x、 、u 喻 ·..、50η。第一時 序"is號15係是經由串連之延遲元件5〇a、 5〇x、.·.、50η傳遞至閂鎖4以選定之延遲元件5〇χ·。··可 變延遲線50之輸出55係第三時序信號&且輸入内部緩 衝器60。内部緩衝器60則放大、緩衝第三時序信號^ 以用於積體電路内部電路之傳輸。 u 内部緩衝器60之延遲設計為旬，如此固定延遲線 20之延遲恰為輸入缓衝器10及内部緩衝器的之延遲總 和。量測延遲線3 0之量測周期τ m係外部系統時鐘5周期 ^ck及第二延遲因數（d]+d2)之差〇即：Tm=i：ck-(di+cl2)。 量測周期τ m之決定時間為外部系統時鐘5之第—個 周期，而同步則發生在第二個周期。可變延遲線5〇係延 遲第一時序信號15量測周期、之時間，使内部時鐘iclk 65在啟動兩個周期後能與外部系統時鐘5同步。 另外，同步鏡延遲電路，如T.Saeki，H Nakamura， J. Shimizu 之”A 2.5ns cl〇ck access 25〇Mhz 356_ SDRAM with a synchronous mirror delay”，IEEE International Solid State Circuits Conference ， Petef#SP23_4，P.374-375，1996 則示於第 2 圖。其中， 外部系統時鐘105係輸入緩衝器11〇之輪入，而輸入緩 衝器110之延遲時間則設為第一延遲因數山。 輸入緩衝器110的輸出U5係第—時序信號乂〇且連 接至固定延遲線120。固定延遲線120的輸出ι25則自 本紙張尺度適用中國國家標率（CNS ) A4規格（2丨0X297公釐） (請先閱讀背面之注意事項再填寫本頁) 袈- 訂 ·"/> 44294 7 A7 B7 五、發明説明（4 ) — ~""" 第一時序信號χ0延遲第二延遲因數di+d2 ,藉以做為第 二時序信號Xj。 第二時序信號125係量測延遲線13〇之輸入。量測 延遲線130包括複數串連之延遲元件n〇a、13〇b、.、 130x、…、l3〇n。相似於閂鎖式時脈同步延遲電路，複 數延遲元件係閘控移相暫存器各級。各延遲元件n〇a、 130b、…、l30x、…、13〇n之輸出135則連接至轉移 閘陣列140。 轉移閘陣列140具有複數轉移閘14〇a、14〇b、..、 140x、…、140η。第一時序信號us則連接各轉移閘。 导延遲之第二時序信號135延遲至第二時序信號135之 第一周期對齊第一時序信號US之第二周期時，轉移閘 140x會觸發。而延遲之第二時序信號135便經由選定之 轉移閘140χ轉移至可變延遲線15〇。 經濟部中央榇準局員工消費合作社印製 可變延遲線150具有複數串聯之延遲元件15〇a、 150b、…、i5〇x、…、15〇n。各延遲元件 15〇&、 150b、’·’、i5〇x、…、i5〇n具有一輸出連接轉移閘14〇 之輸出145。當第二時序信號135之第一脈衝對齊第一 時序信號115 ，觸發之轉移閘14〇χ連接至延遲元件 150χ，使延遲之第二時序信號145經由可變延遲線Η。 轉移及延遲，藉以形成第三時序信號& 155。 第三時序信號155係内部緩衝器16〇之輸入。内部 緩衝器160則用以放大、緩衝、延遲第三時序信號155， 藉以形成内部時鐘165。内部緩衝器之延遲為第三延遲 本紙張尺度適用中涵 ；44294? A7 ___ B7 五、發明説明（5 ) ' 因數心’其能夠使内部時鐘155與外部系統時鐘ι〇5對 齊。 第3圖係說明閂鎖式時脈同步延遲電路及同步鏡延 遲電路用以同步内部時鐘ICLK 325與外部系統時鐘 xclk3〇o之方法。外部系統時鐘XCLK 3〇〇係接收並延 遲第一延遲因數330以形成第一時序信號χ〇 3〇5。第 —時序信號Χ03〇5則延遲第二延遲因數h以形成第二時 序信號XtSlO。第二延遲因數4335通常為第—延遲因 數及第五延遲因數^第四時序信號&及内部時鐘iclk 3 2 5間之延遲）的總和，即： 第二時序信號Xl 310係依序延遲至第一上升邊緣 312對齊外部系統時鐘χ c L κ 3⑽之上升邊緣地，藉以 產生第三時序信號&315。第二時序信號又门⑺及第三 時序信號Χ2 315以時間延遲則為量測延遲時間b 340 ^量測延遲時間ts 34〇係外部系統時鐘xclk如〇之 周期tctc與第二延遲因數335之差，即： t3=tck-t2 t3=tck-(t1+t5) 經濟部中央標準扃員工消費合作社印t ：---^-----' 裝— (請先閣讀背面之注Jt.!^項再填寫本頁) 第四時序信號X3 3 2 0則以可變延遲時間14 3 4 5延遲 第三時序信號得到。圖中，第四時序信號Μ。的上升 邊緣並未對齊外部時鐘XCLK3〇〇，且右货τ β m Α υ 1有第五延遲因數t5 350之偏移。 另外，内部緩衝器則放大、延遲第四時序信號&32〇 第五延遲因數t5 35〇,藉以形成内部時鐘iclk 325 1 本紙張尺度㈣U家縣（CNS ) A4規格（21()><297公£^ ----__ 442947 A7 B7 五、發明説明（6 ) 中，内部時鐘ICLK 325係對齊於外部時鐘3〇() ^ 美國專利5614845(MaSleid)中敘述—種時脈穩壓 器，其可以在每個時脈周期内提供兩個控制用之時序參 考牲號。這個穩壓器具有兩個相位偵測器及兩個相位對 準電路，分別用來對齊時脈之上升及下降邊緣以得到上 述時序參考信號。 美國專利5663W(Rumreich et al )中則描述一種時 脈重定時裝置，其利用延遲線之閃鎖輸出對齊視訊時脈 邊緣及視訊信號之水平同步信號，至於延遲線的輸出係 根據其對齊水平同步信號而選定。 經濟部十央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 另外，美國專利5488664(Ashuri)中亦揭露一種減低 偏移現象及調整同步化波形之積體電路。此電路中，同 步化波形係由數位·時間定義域轉換器產生，其通過移相 器及圖形暫存器輕合於同步延遲線及圖型唯讀記憶體。 而同步延遲線則根據參考信號產生複數㈣，使;抽頭 分別具有單位延遲時間並搞合於數位時収義域轉換 器。此電路包括微延遲校準電路、消除偏移之控制電路、 及延遲内插電路。微延遲校準電路耦合於同步延遲線及 消除偏移之控制電路。消除偏移之控制電路麵合於移相 器及延遲内插電路。而内插電路則接收數位時間定義域 轉換器之輪出、並進而輸出一消除偏移後之同步化波 形◊ 綜上所述’本發明之主要目的便是在積體電路中提 供同步於外部時鐘或時序信號之内部時鐘或時序_ ____ 9 本紙張纽賴巾_家縣（ A7 五、發明説明（7) 號。 本發明之另一個目沾θ a 時鐘或時序信號具有最電;;提供一與外^ 號。 里之内部時鐘或時序十 界發明的又 經濟部中央標準局員工消費合作社印製 似9的是將積體雷 與外部時序信號在外部時序信=時輸 為達上述及其他目的+周期内同步化。 w 的’本發明係提供—種時序H 同步電路，其具有輪入緩衝 予序乜讀 取W于電路，用來接收、绥 放大外部時序信號。輸入緩 _ €塔具有第一延遲因數 (P接收外部時序信號之延遲㈣）。另外， 電路則連接輸人緩衝子電路，縣㈣接收之外部時序 ^號第—延遲因數，藉以產生第—時序信號。又，第一 量測延遲線係連接U定延遲線以接收第—時序信號、量 測第時序仏號一周期之第一部分、及維持該周期第一 部分之量測◊而第二量測延遲線則連接固定延遲線以接 收第一時序信號、量測第一時序信號該周期之第二部 分、及維持該周期第二部分之量測。 此外’第一閂鎖陣列係連接第一量測延遲線以接收 該周期第一部分之量測並產生第一閂鎖信號。同時，第 一閃鎖陣列則連接第二量測延遲線以接收該周期第二部 分之量測並產生第二閂鎖信號。又，可變延遲線係連接 第一及第二閂鎖陣列以接收第一及第二閂鎖信號並根據 第一時序信號周期之第一及第二部分量測值（其小於該 第二延遲因數）調整其延遲時間〇且，可變延遲線亦同時 _____ 10 ) A4im ( 210X297^^7 請 先 聞 讀 背- iS 之 注 意" 事 項 再 !I f r 經濟部中央標準局員工消費合作社印製 4429 4 7 A7 --------—_— _B7 五、發明説明（8) 連接固定延遲線以接❿、延遲第一時序信號該可變延遲 線之延遲時間，用來產生第二時序信號。 另外，内部緩衝子電路則用來接收、緩衝、放大、 延遲第二時序信號第三延遲因數，藉以在積體電路中產 生與外部時序信號同步之内部時序信號。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式說明 第1圖係習知問鎖式時脈同步延遲電路之方塊圖； 第2圖係習知同步鏡延遲電路之方塊圖； 第3圖係習知將積體電路之内部時鐘與外部時鐘同 步方法之時序圖； 第4圖係本發明閂鎖式時序信號同步電路之方塊 圖；以及 第5圖係本發明同步内部時鐘及外部時鐘以消除偏 移方法之時序圖。 實施例 第4圖係本發明中邊緣觸發之閃鎖式時脈同步延遲 電路的方塊圖。其中，外部系統時鐘xclk 2〇5係送至 輸=緩衝器2H)。輸入緩衝器21〇基本上是由⑽⑽反 相器串連而成且設計具有第一延遲因數dl。輸入緩衝器 的輸出則是第-時序信號x〇215。第—時序信號 215係固定延遲線22〇之輸入。第二時序信號& 2乃則 本紙張尺度適财( CNS ) A4^ ------^-----:...、t-- (請先閲讀t·面之注t'事項再填寫本頁) 訂44294 7 Printed by the Central Standards Bureau, Ministry of Economic Affairs, Machining and Consumer Cooperatives. A7 B7 V. Description of the invention (1) The present invention relates to integrated circuits, such as the internal clock signal in the synchronous dynamic random access memory (SDRA M) and the external Synchronization circuit of clock signal, and more particularly, it relates to a synchronization circuit that can align internal clock signal with external clock signal in a single cycle of external clock. In the conventional integrated circuit, most of the digital logic circuits belong to Clocked synchronous sequential logic (Clocked synchronous sequential logic), and the external system clock is usually received by the input buffer, and then re-driven by the internal buffer shaping Internal circuit. Therefore, the time delay of the input buffer and the internal buffer will cause the internal clock and the external clock to shift from each other, resulting in the phenomenon that the signal transmitted by the integrated circuit is not synchronized with the external system clock. Taking SDRAM as an example, this offset may cause its minimum data access time to take at least two cycles of the external system clock, but if the offset is removed, the minimum data access time requires only one External system clock of the cycle. Generally, the two timing signals can be synchronized with a phase locked loop (PLL) or a delay locked loop (DLL). Β T. Lee et al. In " A 2.5V Delay Locked Loop For An 18Mb » 500MB / s DRAM " »IEEE International Solid State Circuit Conference, Paper # FAl 8.6, p300, 1994 The phase-locked loop and lock-delay loop proposed in 1994 require an external system clock of more than 50 cycles to obtain synchronized results. In addition, since the internal clock needs to be turned on / off frequently to control the activity and power consumption of the integrated circuit, the PLL and DLL require 50 external system clock cycles to achieve synchronization and cannot be shut down quickly to save power. And this will also be used in the integrated circuit 'as above-mentioned this paper size it uses the Chinese National Standard (CNS) A4 specification (210X297g t) (read the first note on the back before filling in this page); Consumer co-operation by the Bureau of Du Du Printing 4 429 4 7 A7 87 V. Description of the invention (2) Unexpected power consumption on the SDRAM. In view of this, two types of clock synchronization circuits, a latch clock synchronization delay circuit (CSD) and a synchronous mirror delay circuit (SMD), have been proposed. Latching clock synchronization delay circuit, such as τ. Saeki, H. Nakamura, J. Shimizu " A lps Jitter 2 Clock Cycle Lock Time CMOS Digital Clock Generator Based On An Interleaved Synchronous Mirror Delay Scheme " > Digest of Technical Paper-Symposium on VLSI Circuit 1 IEEE '1997 is not in Figure 1. The input buffer 10 is used to receive the external system clock XCLK 5. The delay factor of the input buffer 10 is mountain. The output 15 of the input buffer 10 is the first-sequence clock X0 input to the fixed delay line 20. The delay of the fixed delay line 20 is mountain + (12, which is the second delay factor. The delay of the fixed delay line 20 is usually determined by the inverters connected in series. The delay of the inverter is usually on the order of 10-20ps. Fixed delay The output 25 of line 20 is the second timing clock Xι and is input to the measurement delay line 30. The measurement delay line 30 includes a plurality of delay elements 30a, 30b, 30x, ..., 30η, which is usually a gated shift temporary storage The output 35 of each delay element 30a, 30b, ..., 30x, ..., 30n is connected to a latch array 40. The latch array 40 has a plurality of parallel latches 40a, 40b, ..., 40x, ... , 40η. When the delay signal from the measurement delay line 30 is aligned with the second pulse of the first timing clock 15, the latch 40χ will be triggered. The output of the plural parallel latches 40a, 40b, ..., 40χ, ..., 40η is 45 It is connected to the variable delay line 50. The variable delay line 50 has a plurality of 5. This paper size is applicable to the Chinese National Standard (CNS) 8-4 specification (2HX297). (Please read the precautions on the back before filling this page) '袈--5 44294 7 Printed by the Central Ministry of Economic Affairs, K Industrial Consumer Cooperative A7 _____ B7 V. Description of the invention (3) Delay elements 50a, 50b, ..., 50x,, u, ..., 50η are connected in series. The first timing " is number 15 is a delay element 50a, 5 connected in series 〇x, .., 50n are passed to the latch 4 to select the delay element 50x ... The output 55 of the variable delay line 50 is the third timing signal & and is input to the internal buffer 60. The internal buffer 60 amplifies and buffers the third timing signal ^ for transmission of the internal circuit of the integrated circuit. U The delay of the internal buffer 60 is designed to be ten, so the delay of the fixed delay line 20 is exactly the input buffer 10 and the internal buffer Sum of the delay. The measurement period τ m of the measurement delay line 30 is the difference between the external system clock 5 cycles ^ ck and the second delay factor (d) + d2). That is: Tm = i: ck- (di + cl2). The determination time of the measurement period τ m is the first period of the external system clock 5, and synchronization occurs in the second period. The variable delay line 50 delays the first timing signal by 15 measurement periods, Time, so that the internal clock iclk 65 can be synchronized with the external system clock 5 after starting two cycles. In addition, the synchronous mirror delay circuit, T. Saeki, H Nakamura, J. Shimizu, "A 2.5ns cl0ck access 25〇Mhz 356_ SDRAM with a synchronous mirror delay", IEEE International Solid State Circuits Conference, Petef # SP23_4, P.374-375, 1996 Shown in Figure 2. Among them, the external system clock 105 is the rotation of the input buffer 110, and the delay time of the input buffer 110 is set to the first delay factor mountain. The output U5 of the input buffer 110 is the first timing signal 乂 0 and is connected to the fixed delay line 120. The output ι25 of the fixed delay line 120 applies the Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) from this paper scale (please read the precautions on the back before filling this page) 袈 -Order · " / & gt 44294 7 A7 B7 V. Description of the invention (4) — ~ " " " The first timing signal χ0 is delayed by the second delay factor di + d2, so as to serve as the second timing signal Xj. The second timing signal 125 is an input of the measurement delay line 130. The measurement delay line 130 includes a plurality of serially connected delay elements noa, 130b,... 130x, ..., 130n. Similar to the latch-type clock synchronization delay circuit, the plurality of delay elements are stages of a gated phase shift register. The outputs 135 of the respective delay elements noa, 130b, ..., 130x, ..., 13n are connected to the transfer gate array 140. The transfer gate array 140 includes a plurality of transfer gates 140a, 14b, ..., 140x, ..., 140n. The first timing signal us is connected to each transfer gate. When the second delayed timing signal 135 is delayed until the first period of the second timing signal 135 is aligned with the second period of the first timing signal US, the transfer gate 140x is triggered. The delayed second timing signal 135 is transferred to the variable delay line 15 through the selected transfer gate 140x. Printed by the Consumers' Cooperative of the Central Economic and Technical Bureau of the Ministry of Economic Affairs. The variable delay line 150 has a plurality of delay elements 15a, 150b, ..., i50x, ..., 150n connected in series. Each delay element 15o &, 150b, '·', i50x, ..., i50n has an output 145 connected to the transfer gate 14o. When the first pulse of the second timing signal 135 is aligned with the first timing signal 115, the triggered transfer gate 140x is connected to the delay element 150x, so that the delayed second timing signal 145 passes through the variable delay line Η. Transfer and delay to form the third timing signal & 155. The third timing signal 155 is the input of the internal buffer 160. The internal buffer 160 is used to amplify, buffer, and delay the third timing signal 155 to form the internal clock 165. The delay of the internal buffer is the third delay. 44294? A7 ___ B7 V. Description of the invention (5) 'Factor of heart' It can align the internal clock 155 with the external system clock ι05. Figure 3 illustrates the method by which the latch-type clock synchronization delay circuit and the synchronous mirror delay circuit are used to synchronize the internal clock ICLK 325 and the external system clock xclk3o. The external system clock XCLK 300 receives and delays the first delay factor 330 to form the first timing signal X305. The first timing signal X0305 is delayed by the second delay factor h to form a second timing signal XtSlO. The second delay factor 4335 is usually the sum of the first delay factor and the fifth delay factor ^ the delay between the fourth timing signal & and the internal clock iclk 3 2 5), that is, the second timing signal Xl 310 is sequentially delayed to The first rising edge 312 is aligned with the rising edge ground of the external system clock χ c L κ 3⑽, thereby generating a third timing signal & 315. The second timing signal and the third timing signal X2 315 are measured with the time delay as the measurement delay time b 340 ^ The measurement delay time ts 34 0 is the period of the external system clock xclk such as 0 and the second delay factor 335 The difference is: t3 = tck-t2 t3 = tck- (t1 + t5) Central Standard of the Ministry of Economic Affairs 扃 Stamp of Consumer Cooperatives t: --- ^ ----- '装 — (Please read the note on the back Jt .! ^ Item, fill in this page again) The fourth timing signal X3 3 2 0 is obtained by delaying the third timing signal with a variable delay time 14 3 4 5. In the figure, the fourth timing signal M. The rising edge of is not aligned with the external clock XCLK3〇〇, and the right cargo τ β m Α υ 1 has an offset of the fifth delay factor t5 350. In addition, the internal buffer amplifies and delays the fourth timing signal & 32, the fifth delay factor t5 35, and thereby forms the internal clock iclk 325 1 paper standard ㈣U County (CNS) A4 specification (21 () > < 297 public pounds ^ ---- __ 442947 A7 B7 5. In the description of the invention (6), the internal clock ICLK 325 is aligned with the external clock 30 () ^ described in US patent 5614845 (MaSleid)-a kind of clock regulation It can provide two timing reference numbers for control in each clock cycle. This regulator has two phase detectors and two phase alignment circuits, which are used to align the rising and The falling edge to obtain the above-mentioned timing reference signal. U.S. Patent No. 5,663W (Rumreich et al) describes a clock retiming device, which uses the flash lock output of the delay line to align the video clock edge and the horizontal synchronization signal of the video signal. The output of the line is selected based on its aligned horizontal synchronization signal. Printed by the Consumer Cooperative of the Shiyang Standard Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) In addition, it is also disclosed in US Patent 5488664 (Ashuri) An integrated circuit for reducing the offset phenomenon and adjusting the synchronization waveform. In this circuit, the synchronization waveform is generated by a digital-time domain converter, which is lightly connected to the synchronization delay line through a phase shifter and a graphic register. And graphic read-only memory. The synchronous delay line generates a complex number based on the reference signal, so that the taps have a unit delay time and fit in the digital domain receiver. This circuit includes a micro-delay calibration circuit and eliminates bias. Shift control circuit and delay interpolation circuit. Micro-delay calibration circuit is coupled to the synchronous delay line and the control circuit to eliminate offset. The control circuit to eliminate offset is integrated with the phase shifter and delay interpolation circuit. And the interpolation circuit Then receive the rotation of the digital time domain converter and output a synchronized waveform after eliminating the offset. In summary, the main purpose of the present invention is to provide an external clock or timing signal in the integrated circuit. The internal clock or timing _ ____ 9 of this paper Nilai towel _ Jiaxian (A7 V. Invention Note (7). Another object of the present invention is θ a clock or timing signal Have the most electricity ;; Provide an and external ^ number. The internal clock or time sequence of the ten circles invented and printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs is like 9 is the integration of the integrated mine and external timing signals in the external timing signal = Time-lapse to achieve the above and other purposes + synchronization within a cycle. The invention of w provides a timing H synchronization circuit with a round-robin buffer pre-sequence reading from the circuit for receiving and amplifying external timing Signal. The input delay _ € tower has a first delay factor (P delay for receiving external timing signals). In addition, the circuit is connected to the input buffer subcircuit, and the external timing sequence received by the county is the first delay factor to generate the first -Timing signals. In addition, the first measurement delay line is connected to a U-determined delay line to receive a first timing signal, to measure the first part of a period of the first time sequence number, and to maintain the measurement part of the first part of the period, and the second measurement delay line Then, a fixed delay line is connected to receive the first timing signal, measure the second part of the period of the first timing signal, and maintain the measurement of the second part of the period. In addition, the 'first latch array is connected to a first measurement delay line to receive the measurement of the first part of the cycle and generate a first latch signal. At the same time, the first flash lock array is connected to the second measurement delay line to receive the measurement of the second part of the cycle and generate a second latch signal. In addition, the variable delay line is connected to the first and second latch arrays to receive the first and second latch signals and is measured according to the first and second portions of the first timing signal period (which is smaller than the second Delay factor) adjust its delay time 〇 And, the variable delay line is also _____ 10) A4im (210X297 ^^ 7 Please read and read back-iS's attention " matters again! I fr Ministry of Economic Affairs Central Standards Bureau Staff Consumer Cooperatives Printed 4429 4 7 A7 --------—_— _B7 V. Description of the invention (8) Connect a fixed delay line to connect and delay the first timing signal. The delay time of the variable delay line is used to The second timing signal is generated. In addition, the internal buffer sub-circuit is used to receive, buffer, amplify, and delay the second timing signal and the third delay factor, thereby generating an internal timing signal in the integrated circuit that is synchronized with the external timing signal. The above-mentioned objects, features, and advantages of the present invention can be more clearly and easily understood. A preferred embodiment is exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: Schematic description The first diagram is a conventional interlocking clock Blocks of Synchronous Delay Circuit Figure 2 is a block diagram of a conventional synchronous mirror delay circuit; Figure 3 is a timing diagram of a conventional method for synchronizing the internal clock of an integrated circuit with an external clock; Figure 4 is a latch-type timing signal synchronization circuit of the present invention And FIG. 5 is a timing diagram of a method for synchronizing an internal clock and an external clock to eliminate offset according to the present invention. Embodiment 4 is a block diagram of an edge-triggered flash-locked clock synchronization delay circuit in the present invention. Among them, the external system clock xclk 2 05 is sent to the input = buffer 2H). The input buffer 21o is basically formed by a series of unitary inverters and has a first delay factor dl. The output of the input buffer is the -timing signal x0215. The first-timing signal 215 is the input of the fixed delay line 22o. The second timing signal & 2 is the paper size of the paper (CNS) A4 ^ ------ ^ -----: ..., t-- (Please read t. (Please fill in this page again)
經濟部中央標準局員工消費合作社印製 ..4 429 4 7 A7 --------------B7 五、發明説明（9 ) - ~~ 疋由第時序化號215延遲第二延遲因數d 1 +<12以得 到。第二延遲因數dl+d2係第一延遲因數以及第三延遲 因數d2(内部緩衝器28〇之延遲）的總和。 第一時序信號χι 225係第一量測延遲線230之輸 入第一量測延遲線230包括複數串連之延遲元件 230a、230b、··.、230χ、…、230η。 外部系統時鐘XCLK 205之周期％分為兩部分。第 一部分τ3起自第一邏輯狀態（〇)升至第二邏輯狀態（丨）之 轉換，結束於第二邏輯狀態（1)降至第一邏輯狀態（〇)之轉 換。而第二部分T；b則起自第二邏輯狀態（丨）降至第一邏輯 狀態（0)之轉換，結束於第一邏輯狀態（〇)升至第二邏輯狀 態（1)之轉換。 第一量測延遲線230係正邊緣觸發之延遲線，由第 一時序仏號XD 215之上升邊緣啟動。上升邊緣係出現於 第一時序信號215由第一邏輯狀態（〇)轉換至第二邏 輯狀態（1)的時候。 第一量測延遲線230具有複數輸出235，其為負邊 緣觸發閂鎖陣列25〇之輸入。負邊緣觸發陣列25〇由複 數負邊緣觸發問鎖構成。當第二時序信號Χι225通過第 篆漸對齊第一時 灰偟盤X〇21S之下降邊緣。第一時序信號知2丨5之下降 邊緣係自第二邏輯狀態（1)至第一邏輯狀態（〇)轉換的時 候。當第一時序信號215的下降邊緣對齊第二時序信 號X〗225之上升邊緣時，負觸發閂鎖25〇x便被設定二 本纸浪尺度適用中國國家標準（CNS ) A4規格（2IOX 297公釐） (請先閱讀背面之注$項再填寫本頁) -裝- A7 B7 五、發明说明（10 ) 傳遞第一閂鎖 第一時序信號Χ〇 215係第二量測延遲線240之觸發 輸入，而第二時序信號X, 225則是第二量測延遲線240 之延遲輸入。第二量測延遲線240係負邊緣觸發延遲 線，因此，第一時序信號Χ〇215的下降邊緣會觸發第二 量測延遲線240動作。第二量測延遲線240係將第二時 序信號Χι 225經由各延遲元件240a、240b、…、 240x、...、240η 以傳遞。 當第二時序信 號Χ〇 215的，第二量渺延遲線中有一輸 出245是正確的。此時，正邊緣觸發閂鎖260(260a、 260b、…、260x、…、260η)之問鎖260x為第一時序信 號X。215之上升邊緣所觸發。而正邊緣觸發閂鎖260x 之觸發則產立第二閂鎖信遞265 > 經濟部中央樣準局員工消費合作杜印製 (請先閲讀背面之注意事項再填寫本頁) 另外，第二時序信號225係可變延遲線270之延 遲輸入。可變延遲線270具有複數串連之延遲元件 270a、270b、…、270x、...、270η。第一閂鎖信號 255 及第二閂鎖信號265則分別選擇延遲元件270χ及 270y。延遲元件270χ係置於可變延遲線270中使第二時 序信號X1 225延遲第四延遲因數τ44，即外部時鐘XCLK 205周期tck之第一部分％與第二延遲因數dl+d2的差。 即； l+d2) 第二閂鎖信號265則選擇延遲元件265以提供第三 13 本紙張尺度適用_國國家標準（CNS ) A4说格（210X297公釐） a 429 4*? 第 8710299: 號銳明I -五、發明說明：Tf:::::::::^r!3' I正ί-期月娜ιϋτ!Γ ^irULil 顏！ 經濟部智慧財產局員工消費合作社印製 一第—問鎖信號265則選擇延遲元件265以提供第 —夺序^號父2 275。延遲元件27〇x及27〇y間之延遲 疋件係用以延遲第二時序信號X, 225第五延遲因數 Td5而第五延遲因數則是外部時鐘XCLK 205周期 TCK之第—部分％與第二延遲因數dl+d2的差。即： xd5=tb-(dl+d2) 士可變延遲線的輸出係第三時序信號Χ2 275。第三 %序信號乂2 275為内部缓衝器280之輸入。内部緩衝 时280的輸出則是内部時鐘ICLK 285。内部緩衝器28〇 之延遲係第三延遲因數d2。故，自輸入缓衝器210輸 入至内部緩衝器2S0輸出之時間延遲總共有。Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs: 4 429 4 7 A7 -------------- B7 V. Description of the Invention (9)-~~ 疋 Delayed by No. 215 The second delay factor d 1 + <12 is obtained. The second delay factor dl + d2 is the sum of the first delay factor and the third delay factor d2 (the delay of the internal buffer 28). The first timing signal χι 225 is an input of the first measurement delay line 230. The first measurement delay line 230 includes a plurality of delay elements 230a, 230b, ..., 230x, ..., 230η connected in series. The cycle% of the external system clock XCLK 205 is divided into two parts. The first part τ3 starts from the transition from the first logic state (0) to the second logic state (丨), and ends at the transition from the second logic state (1) to the first logic state (0). The second part T; b starts from the transition from the second logic state (丨) to the first logic state (0), and ends at the transition from the first logic state (0) to the second logic state (1). The first measurement delay line 230 is a delay line triggered by a positive edge, and is started by the rising edge of the first timing sequence number XD 215. The rising edge occurs when the first timing signal 215 transitions from the first logic state (0) to the second logic state (1). The first measurement delay line 230 has a complex output 235, which is the input of the negative edge triggered latch array 25. The negative edge trigger array 25 is composed of a plurality of negative edge trigger interlocks. When the second timing signal X225 passes through the first to gradually align the first, the falling edge of the gray disk X021S. The falling edge of the first timing signal 21-5 is the time when the transition from the second logic state (1) to the first logic state (0) occurs. When the falling edge of the first timing signal 215 is aligned with the rising edge of the second timing signal X〗 225, the negative trigger latch 25 × x is set. The two paper wave standards are applicable to the Chinese National Standard (CNS) A4 specification (2IOX 297). (Mm) (Please read the note on the back before filling this page) -Installation-A7 B7 V. Description of the invention (10) Passing the first latch first timing signal X〇215 is the second measurement delay line 240 And the second timing signal X, 225 is the delay input of the second measurement delay line 240. The second measurement delay line 240 is a negative edge trigger delay line. Therefore, the falling edge of the first timing signal X0215 triggers the operation of the second measurement delay line 240. The second measurement delay line 240 transmits the second timing signal X 225 through the delay elements 240a, 240b, ..., 240x, ..., 240n. When the second timing signal X0 215, an output 245 in the second delay line is correct. At this time, the interlock 260x of the positive edge trigger latch 260 (260a, 260b, ..., 260x, ..., 260η) is the first timing signal X. Triggered by rising edge of 215. The positive edge trigger latch 260x triggers the creation of a second latch letter 265 > printed by the consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) In addition, the second The timing signal 225 is a delay input of the variable delay line 270. The variable delay line 270 has a plurality of delay elements 270a, 270b, ..., 270x, ..., 270n connected in series. The first latch signal 255 and the second latch signal 265 select the delay elements 270x and 270y, respectively. The delay element 270x is placed in the variable delay line 270 to delay the second timing signal X1 225 by a fourth delay factor τ44, that is, the difference between the first portion% of the period tck of the external clock XCLK 205 and the second delay factor dl + d2. That is, l + d2) the second latch signal 265 selects the delay element 265 to provide the third 13 paper sizes applicable _ National Standard (CNS) A4 grid (210X297 mm) a 429 4 *? No. 8710299: No. Ruiming I-V. Description of the invention: Tf ::::::::: ^ r! 3 'I 正 ί- 期 月 娜 ιϋτ! Γ ^ irULil Yan! Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The first-question-lock signal 265 selects the delay element 265 to provide the first-order sequence number 2 275. The delay element between the delay elements 270x and 270y is used to delay the second timing signal X, 225 the fifth delay factor Td5 and the fifth delay factor is the first part of the external clock XCLK 205 cycles TCK and the first The difference between the two delay factors dl + d2. That is: xd5 = tb- (dl + d2) The output of the variable delay line is the third timing signal X2 275. The third% sequence signal 乂 2 275 is the input of the internal buffer 280. The output of the internal buffer 280 is the internal clock ICLK 285. The delay of the internal buffer 280 is the third delay factor d2. Therefore, there is a total time delay from the input of the input buffer 210 to the output of the internal buffer 2S0.
Tdt〇t:=dl+(dl+d2)+x4+x5+d2 /ccit〇t==dl+(dl+d2)+Ta-(dl+d2)+Tb-(dl+d2)+d2Tdt〇t: = dl + (dl + d2) + x4 + x5 + d2 / ccit〇t == dl + (dl + d2) + Ta- (dl + d2) + Tb- (dl + d2) + d2
Xdtot = ^a + Tb 如此’内部時鐘ICLK 285可在外部時鐘XCLK 205 之單一周期内與外部時鐘XCLK 205同步。 第5圖係說明同步内部時鐘ICLK與外部時鐘 XCLK之方法。外部時鐘XCLK係接收及緩衝第一延 遲因數t,以形成第一時序信號X，在這個方法中，緩 衝時序信號X。的下降邊綠fe〇及上升邊緣reG係用以 觸發所有邊緣敏感（edge sensitive)的延遲線及閂鎖。 第一時序is號X〇則延遲第二延遲因數q。第二延遲因 數tz係以輸出緩衝電路設計為第一延遲因數及第五延 遲因數之總和。外部時鐘XClk周期TcK具有第一 14 私紙張尺度適用令國國家標準（CNS)A4規格（2】〇 X 297公楚） (請先閱讀背面之注意事項再填寫本頁) VA--------Xdtot = ^ a + Tb In this way, the internal clock ICLK 285 can be synchronized with the external clock XCLK 205 in a single cycle of the external clock XCLK 205. Figure 5 illustrates the method of synchronizing the internal clock ICLK with the external clock XCLK. The external clock XCLK receives and buffers the first delay factor t to form a first timing signal X. In this method, the timing signal X is buffered. The falling edge green fe0 and rising edge reG are used to trigger all edge sensitive delay lines and latches. The first timing is number X0 is delayed by the second delay factor q. The second delay factor tz is an output buffer circuit designed as the sum of the first delay factor and the fifth delay factor. The external clock XClk cycle TcK has the first 14 private paper standards applicable to the national standard (CNS) A4 specifications (2) 0X 297 Chu (Please read the precautions on the back before filling this page) VA ----- ---
五、發明說明（i2 ) 邓分％及第二部分％。通常，、二％ = (1/20cK。但本發明 亦可以用於具有不平均周期比（uneven duty cycle)的時 脈L號，亦即：τ〆^且T；a+1：b=i：CK。第一部分、係外部時 鐘XCLK周期τ(：κ中第二邏輯狀態（1)之部分。.第二部 分、則是外部時鐘XCLK周期Tck中第一邏輯狀態（〇) 之部分。第二時序信號X!係延遲時間t3直到其上升 邊緣rei對齊第一時序信號X。之下降邊緣feQ，如此便 可量測外部時鐘XCLK周期Tck之第一部分、與第二延 遲因，的時間差t3，亦即：tnt2。 第二時序信號\係延遲時間t4，直到其下降邊緣 .1對齊第時序彳s號X0的上升邊緣re0。時間t4係 第外部時鐘XCLK周期tck第二部分xb與第二延遲因 =之時間差，亦即：〖4=τ〆2。第二時序信號&則延遲 時間及％以產生第三時序信號X2。第三時序信號 X2係緩衝、放大、延遲第五延遲因數t5以形成内部 時鐘ICLK。内部時鐘ICLK則傳輸至積體電路之内 部電路中β 雖然本發明已以較佳實施例揭露如上，然其並 非用以限定本發明，任何熟習此項技藝者，在不脫 離本發明之精神和範圍内，當可作更動與潤飾，因 此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 1 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --線· 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 杜 印 製5. Description of the invention (i2) Deng cent% and second part%. Generally, two% = (1 / 20cK. But the present invention can also be used for clock L numbers with an uneven duty cycle, that is: τ〆 ^ and T; a + 1: b = i : CK. The first part is the part of the second logic state (1) in the external clock XCLK cycle τ (: κ .. The second part is the part of the first logic state (0) in the external clock XCLK cycle Tck. The second timing signal X! Is a delay time t3 until its rising edge rei aligns with the falling edge feQ of the first timing signal X. In this way, the time difference t3 between the first part of the external clock XCLK cycle Tck and the second delay factor can be measured. , That is: tnt2. The second timing signal \ is a delay time t4 until its falling edge. 1 is aligned with the rising edge re0 of the timing 彳 s number X0. Time t4 is the second part of the external clock XCLK cycle tck xb and the second The time difference of the delay factor =, that is: 〖4 = τ〆2. The second timing signal & then delay time and% to generate a third timing signal X2. The third timing signal X2 is a buffering, amplifying, and delaying a fifth delay factor t5 to form the internal clock ICLK. The internal clock ICLK is transmitted to the integrated circuit Β in the internal circuit Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make changes and decorations without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. 1 X 297 mm) (Please read the notes on the back before filling this page) Cooperative Du Printing