TW442941B - Transistor structure with electrostatic discharge protection ion implantation and the fabricating method of the same - Google Patents

Abstract

This invention proposes a transistor that has high electrostatic discharge tolerance capability and its fabricating method. This transistor includes a gate structure, a drain region and a source region. This gate structure is set on the well region surface of the first conduction type on the substrate. The drain region and the source region are set on the well region surface and are individually adjacent to the gate structure. The drain region includes the first protection region with the second conduction type and the first highly doped region with the second conduction type. The first protection region with the second conduction type is set on the surface of well region and is adjacent to the gate structure. The first highly doped region with the second conduction type is set on the surface of well region. The depth of the first protection region is deeper than that of the first highly doped region. The concentration of the first protection region is lighter than that of the first highly doped region. Part of the first protection region is overlapped part of the first highly doped region. The transistor of this invention is provided with the following advantages, such as elimination of LDD tip structure, discharging through the well region and having the same breakdown voltage of drain region as that of source/drain of the ordinary device.

Description

Tv 4 429 4 1_, V. Description of the invention (1) The present invention relates to a transistor structure and a manufacturing method thereof, particularly a transistor structure having a good electrostatic discharge protection effect and a manufacturing method thereof. With the progress of process technology, electrostatic discharge (ESD) has become one of the main considerations for the reliability of integrated circuits (1C). In particular, after the semiconductor process technology has entered the deep submicron regime, scaled-down transistors and thinner gate oxide layers have lower ESD tolerance. Therefore, in the IC I / O ports must be equipped with esd protection circuits to protect the components in the IC from ESD damage. In the output port (output buff er), the n-type metal-oxide-semiconductor (NM0S) and P-type metal-oxide-semiconductor (PM0s) with negative output are generally designed with large component sizes so that NM0S and PM0S have Sufficient drive current to drive external loads. Large-sized components are likely to withstand greater power. Therefore, generally, the NM0S and PM0S of the output port are directly used as electrostatic discharge protection components. FIG. 1A is a schematic diagram of an output port with an LDD structure, and FIG. 1B is a photomask layout diagram of FIG. 1A. In the industry, NMOS often uses lightly-doped drain (LDD) structures to prevent hot electrons generated by high electric fields from damaging the gate oxide layer. Figure U and Figure 2 both contain two NMOSs, which are located on a p-type well area 12. Each NMOS includes a gate structure 14, a source region 8 and a drain region 16. The non-electrode region 16 is coupled to the input and output bonding pads 20, and the source region 18 and the well region 12 are both coupled to the power port vss. LD]) structure provides the drain region

'* ι · 4 42 9 4 ^ V. Description of the invention (2) 16 There is a peak structure under the gate structure, as shown in the N-doped region in Figure 1A. When an ESD event with a positive pulse relative to the power port vss occurs on the bonding pad 20, the ESD current first flows into the drain region 16 through the contact of the drain region 16. Because the LDD tip structure in the drain region 16 is closest to the source region 18, the ESD current will first flow into the substrate through the collapse of the PN junction of the LDD tip and flow into the substrate. Finally, 5; SD current flows into the power supply port VSS through the source region 18 or the substrate 12 to discharge. As shown in Figure 1A, the PN junction depth of the LDD tip structure is shallower than the highly doped region (ie, N + doped region) in the drain region, and is very close to the surface channel with 0s ( surface channel). For TSMC's 0.35 micron CMOS process &, the PN junction depth of the tip structure is approximately 0.02 micrometers, and the junction depth of the N + doped region is approximately 0.2 micrometers. When the ESD current flows through a shallow 115]) tip structure, the high heat generated is often too late to dissipate, which can easily cause permanent damage to the LDD interface or surface channel, so the ldd structure has only a very low ESD tolerance. One way to improve ESD protection is to remove the LDD structure, as shown in Figure 2 [i and Figure L and Figure 23]. Figure 2A is another schematic diagram of the output port cage. The conventional method is to make certain specific components in the process and an ion implantation process without ^ " S. Such an ion implantation process can be formed on the sidewalls as described in U.S. Patent Nos. 5,416, 5, 5, ..., 5,941, 5,585,2 ", 5,672,527 and the like. And the N doping is covered by the t-protected region (ie, the n-doped region 19), but the doping concentration is greater than the doping concentration at the LDD tip structure.

Page 6 44294 1 V. Description of the invention (3) So it can cover the LDD tip structure. Because such an OS-related element does not have an LDD tip structure, its ESD tolerance can be improved. Another known method to improve ESD protection is to create a low breakdown voltage junction in the drain region, so that “^ current is discharged through the low breakdown voltage junction, but not through the LDD tip structure, as shown in Figure 3A and Figure 3. Figure 3A is a schematic diagram of another output port, and Figure 3B is a photomask layout of Figure 3A. This method also adds a photomask and an ion to the original L]) D process. The implantation process causes a high-concentration doped region 22 to be formed at the junction under the W-doped region of some specific elements. If the conductivity type of the high-concentration doped region 22 is, its doping concentration must be greater than ... If the conductivity type of the agro-doped region 22 is p-type, its doping concentration must be greater than the doping concentration of the well region 12. According to semiconductor physics, The PN junction will have a lower breakdown voltage, so the high-concentration doped region 22 can form a low breakdown voltage junction β when £ 31; 31) when the event occurs on the bonding pad 20, the 'ESD current will pass through the low breakdown voltage junction And released into the well area 12. Because the release path is away from the surface And LDj) tip structure, and the well area 12 has good heat dissipation ability, so this method can improve the ESD tolerance of the component. US Patent Nos. 5, 3 74, 565, 5, 581, 104, 5'674 This method is introduced in '761, 5, 953, 601, etc. One, however, the higher concentration of PN junctions will also have higher leakage current under the same reverse bias. For example, if the breakdown voltage is low The method of increasing the ES]) tolerance ability is applied to the 3 / 5v tolerant I / O buffer which can withstand the 3 / 5v tolerant I / O buffer, which may cause a significant leakage current to the input and output ports. ). 8 cm of CM micros

v 4 429 4 1

5. Description of the invention (4) During the process, the breakdown voltage of the low breakdown voltage interface is about 6 volts. If the bond pad 20 is maintained at a voltage of 5 volts (this often occurs in input / output ports that can tolerate 3/5 volts), then the bias (~ 5V) on the low breakdown voltage interface is very close to its breakdown Voltage, so as long as the process or voltage drifts a little, it may produce significant leakage current and consume power. Therefore, the method of improving the ESD tolerance with a low breakdown voltage interface is not suitable for the high voltage input and output ports. The present invention has two main purposes. The first is to remove the L]) D tip structure, the second is to guide the discharge of electrostatic discharge current through the well area, and the third is to not reduce the breakdown voltage of the PN junction in the electrodeless region. According to the above object, the present invention provides a device structure having a high electrostatic discharge tolerance and a manufacturing method thereof. The manufacturing method of the present invention includes the following steps. First, the manufacturing method of the present invention provides a base. The substrate includes a well region of a first conductivity type and a structure disposed in the well. In the manufacturing method of the present invention, an electrostatic discharge protection process is performed to form a second conductive type first protection product on the surface of the well area and the first protection area is adjacent to the gate structure. According to the manufacturing method of the present invention, a second, first, and first highly doped region is formed on the surface of the well region. Among them, the depth of the first protected area is lower than -highly doped. The concentration of the first protected area is lighter than that of the adjacent 5th of the doped area, and the part of the first protected area is related to the -higher < The points overlap. Component knot

As far as the capable structure is concerned, the present invention proposes a high electrostatic discharge resistance. The transistor includes a gate structure and a drain region.

Page 8 5. Invention description (5) and a source region. The gate structure is provided on the surface of a well region of a first conductive plastic on the substrate. The drain region and the source region are disposed on the surface of the well region, and are respectively adjacent to the gate structure. The drain region includes a first protection region of a second conductivity type and a first highly doped region of a second conductivity type. The first protection area of the second conductivity type is disposed on the surface of the well area and is adjacent to the gate structure. The first still doped region of the second conductivity type is provided on the surface of the well region. The depth of the first protection region is deeper than the depth of the first highly doped region. The concentration of the first protection region is lighter than that of the first highly doped region. Part of the first protection region is Overlaps with a portion of the first highly doped region. Because the first protection region and the LDD low-doped region are adjacent to the gate structure ', and the depth of the first protection region is deeper than the depth of the first highly doped region, so' as long as the If the doping concentration is greater than 11} 1), if the doping concentration in the region is low, the LDD tip structure will be covered and removed by the first protection region, so the ESD tolerance can be improved. On the other hand, because the first protection region and the first highly doped region only partially overlap, the pN junction formed by the first highly doped region and the well region will have a relatively large amount in the drain region. The pN junction formed by the first protection region and the well region has a low breakdown voltage. The ESD current will flow into the well region through the μ junction formed by the first highly doped region and the well region, and the well region can release a large amount of ESD power. In the present invention, the maximum concentration in the second conductivity type is that the P N junction breakdown voltage of the first high doped region is maintained as it is. ’From the basic structure, the device with this capability is suitable for a substrate, a conductive well area, and a second conductive device to provide a high electrostatic discharge resistance. The device of the invention comprises a first erbium doped region and a first

4429 4 Five Description of the invention (6) The first protection zone of two conductivity type. The well area is coupled to a power port. The first hafnium-doped region is disposed on the surface of the well region, is coupled to a bonding pad, and includes a side to be protected. The first protection area is provided on the surface of the well area and covers the side to be protected. The first protection region and the first highly doped region do not completely overlap. Wherein, the depth of the first protection region is deeper than the depth of the first highly doped =, and the concentration of the first protection region is lighter than that of the first highly doped region. —The gross point of this month is that the side to be protected is covered by the first protected area. Moreover, the depth of the first protected area is deeper than the depth of the -highly doped region. "[1 &gt; 1) Questions arising from the tip structure in the structure: because the ~ protected region and the -highly doped region are only scalloped, so the first highly doped region and the well The junction formed by the zone will have a lower ρν in the liquid electrode region than in the first protection zone and the well zone.

The junction has a low collapse 'ESD current will flow into the well region through the PN junction formed by the first highly doped region and the well region' and the well region can release a large amount of ESD. The largest concentration in the invention having the second conductivity type is The first inter-doped region is exactly the same as the LDD structure in the conventional process, so there is no problem of reducing the breakdown voltage of the PN junction. The above-mentioned purpose, characteristics and advantages can be more clearly understood. Special examples-better implementation examples and the accompanying drawings are used to make detailed descriptions. Simple illustration of the drawings: Figure 1A is a tradition Schematic diagram of output port with 0 LSD structure;

Page 10 AA29 4 1 V. Explanation of the invention (7) Figure 1B is Figure 1A and Figure 2A is another intent; Figure 2B is Figure 2A and Figure 3A is a schematic diagram of a conventional output port NMOS Figure 3B Figures 3A, 4A to 4F, Figures 5A and 5C are cross-sectional views of the PMOS transistor. Figure 5B is Figure 5A, Figures 6A and 6C, and Figure 6B of the PMOS transistor is Figure 6A. Figures 7A and 7B are schematic diagrams of the crystal; Figures 8A and 8B are layered transistors; Figure 9A is the invention and Figure 9B is a symbol description of the invention: 30 ~ substrate 12; U, 34 ~ Photomask layout diagram of gate structure; Known photomask layout diagram of output port NM0s with LDD structure removed; Known to use low breakdown voltage interface as ESD protection diagram; Photomask layout diagram of the present invention Schematic diagram of the manufacturing method; Respective transistors provided in the present invention and the photomask in Figure 5C: Respective electrical cross-sections provided in the present invention; and Figure 6C Mask layout diagram; for applying the present invention in N-type and p-type fields Application of a first embodiment of the diode element of the embodiment; In the second application to the diode elements of the well region 2 ~ 3; 31~ gate; Example

442941 V. Description of the invention (8) 1 6, 3 5 ~ Drain region 36 ~ LDD region; 40 ~ Side wall; 44 ~ Bond; 48 ~ Metal wire; 60 ~ Field oxide layer; 33 ~ Gate oxidation Layer; 18, 3 7 ~ source region; 38, 54 ~ ESD region; 42, 52 ~ N + diffusion region; 46-ILD; 50 ~ P + diffusion region; 6 6 ~ side to be protected. Example: Please refer to FIGS. 4A to 4F, and FIGS. 4A to 4FR] are schematic flowcharts of the manufacturing method of the present invention. For convenience of explanation, the first conductive type is replaced by a P type, and the second conductive type is replaced by an N type. The manufacturing method of the present invention is used for manufacturing an electrostatic discharge (ESD) protection element. The left half of Figures 4 through 4 are cross-sectional views of general components, and the right half are cross-sectional views of ESD protection components. 1 First, the present invention provides a substrate 30. The substrate 30 includes a p-well region 32 and a gate structure 34 'as shown in FIG. 4A. In Fig. 4A, the cross section of the general element and the ESD protection element have two gate structures 34. Each gate structure 34 is composed of a gate electrode 31 and a gate oxide layer 33. The surface of the middle well region 32 of the two gate structures ^ is called the drain region 35, and the surface of the outer region 32 of the two gate structures 34 is called the source. Polar region 37. Then • 'The present invention performs a second ion implantation process, also known as a 1-ightly-doped-drain ion implantation process, to form -N-type first- The low-doped region, also known as hafnium, is shown in Figure 4B. The LDD ion implantation process is mostly based on a photoresist layer and a substrate.

Page 12 4 429 4 1 V. Description of the invention (9) ί Hi: 1 structure 34 is used as a veil for ion implantation, so ^ and zone 3 6 will be adjacent to the gate structure 3 4. ESD protection elements or general elements can form the LDD region 36, as shown in Fig. 4B. Then, an electrostatic discharge (ESD) ion implantation process is performed to form a first protection zone, also called ESD zone 38, on the well area, as shown in the figure. In the ESD ion implantation process, a photoresist layer and the gate and π structure 34 on the substrate 30 are used as a mask for ion implantation, so the area μ formed will be adjacent to the gate structure 34. Moreover, the ESD ion implantation process only implants specific areas of the esj) elements, and does not implant general elements. As shown in the figure, 'ESD region 38 is formed only in the drain region 35 of the ESD protection element, and f does not have ESI in the region where the contact hole is scheduled to be formed. That is, the contact hole is not associated with ESD The areas 38 overlap. The doping concentration of the ESD region 38 is greater than the doping concentration of the LDD region 36. The depth of the ESD region 38 is greater than the depth / operation of the LDD region 36. Therefore, the region where the ESD region 38 and the LDD region 36 overlap will be esd region 38. -Mainly 'as shown in Figure 4C. Then, a side wall 40 is formed on the side wall of the gate structure 34, as shown in FIG. 4d. The manufacturing process of the sidewall member 40 generally includes two steps. The first is to deposit a layer of oxide on the substrate 30; for example, a low temperature oxygen second layer (LTO). The second is to perform an etch back process' remove the silicon oxide layer on the substrate vertically with an anisotropic etch and leave the silicon oxide layer on the sidewall of the gate structure to form a sidewall. 4D picture. Then, a first ion implantation process is performed, also called source / drain (S / D) ion implantation, to form an n on the surface of the well area.

d429 4 ^ V. Description of the Invention The first highly doped region of the type αο) is also called an N + diffusion region 42. Both the ESD protection element and the general element can form the N + diffusion region 42. The doping concentration of the branch diffusion region 42 is greater than that of the ESD region 38. The depth of the N + diffusion region 42 is between the depth of the LDD region 36 and the depth of the ESD region 38, as shown in FIG. 4D. Generally speaking, the S / D ion implantation process uses a photoresist layer, the gate structure 34 on the substrate 30, and the side wall 40 as a mask to perform ion implantation, so the N + diffusion region 42 formed will be adjacent to the side wall. 40%. Moreover, in the drain region 35 of the ESD protection element, the material diffusion region "does not completely overlap with EsDg38, that is, a portion of the N + diffusion region 42 overlaps with a portion of the ESD region 38. As shown in Fig. 4D, £ The pupal region 38 covers the Xu diffusion region "close to the gate structure 34." It is divided, and there is only n + diffusion in the area where the contact hole is to be formed. Finally, a subsequent connection process is performed to form an interconnecting line, so that the material diffusion region of the drain region 35 of the ESD protection element is “coupled to a junction”. Pad 44, and well area 32 is coupled to a power port vss, as shown in Figure 4 and Figure VII. For example, first, an interlayer dielectric (mter-layer-diehcthc) is formed on the substrate 30 and the gate structure 34. iLD) layer 46; then contact =, as shown in Figure 4E; then fill the hole with a conductive object; and then form a metal wire ", as shown in Figure 4F β requires special attention, the drain region of the ESD protection element The contact hole in 35 does not overlap with the ESD region 38 in position. The spirit of the manufacturing method of the present invention is that an ESD ion implantation process is used to form the ESD region of the drain region of the ESD protection element to enhance the ESD tolerance of the protection element. The doping concentration of the ESD region 38 is between the diffusion region and the diffusion region. Between the doping concentrations of the LDD region 36, the depth of the ESD region 38 is greater than the N + diffusion region

Page 14 V. Description of the invention (11) 42 and the part of the ESD region 38 overlaps with the part of the N + diffusion region 42. The advantages of the present invention are as follows: 1. The drain region 35 of the ESD protection element no longer has the LDD tip structure because of the presence of the ESD region 38. Therefore, in the event of an ESD event, there is no discharge of the LDD tip to reduce ESD Problems with tolerance. 2. The lowest breakdown voltage of the drain region 35 of the ESD protection element will fall at the PN junction of the N + diffusion region 42 and the well region 32. In other words, the ESD current will no longer be released to the power port VSS through the vicinity of the surface channel, but will be released to the power port VSS through the N + diffusion region 42 and the PN interface of the well region 32, and then pass through the well region 32. Paths can be subject to large esd currents. 3. The lowest breakdown voltage of the drain region 35 of the ESD protection device will be the same as the lowest breakdown voltage of the drain region of the general device. It can be seen from FIGS. 4D to 4F that the lowest breakdown voltage of the drain region 35 of the general device and the ESD protection device is determined by the doping concentration in the N + diffusion region 42 and the well region 32, so they are all the same. In other words, the manufacturing method of the present invention does not reduce the breakdown voltage of the ESD protection element, so it can be applied to the design of high-voltage input / output ports. Of course, the method of the present invention can also be applied to a field-oxide device to improve its ESD tolerance. For example, the gate structure contains a field oxide layer. The other steps are the same, so I won't go into details here. Moreover, in addition to the above-mentioned NMOS, the production method of the present invention can also produce PMOS, as long as the first conductivity type is replaced by N, and the second conductivity type is replaced by p-type. The following is a process integration

Page 15 '4 429 4 1 V. Description of the invention (12)' Process examples: 1. Provide gate structure; 2. N-type LDD ion implantation; 3. P-type LDD ion implantation; 4. N-type ESD Ion implantation; 5. P-type ESD ion implantation; 6. Making sidewalls; 7. N-type S / D ion implantation; P-type S / D ion implantation; and 9. Making interconnects. Please refer to FIG. 5A to FIG. 5C, FIG. 5A and FIG.% Are cross-sectional views of the ㈣s transistor and the PM0S transistor provided by the present invention, and FIG. Hood layout diagram. In terms of element structure, the present invention provides a transistor having a high electrostatic discharge resistance, such as the NMOS transistor in Fig. 5A and the pMOS transistor in Fig. 5C. Here we will introduce the NMOS transistor. As for the PMOS transistor, please refer directly to the% chart and the corresponding number. The pass transistor includes a gate structure 34, a drain region 35 = and a source region 37. The gate structure 34 is disposed on the surface of a P-shaped well region 32 on a substrate 30 and includes a gate electrode 31 and a gate oxide layer. A sidewall 40 is adjacent to the periphery of the gate structure 34. The pole region 35 and the source The pole region 37 is located on the surface of the well region, and is individually adjacent to the gate 14. The drain region 35 includes an N-type first protection region (that is, ES) region ^ = type first-highly doped region (that is, Is N + diffusion region 42). The ESD region 38 is provided on the surface of the well region 32 and is adjacent to the gate structure 34. The material diffusion region is provided in the well

4429 4 1 V. Description of the invention (13) The depth of the surface ESD region 38 of the region 32 is relatively higher than that of the diffusion region. The concentration of ESD = 38 is lighter than that of the N + diffusion region 42 and the N + diffusion region 42. It partially overlaps. The non-polar region has passed through at least one scattering, and the contact hole on: 2 is coupled to the bonding pad ", and the contact hole does not overlap the ESD region 38, as shown in Figure 5B. The source region 37 is a Ud structure, = The second highly doped # region containing the -N type (ie, the N + diffusion region 52) and a 100 ° P-type well region 32 are coupled to a power port through a P + diffusion region 50, or through N + diffusion. A pN junction formed between the region 52 and the well region 32 is coupled to the power port VSS. ^ When an ESD event with a positive voltage relative to the power port VSS occurs on the bonding pad 44, the ESD current will flow into the well area through the contact surface under the contact hole, and then flow into the power port vss. Such a discharge path has a large ESD tolerance, so it can provide better ESO protection. The source region 37 can also be made into a structure similar to the drain region 35, with the same addition of the £ 81) region, as shown in Figures 64 to 6 (: Figures. Figures 6 and 6 (: Figures, respectively) This is another cross-sectional view of a leg 〇3 transistor and a PM 〇s transistor provided in the present invention. 'Figure 6B is a photomask layout diagram of Figures 6A and 6C. When the ESD region 38 is formed' The source region 37 forms an N-type second protection region (ie, the ESD region 54). The ESD region 54 meets the N + diffusion region 52. Because the esd region 54 and the ESD region 38 are formed at the same time, the ESD region 54 and The characteristics of the ESD region 38 are exactly the same. The present invention can also be applied to other ESD protection elements, such as a field-oxide device. For example, if FIG. 5A and FIG.

4429 4 Ί Description of the invention (14) The gate electrodes 31, 31a and the gate oxide layers 33, 33a in Fig. 5C are all replaced with the field oxide layer 60, and the results are shown in Figs. 7A and 7B. For the same reason, the gate electrodes 31, 31a and the gate oxide layers 33, 33 &amp; in Figs. 6A and 6C can also be replaced with the field oxide layer 60. The results are shown in Figs. 8A and 8B. . The present invention uses a deeper ESD region 38 to protect the LDD structure that was more susceptible to ESD damage, and causes the ESD current to find another channel to be released. Therefore, the same concept, if a device has a side that is easily damaged by gSj) and needs to be protected (called the side to be protected), then an ESD zone can be added to the side to be protected to strengthen ESD protection. effect. The present invention can also be applied to a diode structure to improve its resistance to ESD, as shown in Fig. 9A. Fig. 9A is a first embodiment of the present invention applied to a diode element. The diode to which the present invention is applied includes a p-type well region 32, an N-type first highly doped region (N + diffusion region 42), and an N-type first protection region (ESD region 38). The well region 32 is consumed by a well contact region (p + diffusion region 50) to a power supply port VSS 'as the anode of the diode (anocje) + diffusion region 42 is provided on the surface of the well region 32 and is coupled to a bonding pad 44 Contains a side 66 to be protected. The ESD region 38 is provided on the surface of the well region 32 and covers the side 66 to be protected. The ESD region 38 and the N + diffusion region 42 serve as cathodes of the diodes and do not completely overlap. Among them, the depth of the ESD region 38 is deeper than the depth of the N + diffusion region 42. The concentration of the ESD region 38 is lighter than that of the N + diffusion region 42. In this way, when the ESD event occurs on the bonding pad 44, the ESD current will not be released through the side 66 to be protected, but will seek the area in the diffusion area 42 that is not covered by the ESD area 38. Therefore, the device of the invention can have a good ESI) resistance

Page 18 V 442941 V. Description of Invention (15) Capability. For the same reason, the present invention can also be applied to a diode provided between the bonding pad 44 and the power supply port VDD, as shown in FIG. 9B ° FIG. 98 is a second implementation of the present invention applied to a diode example. The diode in the second embodiment includes an N-type well region 32a, a P-type first highly doped region (P + diffusion region 42a), and a P-type first protection region (ESD region 38a). The well region 32 is coupled to a power supply port VDD through a well contact region (N + diffusion region 50a), and serves as a cathode of the diode ° P + diffusion region 42a is provided on the surface of the well region 32a, and is coupled to a bonding pad 44, Contains a side 66a to be protected. The ESD region 38a is provided on the surface of the well region 32a and covers the side to be protected "a. The ESD region 38a and the P + diffusion region 42a serve as anodes of the diodes and do not completely overlap. Among them, ' The depth of the ESD region 38a is deeper than the depth of the p + diffusion region 42a, and the concentration of the ESD region 38 is lighter than that of the P + diffusion region 42a. Compared to the conventional manufacturing method, the present invention is produced by an ESD ion implantation process. An ESD region to make the LDD structure disappear, and the ESD region does not completely cover the N + diffusion region, so the ESD current can flow through the well region with greater eSE) tolerance. In addition, the doping concentration ratio of the ESD region … The doping concentration of the diffusion region is low, so it will not reduce the breakdown voltage of the PN junction. Although the present invention is disclosed above in a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art, Without departing from the spirit and scope of the present invention, some modifications and retouching can be done. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (1)

4429 4 VI. Patent application scope I A transistor with electrostatic discharge protection capability, including: a gate structure, a first conductive well surface on a substrate, an electrodeless region, and The gate structure has a drain-second conductive type connected to the gate structure; and a source region 'is provided on the surface of the well region' and individual adjacent regions include: a first protection region provided on the surface of the well region and The first highly doped region adjacent to the J-conductivity type is provided on the surface of the well region; Acoustic: Zhong Zhe The depth of the first protection region is deeper than the first highly doped region, and the first The concentration of the protection region is lighter than that of the first highly doped region, and a portion of the first protection region overlaps with a portion of the first highly doped region. 2. The transistor according to item 1 of the patent application scope, wherein the transistor further includes a side wall adjacent to the periphery of the gate structure, and the first highly doped region is adjacent to the side wall. ^ 3. The transistor according to item 1 of the patent application, wherein the drain region is coupled to a bonding pad, and the well region is coupled to a power port. 4. The transistor according to item 3 of the patent application, wherein the drain region is coupled to the bonding pad through at least one contact hole provided on the first doped region, and the contact hole is not connected with the contact pad. The first protected areas overlap. 5 · If the transistor of the scope of the patent application, the source region is a lightly doped; and the electrode structure (Hght-doped-drain structure). 6. If the scope of the patent application of the transistor , Where the source region contains: Page 20 4429 4 1 VI. The scope of the patent application is one second and one second two highly doped regions. Among them, the depth is deep, the first 7. 7. A method, including providing a one-to-one gate junction for one. Forming a second gate structure; performing one of the two conductivity types, the depth is deep, the lightest, and the first stack. 8. The method further includes forming a second conductive zone of a conductive type on the surface of the well area; a second protective area of the conductive type * the second protective area is coupled with the first; The depth of the protected area is deeper than that of the second highly doped area, and the concentration of the protected area is deeper than that of the second side soot area? Nongdu produces a structure with electrostatic discharge protection capabilities. The manufacturer has the following steps: The substrate * includes: a conductive well area; and a structure disposed on the surface of the well area. A first conductive region of surface conductivity type, and the first protective region is adjacent to the first ion distribution process, forming a first highly doped region on the surface of the well region; the depth of the first protective region The concentration of the protection region is deeper than that of the first highly doped region. The portion of the protection region that is deeper than the concentration of the first highly doped region is the same as that of the first highly doped region. The production method, wherein the production has the following steps: an inter-connection to make the well Page M ^ 429 4 1 VI. The patent application park is coupled to a power port and the first high ^. Doped region is coupled to a bonding technique 9 containing a hole ^ on the highly doped region as the first The high-doped region is electrically connected, and the contact hole does not overlap the first protection region. 10. The manufacturing method according to item 7 of the scope of patent application, wherein the manufacturing method further includes the following step: performing a second ion distribution process to form a second conductive type first on the surface of the well area. The low-doped region is adjacent to the gate structure. The doping concentration of the first lowly doped region is lighter than that of the first protection region, and the depth of the second doped region is shallower than the depth of the first highly doped region. 11. The manufacturing method according to item 7 of the scope of patent application, wherein the manufacturing method further includes a step for forming a sidewall on the sidewall of the gate structure before the first ion distribution process, and the first A highly doped region is adjacent to the sidewall. 1 2. The manufacturing method according to item 7 of the patent application scope, wherein the gate structure includes a gate electrode and a gate oxide layer. 1 3. The manufacturing method according to item 7 of the patent application scope, wherein the gate structure includes a field oxide layer. 14. The manufacturing method according to item 7 of the scope of patent application, wherein the first conductivity type is a P-type and the second conductivity type is an n-type. 1 5. The manufacturing method of item 7 in the scope of patent application, wherein the first Page 22 4 42 9 4 1 6. Scope of patent application Conductive type, and the second conductive type is P type. 16. -¾¾ A device capable of protecting against electrostatic discharge, suitable for being thrown on a substrate, including: a well region of a first conductivity type, coupled to a power port;-a first highly doped region of a second conductivity type, On the surface of the well area, a surface is bonded to a bonding pad, which includes a side to be protected; and a second conductive type first protection area is provided on the surface of the well area, and the first protection area covers the to be protected. Protect the side, and the first protection region and the first highly doped region do not completely overlap; wherein the depth of the first protection region is deeper than the depth of the first highly doped region, the first protection region The concentration is lighter than the concentration of the first highly doped region. 17. The device according to item 16 of the scope of patent application, wherein the device further comprises a well contacting area of the first conductivity type, which is provided on the surface of the well area and is coupled to the power port. 18. For example, the device under the scope of application for patent No. 16 wherein the device further includes a second highly doped region of the second conductivity type, which is provided on the surface of the well region and is coupled to the power port. The device of the scope of the patent No. 18, wherein the device further comprises a second protection zone of the second conductivity type, and the second protection zone is combined with the first miscellaneous zone. 20. The device according to item 16 of the patent application scope, wherein the device further comprises a gate structure provided between the first highly doped region and the second highly doped region to separate the first highly doped region The highly doped region and the second highly doped region. Page 23, 4Λ29 4 ^ VI. Patent application scope 21. The device according to item 20 of the patent application scope, wherein the gate structure includes a gate electrode and a gate oxide layer. 2 2. The device as claimed in claim 20, wherein the gate structure includes a field oxide layer. Page 24