TW442876B - Multi-chip module - Google Patents

Multi-chip module Download PDF

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Publication number
TW442876B
TW442876B TW089109787A TW89109787A TW442876B TW 442876 B TW442876 B TW 442876B TW 089109787 A TW089109787 A TW 089109787A TW 89109787 A TW89109787 A TW 89109787A TW 442876 B TW442876 B TW 442876B
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Taiwan
Prior art keywords
wafer
bonding
conductive
chip
package structure
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TW089109787A
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Chinese (zh)
Inventor
Chun-Hung Lin
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/484—Connecting portions
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    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
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    • H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
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    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A multi-chip module comprises two chips stacked on a device for carrying chips. The two chips are electrically connected to the device for carrying chips by bonding wires. A plurality of conductive bumps are formed between the two chips. The bump has a base and a columnar protrusion. The bump is connected to the chip pad of the bottom chip by its base, and to the bottom of the upper chip by its columnar protrusion for supporting the upper chip. In accordance with the multi-chip module of the present invention, the columnar protrusion of the bump provides the clearance required for the bonding wires at bottom chip, it is able to prevent the bottom chip from being damaged by the upper chip.

Description

442876442876

五、發明說明（l)發明領域： W發明frf、關於一種多晶片封裝構造 nodule, MCM),特別有關於一種晶片堆疊式多hiP 造 先前技術 晶片封裴 構 片2 ί ϋ ί ί越來越輕薄短小’使得用以保護半導翻 片以及k供外部電路連接的封裝構造也同樣 2體晶 化0 干王碎短小 '隨著微小化以及高運作速度需求的增加，多晶 ίί:多電子裝置越來越吸引人。多晶片封裝構造可Ϊ構 將兩個或兩個以上之晶片組合在單一封裝構造 I踌由 統運作速度之限制最小化β此外’多晶片封裝二來使系 晶片間連接線路之長度而降低訊號延遲以及存取減少 .最常見的多晶片封裝構造為並排式（side_by~si' '。 片封裝構造，其係將兩個以上之晶月彼此並排地 I多晶 共同基板之主要安裝面。晶片與共同基板上導電 於一V. Description of the invention (l) Field of invention: W invention frf, about a multi-chip package structure (nodule, MCM), especially about a chip stacked multi-hiP manufacturing of the prior art wafer sealing structure 2 ί ϋ ί increasingly 'Thin, thin and short' makes the package structure to protect the semiconducting flip-flops and k for external circuit connection the same. 2 body crystallized 0 dry king broken short 'With the increase in miniaturization and high operating speed requirements, polycrystalline: The installation is getting more and more attractive. The multi-chip package structure can be constructed by combining two or more chips in a single package structure. I. Minimize the speed limit of the system. In addition, the multi-chip package II reduces the signal length of the connection lines between the chips. Delay and access are reduced. The most common multi-chip package structure is side-by-side (side_by ~ si ''. The chip package structure is the main mounting surface of the I polycrystalline common substrate with two or more crystal moons side by side. Wafer Conductive with a common substrate

連接一般係藉由線銲法（wire bonding)達成》然而發間之 式多晶片封裝構造之缺點為封裝效率太低，因為該^ 板之面積會隨者晶片數目的增加而增加。 _ 因此，美國專利第5323060號揭示一多晶片堆疊裝置 (niultichip stacked device)，其包含一第一半導體晶片 110設於一基板120並且電性連接至基板120，以及一第二 半導體晶片130堆疊於該第一半導體晶片上並且電性連接 至基板（參見第一圖）^該美國專利第5323060號之特徵The connection is generally achieved by wire bonding. However, the disadvantage of the multi-chip package structure is that the packaging efficiency is too low, because the area of the board will increase as the number of chips increases. _ Therefore, U.S. Patent No. 5,233,060 discloses a multi-chip stacked device including a first semiconductor wafer 110 disposed on a substrate 120 and electrically connected to the substrate 120, and a second semiconductor wafer 130 stacked on the substrate. The first semiconductor wafer is electrically connected to the substrate (see the first figure) ^ Features of US Patent No. 5323060

'ASEKVER^backup、合灣專利肀謗索、二维條崎說明書、阳0-〇49· Ptd'ASEKVER ^ backup, Hewan patent defamation cable, two-dimensional Shizaki manual, Yang 0-〇49 · Ptd

442876 五、發明說明（2) 在於利用一設於兩晶片間的膠層140來提供銲線線孤（the loops of the bonding wires)所需之空隙（ciearance) 並且該膠層140之厚度必須大於銲線之弧高（i00p height) —指晶片110正面與鲜線150線弧頂點間的距離—以避免晶 片1 3 0接觸到銲線1 5 0之線弧。 習知在晶片銲墊與基板銲墊間形成銲線連接（wire interconnection)之打線技術一般係包含（a)球接合（ban bond)於晶片銲墊’（b) 形成線弧於晶片銲塾與基板銲整 間以及（c)壓印接合（stitch bond)至基板銲墊而完成該 録線連接。一般其孤高約為10至15密爾（mii)。雖然藉著 調整線弧參數，外形以及型式，.習用打線技術可以”將弧高 將低旱大約6密爾（m i 1 )。然而這已是可得到的最小弧高， 因為若更低將使線受損並且使其拉力變差# '间 因此，使用習知打線技術時，該膠層丨4{J之厚度必須大442876 V. Description of the invention (2) The use of an adhesive layer 140 provided between two wafers to provide the gaps required for the loops of the bonding wires, and the thickness of the adhesive layer 140 must be greater than The arc height of the bonding wire (i00p height) —refers to the distance between the front face of the wafer 110 and the apex of the line 150 of the fresh wire—to prevent the wafer 130 from touching the arc of the bonding wire 150. Conventionally, the wire bonding technique for forming a wire interconnection between a wafer pad and a substrate pad generally includes (a) a ban bond on the wafer pad '(b) forming a wire arc between the wafer pad and the wafer pad and The substrate welding entire room and (c) a stitch bond to the substrate pad complete the recording connection. Its solitary height is generally about 10 to 15 mils (mii). Although by adjusting the line arc parameters, shape and type, the conventional wire drawing technology can "lower the arc height by about 6 mils (mi 1). However, this is already the minimum arc height available, because if it is lower, it will make The wire is damaged and its tensile force becomes poor. Therefore, when using conventional wire bonding technology, the thickness of the adhesive layer must be large.

於8密爾以完全防止晶片130接觸到銲線15〇之線弧。該膠 層140之材料一般為環氧膠（ep0Xy)或膠帶（tape)。狭而 形成厚度達8密爾之環氧膠層是非常困難的。此外，”當_ 用厚度達8密爾之膠帶：，其一方面將大幅增加製造成本; 另一方面，塑料.製成的膠帶與梦晶月間的熱’膨脹係數不一 致（CTE mismatch)也將嚴重損壞所製得封裝構造之可靠 ，由使用美國專利第5 7350 30號揭示之打線方法可以將 弧高降低至2密爾。請參照第二圖以及第十二圖， 根據美國專利第5 7 3 5 0 3 0號之打線流程。一聞妞券裉志一It is 8 mils to completely prevent the wafer 130 from contacting the arc of the bonding wire 150. The material of the adhesive layer 140 is generally epoxy adhesive (ep0Xy) or tape. It is very difficult to form an epoxy adhesive layer with a thickness of 8 mils. In addition, "When_ when using a tape with a thickness of 8 mils: on the one hand, it will greatly increase the manufacturing cost; on the other hand, the thermal expansion coefficient (CTE mismatch) between the tape made of plastic and Mengjing Moon will also be The package structure produced by severe damage is reliable, and the arc height can be reduced to 2 mils by using the wiring method disclosed in US Patent No. 5 7350 30. Please refer to the second and twelfth figures according to the US patent No. 5 7 3 5 0 3 The connection process of No. 0. Yi Wen Niu coupon 裉 志 一

VvSERVERVbaekuiA钟糾 ^ ㈣匕牌料㈣ cfl49. ptd 第5頁 4 42 8 7 6 —,MI_ 1 丨關 .....一^· . 丨. 丨丨削_ 丨一 五、發明說明（3) 突起（protuberance)200於晶片銲墊21〇上，其係藉由先球 銲（ball bond)導電銲線之，端於於該晶片銲塾210上，然-後在緊接該銲球端之位置，麇印（s t i t c h b ο n d )該銲線於 該球銲端使得該球銲部以及麇印部一起形成該突起2 00 (如第十三圖所示）。熱後，使用球銲工具(ball bonding tool)將鮮線220之〆端以球接合方式銲接於基板 銲墊2 3 0，然後以壓印接合方式將另一端銲接至晶片銲墊 210上的導電突起2〇〇 (參見第二圖）。 請參照第一圖及第二圖，當使用美國專利第5 3 23 0 6 0號 揭示之打線方法時，該膠層1 4 0—之厚度必須保持至少4密爾 以完全防止晶片1 3 0接觸到銲線2 2 0之線弧。然而要形成厚 度超過4密爾之環氧膠層並真保持穩定之膠層厚度（bond 1 i n e t h i c k n e s s )是非常困難的。而一但無法控制膠層厚 度，則不但在上層晶片1 3 〇安裝後會引起共平面性 (coplanarity)不良之問題，而且嚴重時該上層晶片130將 會碰觸到下層銲線 < 綠弧，甚至導致其扭曲移位。 發明概要： 隨i 因此，本發明之主要目的係提供一種多晶片封裝構造〜了' 其包含兩晶片以堆疊方式安裝於一用以承載晶片之裝置， 該兩晶片分別以線接合方式電性連接.至該用以承載晶片之 裝置，其中該多晶片封裝構造之特徵在於該堆疊晶片間設 有複數個導電凸塊作為間隔，藉此防止上層晶片損傷下廣 晶片之銲線。 根據本發明第一較佳實施例之多晶片封裝構造主要包含VvSERVERVbaekuiA 钟 纠 ^ ㈣ 牌 牌 料 ㈣ cfl49. Ptd Page 5 4 42 8 7 6 —, MI_ 1 丨 Off ..... One ^.. 丨. 丨 丨 Cutting_ 丨 Fifth, the description of the invention (3) A protrusion 200 is formed on the wafer pad 21, which is connected to the wafer pad 210 by a ball bond conductive wire, and then-immediately after the end of the solder ball. Position, stamp (stitchb ο nd) the bonding wire at the ball welding end so that the ball welded part and the stamped part together form the protrusion 2 00 (as shown in the thirteenth figure). After heating, use a ball bonding tool to solder the end of the fresh wire 220 to the substrate pad 2 3 0 by ball bonding, and then solder the other end to the conductive pad on the wafer pad 210 by imprint bonding. The protrusion 200 (see the second figure). Please refer to the first figure and the second figure. When using the wire bonding method disclosed in US Patent No. 5,323,060, the thickness of the adhesive layer must be kept at least 4 mils to completely prevent the wafer 1 3 0 Touch the arc of the wire 2 2 0. However, it is very difficult to form an epoxy adhesive layer having a thickness of more than 4 mils and truly maintain a stable adhesive layer thickness (bond 1 i n e t h i c k n e s s). However, once the thickness of the glue layer cannot be controlled, not only will the problem of poor coplanarity be caused after the upper wafer 130 is installed, but in severe cases, the upper wafer 130 will touch the lower bonding wire < green arc And even cause it to distort. Summary of the Invention: With i, the main object of the present invention is to provide a multi-chip package structure ~ which includes two chips mounted in a stack on a device for carrying the chips, and the two chips are electrically connected by wire bonding. To the device for carrying a wafer, wherein the multi-chip package structure is characterized in that a plurality of conductive bumps are provided as intervals between the stacked wafers, thereby preventing the upper wafer from damaging the bonding wires of the lower wafer. The multi-chip package structure according to the first preferred embodiment of the present invention mainly includes

第6頁 4:428 7 6 4、發明說明⑷ — |兩晶片以堆疊方式設於一用以承載晶片之裝置（例如一基 i板或一導線架）^該兩晶片間設有複數個導電凸塊，其具 有基部以及柱狀突出部，該凸塊以其基部接合於下層晶片 之晶>1銲墊，並且以其柱狀突出部連接該上層晶片之底部 丨以支撐該上層晶片。該兩晶片間設有一膠層。該兩晶片分 Μ以線接合方式電性連接至該用以承載晶片之裝置，其中 ώ下層銲線之一端係以球接合方式（ball bonding)連接至 用以承載晶片之裝置，另一端係以壓印接合方式 (jstitch bonding)連接至該設於該下層晶片銲墊上導電凸 塊之基部。根據本發明第一較佳實施例之多晶片封裝構 造，由於該凸塊之柱狀突出部提供下層銲線所需之空隙 (| c 1 e a r a n c e )，藉此可防止上層晶片損傷下層晶片之銲 降。Page 6 4: 428 7 6 4. Description of the invention | — | Two chips are stacked in a device (such as a base i-board or a lead frame) for carrying the chips ^ There are a plurality of conductive between the two chips The bump has a base portion and a columnar protruding portion, the bump is bonded to the crystal of the lower layer wafer with its base portion> 1, and the columnar protruding portion is connected to the bottom of the upper layer wafer to support the upper layer wafer. An adhesive layer is disposed between the two wafers. The two wafers are electrically connected to the device for carrying the wafer by wire bonding. One end of the lower bonding wire is connected to the device for carrying the wafer by ball bonding and the other end is connected to the device for carrying the wafer. Jstitch bonding is connected to the base of the conductive bump provided on the underlying wafer pad. According to the multi-chip package structure of the first preferred embodiment of the present invention, since the pillar-shaped protruding portion of the bump provides the gap (| c 1 earance) required for the lower bonding wire, thereby preventing the upper bonding wafer from damaging the bonding of the lower bonding wafer. drop.

i根據本發明第二較佳實施例之多晶片封裝構造，其特徵 以於該下層晶片之晶片銲墊設有導電突起，其中該下層銲 _之一端係以球接合方式連接至該用以承載晶片之裝置， i另一端係以壓印接合方式連接至該導電突起。此外，該 I晶片間亦設有複數個導電凸塊位於該下層銲線之壓印接合 _，並且連接至該上層晶片之底部以支撐該上層晶片。可 k理解的是，根據本發明第二較佳實施例之導電凸塊.只需 設置在晶片的四個角落區域即可提供下層銲線所需之空隙 (c 1 e a r a n c e )而防止上層晶片損傷下層晶片之鮮線。 丨本發明另提供一種製造根據本發明第一較佳實施例多晶The multi-chip package structure according to the second preferred embodiment of the present invention is characterized in that the wafer pads of the lower layer wafer are provided with conductive protrusions, wherein one end of the lower layer solder is connected to the load-bearing manner by ball bonding The other end of the device of the chip is connected to the conductive protrusion in an embossed manner. In addition, a plurality of conductive bumps are also arranged between the I-chips, and are connected to the bottom of the upper-layer bonding wire to support the upper-layer chip. It can be understood that the conductive bumps according to the second preferred embodiment of the present invention can be provided in the four corner areas of the wafer to provide the gaps (c 1 earance) required for the lower bonding wires and prevent the upper wafer from being damaged. Fresh line of the lower wafer.丨 The present invention further provides a method for manufacturing a polycrystal according to the first preferred embodiment of the present invention.

I i片封裝構造之方法，其包含下列步驟··（ a ) 固定下層晶片A method for constructing an i-chip package, including the following steps: (a) fixing a lower-layer chip

\ASE]iVER\bac(tup\台灣專利申锖*\二維條磷坑明書#00-0«. ptd 第7頁 4 42 8 7 6 庄、發明說明（5) 至一用以承載晶片 具有基部以及柱狀 片之晶片銲墊；（C i一端於該導電引線 |以承載晶片之裝置 |面；（e ) 將上層晶 、導電凸塊之柱狀 襖數條下層銲線至 晶片銲墊。 本發明再提供一 之裝置；（b)形成複數個導電凸塊，其 突出部，該凸塊以其基部接合於下層晶 )以球接合方式連接複數條下層銲線之 ，以壓印接合方式連接其另一端至該用 ;(d ) 塗佈一膠層於該上層晶片之正 片置入該膠層直到接觸該下層晶片銲墊 突出部；（f)固化該膠層；及（g) 連接 該用以承載晶片之裝置以及上層晶片之 片封裝構造 以承 至 用 下層晶 銲線之 接其另 複數個 !膠·.層於 _到接 條下層 銲墊。 為了 顯，下 細說明 b明說 片之 -端 一端 導電 該上 觸該 鲜線 讓本 文特 如下 明： 之方法 載晶片 晶片鮮 至該用 至設於 凸塊於 層晶片 導電凸 至該用 發明之 舉本發 種製造根據本 ，其包含下列 之裝置；（b) 墊；（c ) 以球 以承載晶片之 下層晶片銲墊 該下層銲線之 之正面；（f ) 塊；（g ) 固化 以承載晶片之 發明第二較佳實施例多 步驟：（a ) 固定下層晶 形成複數個導電突起於 接合方式連接複數條下 裝置，以壓印接合方式 上之導電突起；（d) 形 壓印接合端；（e ) 塗佈 將上層晶片置入該膠 該膠層；及（h) 連接複 裝置以及上層晶片之晶 QS 月 該 層 連 成\ ASE] iVER \ bac (tup \ Taiwan Patent Application ** Two-dimensional strip phosphorus pit certificate # 00-0 «. Ptd page 7 4 42 8 7 6 Zhuang, invention description (5) to one for carrying wafers A wafer bonding pad having a base and a columnar piece; (C i is at one end of the conductive lead | to carry the device of the wafer | surface; (e) a column of upper crystals and conductive bumps, a plurality of lower bonding wires to the wafer bonding The present invention further provides another device; (b) forming a plurality of conductive bumps with protrusions, and the bumps are bonded to the lower crystal with their bases) connecting a plurality of lower bonding wires by ball bonding to embossing Connect the other end to the application by bonding; (d) apply an adhesive layer to the positive side of the upper wafer and place the adhesive layer until it contacts the protruding portion of the lower wafer pad; (f) cure the adhesive layer; and (g) ) Connect the device used to carry the chip and the chip package structure of the upper layer of the chip to support the connection of the lower layer of the crystal bonding wire with a plurality of other! Adhesive ·. The layer is connected to the lower bonding pad of the connection. For the sake of clarity, the following detailed description b Ming said that the end of the piece is conductive and that the fresh line is touched, so that this article is as follows: The wafer wafer is fresh enough to be provided on the bumps and the wafer is conductively raised to the invention. The manufacturing method of the invention includes the following devices; (b) pads; (c) ball to carry the lower layer of the wafer The front side of the lower bonding wire of the wafer pad; (f) block; (g) the second preferred embodiment of the invention that is cured to carry the wafer. Multiple steps: (a) fixing the lower layer crystal to form a plurality of conductive protrusions in a bonding manner to connect the plurality Under the device, conductive protrusions on the embossed joint; (d) shaped embossed joint ends; (e) coating the upper wafer into the glue and the glue layer; and (h) connecting the complex device and the upper wafer. Crystal QS

片 上述和其他目的、特徵、和優點能更明 明較佳實施例，並配合所附圖示，作詳The above and other objects, features, and advantages will clarify the preferred embodiment, and will be described in detail with the accompanying drawings.

\\SEI!TER\backup\e瑋寻利申晴*\二堆條磉坑明書\P0O-049. phi 第8頁 442876 I 、 k、發明說明（6) ' j · i請參照第三圖，其揭示根據本發明第一較佳實施例移除 j封膠體後之多晶片封裝構造30〇，其主要包含兩半導體晶- |片310、320彼此堆疊安裝於一基板3 3〇 D該基板3 3〇具有一 |用以與外界形成電性連接之構造，其包含複數條導電引線 (|conductive lead)330a。該兩半導體晶片 310、320，各 i具有複數個晶片銲墊310a、320a設於其正面。該半導體晶 |月3 1 0之背面係利用一膠層（未示於圖中）設於該基板 - 冰30。該半導體晶片320之背面係利用一膠層340固著於該 |半導體晶片3 1 0之正面。該兩晶片間設有複數個導電凸胤 $50 ’其具有基部3 5 0 a以及柱狀突出部35〇b，該凸塊3 5 0以 j其基部350a接合於晶片310之晶片銲墊310a，並且以其柱 狀突出部3 5 0 b連接晶片3 2 0之底部以支撐該晶片3 2 0。該兩 晶片分別以銲線36 0、3 7 0電性連接至該基板3 3 0之導電引 線3 3 0 a。該銲線3 6 0之一端係以球接合方式（b a 1 1 bonding)連接至導電引線3 3 0a，另一端係以壓印接合方式 ^stitch bonding)連接至設於晶片銲塾310a上導電凸 含50之基部350a。該多晶片封裝構造300較佳包含一封ϋί! ! » 未示於圖中）包覆該晶片310、320 ，銲線360、370以及' _基板330之一部分〇 . 根據本發明之多晶片封裝構造330，由於該凸塊350之柱 狀突出部350a提供銲線360所需之空隙（clearance)，藉此 可防止晶片3 2 0損傷銲線3 6 0。值得注意的是’敦於兩晶片 間之複數個導電凸塊.3 5 Q係具有大致相同之高度’因此該 晶片3 2 0安裝後昇有良好之共平面性（c ο p 1 a n a r i t y)，藉此\\ SEI! TER \ backup \ eWei Xunli Shen Qing * \ Erdui Tiao Peng Hang Ming \ P0O-049. Phi p. 8 442876 I, k, description of the invention (6) 'j · i Please refer to the third Figure, which reveals the multi-chip package structure 30o after removing the j-sealing colloid according to the first preferred embodiment of the present invention, which mainly includes two semiconductor crystals-sheets 310, 320 are stacked on each other and mounted on a substrate 3 300D. The substrate 3 30 has a structure for forming an electrical connection with the outside, and includes a plurality of conductive leads 330a. Each of the two semiconductor wafers 310 and 320 has a plurality of wafer pads 310a and 320a provided on its front surface. The back of the semiconductor crystal | 10 is set on the substrate-ice 30 using an adhesive layer (not shown). The back surface of the semiconductor wafer 320 is fixed to the front surface of the semiconductor wafer 310 by an adhesive layer 340. A plurality of conductive bumps $ 50 ′ are provided between the two wafers, which have a base portion 350a and a columnar protruding portion 35b. The bumps 350 are bonded to a wafer pad 310a of the wafer 310 with a base portion 350a, And the columnar protruding portion 3 5 0 b is connected to the bottom of the wafer 3 2 0 to support the wafer 3 2 0. The two chips are electrically connected to the conductive leads 3 3 0 a of the substrate 3 3 0 by bonding wires 36 0 and 3 7 0 respectively. One end of the bonding wire 3 6 0 is connected to the conductive lead 3 3 0a by ball bonding (ba 1 1 bonding), and the other end is connected to the conductive bump provided on the wafer bonding pad 310a by stamp bonding (^ stitch bonding). Contains 50 base 350a. The multi-chip package structure 300 preferably includes a letter (!) (Not shown) covering the chips 310, 320, bonding wires 360, 370, and a portion of the substrate 330. The multi-chip package according to the present invention Structure 330, since the columnar protrusion 350a of the bump 350 provides the clearance required for the bonding wire 360, thereby preventing the wafer 320 from damaging the bonding wire 360. It is worth noting that 'a plurality of conductive bumps lingering between the two wafers. 3 5 Q series have approximately the same height'. Therefore, the wafer 3 2 0 has good coplanarity (c ο p 1 anarity) after installation Take this

\\SE(iVER\becku[>\^ ψ *VP〇〇-049i ptd 第 Q 頁 ί 4^2876 •i · · - · -. i !_： _-__ 4、發明說明⑺ ，~~ i增進該多晶片封裝構造3 00之可靠性。 ；請參照第四圖，其揭示根據本發明第二較佳實施例移除^ 丨 封膠體後之多晶片封裝構造4 00 ’其特徵在於該下層晶片 ;丨10之晶片銲墊310a設有導電突起（protuberance)380，其 辛該下層銲線360之一端係以球接合方式連接至該基板330 丨.之導電引線3 30a，另一端係以壓印接合方式連接至該導電 丨突起3 8 0。此外，諒兩晶片間亦設有複數個導電凸塊3 5 0位 於該銲線360之壓印接合端，並且連接至該晶片320之底部 丨 I以支撐該晶片3 2 0。可以理解的是，根據本發呀第二輕佳 j實施例之導電凸塊只需設置在晶片3 1 0的四個角落區域即 可提供銲線3 6 0所需之空隙（clearance)而防止晶片320損 傷銲線3 6 0 〇 第五圖至第七圖揭示一種根據本發明第一較佳實施例之 製造該多晶片封裝構造3 0 0之方法。 第五圖揭示晶片310利用一膠層（未示於圖中）固著於 該基板330。然後利用習用之球銲工具（bal 1 bonding iool )形成複數個導電凸塊350於晶片31 0之晶片銲墊 . .i 1 0a。該導電凸塊3 50之特徵在於其具有基部350a以及柱上 &突出部3 50b並且該凸塊3 5 0係以其基部接合於晶片錄塾 i 1 0 a »有關於該凸塊之形成技術細節請參照民國八十八年 |六月三十日申請之中華民國第88111228號專利申請案°該 基板330可由玻璃纖維強化BT (bismaleimide-tria^ine) 樹脂，或FR-4玻璃纖維強化環氧樹脂（fiberglass\\ SE (iVER \ becku [> \ ^ ψ * VP〇〇-049i ptd page Q 4 ^ 2876 • i · ·-·-. I! _: _-__ 4. Description of the invention ⑺, ~~ i to improve the reliability of the multi-chip package structure 3 00; please refer to the fourth figure, which reveals that the multi-chip package structure 4 00 'after removing the colloid according to the second preferred embodiment of the present invention is characterized by the Lower wafer; 10 wafer pad 310a is provided with a conductive protrusion 380, one end of the lower welding wire 360 is connected to the substrate 330 in a ball bonding manner, and the other end is 30a The embossing bonding method is connected to the conductive 丨 protrusion 3 8 0. In addition, it is understood that there are also a plurality of conductive bumps 3 5 0 located between the embossing bonding end of the bonding wire 360 and connected to the bottom of the chip 320丨 I to support the wafer 3 2 0. It can be understood that according to the second preferred embodiment of the present invention, the conductive bumps need only be provided at the four corner areas of the wafer 3 1 0 to provide bonding wires 3 6 0 required clearance to prevent the wafer 320 from damaging the bonding wires 3 6 0 〇 The fifth to seventh figures disclose a method according to the present invention A preferred embodiment of the method for manufacturing the multi-chip package structure 300. The fifth figure shows that the wafer 310 is fixed to the substrate 330 with an adhesive layer (not shown). Then, a conventional ball bonding tool ( bal 1 bonding iool) to form a plurality of conductive bumps 350 on the wafer pads of the wafer 3 0. .i 1 0a. The conductive bump 3 50 is characterized in that it has a base 350 a and a post & protrusion 3 50 b and the The bump 3 5 0 is bonded to the wafer with its base i 1 0 a »For details about the formation technology of the bump, please refer to the patent application of the Republic of China No. 88111228 filed on June 30. The substrate 330 can be made of glass fiber reinforced BT (bismaleimide-tria ^ ine) resin, or FR-4 glass fiber reinforced epoxy resin (fiberglass

Reinforced epoxy resin)製成之蕊層（core layer)形 ί 'Reinforced epoxy resin) core layer

WSEiVEKMrackmA合料利中二》條規说明*、剛-〇d9.Ptd 第10頁 4 42 816 i·、發明說明（8) 成。此外，該基板330亦可以是一陶農基板（ceramic substrate)。可以理解的是該基板330亦可以一導線架 lead frame)取代。該導線架一般係包含複數條導線且具 i有内腳部分（inner lead portion)以及外腳部分（outer |ead portion)，其中該内腳部分係用以電性連接至一晶 |月，該外腳部分係用以與外界電性連接》 ! 請參照第六圖，該銲線3 60之一端係利用球銲工具以球 I接合方式銲接於基板3 3 0之導電引線3 3 0a，其另一端係以 |壓印接合方式銲接至導電凸塊350之基部350a。該銲線36Q 敵佳係彎曲而大致形成一直角。 I請參照第七圖，該膠層340係先以點膠的方式塗佈在該 |晶片310之上表面’然後該晶片110再以貼晶片製程（chip ^ittachment )貼上。由於該將晶月3 2 0係置入該膠層34 0直 到接觸設於該晶片銲墊310a上導電凸塊350之柱狀突出部 3 5 0 a，因此只要控:制該凸塊.3 5 0之.高度.即可獲得一·穩定之 膠層厚度（bond line thickness)。因而晶月320安裝後不 |會引起共平面性（coplanarity)不良之問題，而且可保 pt.晶片3 2 0不會碰觸到銲線3 6 0 _之線弧藉此大幅增進其 ^生。該膠層340係為以熱固性環氧材料（thermosetting 〉 dpoxy mater i a 1 )[例如環氧樹脂（epoxy res in)、石夕樹脂 silicone)或聚醯胺（polyamide)]製成之不導電膠。 i請再參照第三圖’在膠層340固化後，該銲線3 7〇可以利 甩美國專利第5 73 5 0 3 0號揭示之打線方法形成。此外，亦 可利用習知的打線技術在晶片銲墊32〇a與導電引線3 3 0a間WSEiVEKMrackmA Blending Lizhong 2 "Regulations *, Gang-〇d9.Ptd Page 10 4 42 816 i ·, Description of Invention (8). In addition, the substrate 330 may also be a ceramic substrate. It can be understood that the substrate 330 can also be replaced by a lead frame. The lead frame generally includes a plurality of wires and has an inner lead portion and an outer leg portion. The inner leg portion is used to be electrically connected to a crystal | month. The outer leg part is for electrical connection with the outside world! Please refer to the sixth figure. One end of the bonding wire 3 60 is soldered to the conductive lead 3 3 0a of the substrate 3 3 0 by a ball bonding method using a ball bonding tool. The other end is soldered to the base 350a of the conductive bump 350 in an embossed joint. This bonding wire 36Q Dijia is bent to form a substantially right angle. Please refer to the seventh figure. The adhesive layer 340 is firstly applied on the top surface of the wafer 310 by dispensing, and then the wafer 110 is pasted by a chip ^ ittachment. Since the crystal moon 3 2 0 is placed in the adhesive layer 3 40 until it contacts the columnar protrusion 3 5 0 a of the conductive bump 350 provided on the wafer pad 310 a, as long as the bump is controlled: 3 A height of 50 to obtain a stable bond line thickness. Therefore, after the installation of Jingyue 320, it will cause the problem of poor coplanarity, and it can ensure that the pt. Wafer 3 2 0 will not touch the bonding wire 3 6 0 _, thereby greatly improving its health. . The adhesive layer 340 is a non-conductive adhesive made of a thermosetting epoxy material (thermosetting> dpoxy mater i a 1) [for example, epoxy res in, stone resin, or polyamide]. Please refer to the third figure again. 'After the adhesive layer 340 is cured, the bonding wire 3 700 can be formed by using the wire bonding method disclosed in U.S. Patent No. 5,73,500,300. In addition, the conventional bonding technology can also be used between the die pad 32a and the conductive lead 3 3 0a.

44^8 7 6_ ， 兰、發明說明（9) ' .形成銲線連接（wire interconnection)，亦即先形成一球 接合（ball bond)於晶片銲墊320a，然後形成線弧於晶片-銲墊3 2 0 a與基板3 3 0之導電引線330a間，最後再壓印接合 <:st i tch bond)至導電引線3 3 0 a。 第八圖至第十圖揭示一種根據本發明第二較佳實施例之 製造該多晶片封裝構造400之方法。 . .第八圖揭不晶片310利用一攀層（未示於圖中）固著於 該基板3 30 »然後利用美國專利第5735030號揭示之打線方 I法，先形成複數個導電突起3 8 0於該晶片3 1 0之晶片銲墊 3 1 〇a，再以球接合方式連接該銲線3 6 0之一端至該基板3 30 |之導電引線3 3 0a，並以壓印接合方式連接其另一端至設於 |晶片銲墊3 1 0a上之導電突起380。該銲線3 60較佳係彎曲而 I大致形成一直角》 |請參照第九圖，複數個導電凸塊3 50係利用習用之球銲 i工具形成於銲線3 60之壓印接合端。有關於該凸塊3 50之形 I成技術細節請參照民國八十八年六月三十日申請之中華民 國第8 8 Π 1 2 2 8號專利申請案。此外，亦可利用民國八十八 年十一月九日申請之中華民國第8 81 19267號專利 示之技術形成複數個導電凸塊於銲線3 6 0之壓印接―合端π二 i根據本發明第二較佳實施例之導電凸塊只需設置在晶片的 |四個角落區域即可提供下層銲線所需之空隙（clearance) |而防止上層晶片損傷下層晶片之.銲線》 !請參照第十圖，該膠層340係先以點膠的方式塗佈在該 I晶片31 0之上表面，然後該晶片3 2 0再以貼晶片製程（chip 144 ^ 8 7 6_, Lan, invention description (9) '. Form a wire interconnection, that is, first form a ball bond on the wafer pad 320a, and then form a wire arc on the wafer-pad Between 3 2 0 a and the conductive lead 330a of the substrate 3 3 0, finally, the bonding <: st i tch bond) is embossed to the conductive lead 3 3 0 a. Figures 8 through 10 illustrate a method of manufacturing the multi-chip package structure 400 according to a second preferred embodiment of the present invention. The eighth picture shows that the chip 310 is fixed to the substrate 3 using a climbing layer (not shown in the figure). Then, using the wire bonding method I disclosed in US Patent No. 5,735,030, a plurality of conductive protrusions 3 8 are formed first. 0 on the wafer pad 3 1 0a of the wafer 3 1 0, and then one end of the bonding wire 3 6 0 is connected to the conductive lead 3 3 0a of the substrate 3 30 by ball bonding, and connected by imprint bonding The other end is to the conductive protrusion 380 provided on the wafer pad 3 1 0a. The bonding wire 3 60 is preferably bent and I forms a substantially right angle. Please refer to the ninth figure. A plurality of conductive bumps 3 50 are formed on the embossed joint end of the bonding wire 3 60 by using a conventional ball bonding i tool. For the technical details of the formation of the bumps 3 50, please refer to the Republic of China Patent Application No. 8 8 Π 1 2 28, which was filed on June 30, 1988. In addition, the technology shown in the Republic of China No. 8 81 19267 filed on November 9, 1998 can be used to form a plurality of conductive bumps on the welding wire 3 6 0-joint end π 2i The conductive bumps according to the second preferred embodiment of the present invention only need to be provided in the four corner areas of the wafer to provide the clearance required for the lower bonding wire, and prevent the upper wafer from damaging the lower wafer. Please refer to the tenth figure. The adhesive layer 340 is firstly applied on the top surface of the I wafer 3 1 0 by dispensing, and then the wafer 3 2 0 is processed by a chip bonding process (chip 1).

-4---:- VASiRTCR'ilwckup、台灣專利中 tj·索\二球條碼說明，\p〇〇- 〇49. ptd 第12頁 44g876 耳、發明說明（10) ' ! Attachment )貼上。 請參照第--圖以及第十二圖*根據美國專利第 + 735030號揭示之打線方法，當銲線2 20之一端壓印接合至 i晶片銲墊210上的導電突起200後，其所形成之連接構造係 i大致呈水平狀，因:而無.法幫助提供，鮮線220所需之空隙’ (^clearance)。相對地’根據本發明，當鲜線36〇之一端壓 i印接合至晶片銲塾310上的導電凸塊350後’其所形成之連 構造具有一柱狀突出部350b，藉此提供銲線360所需之 i空隙（clearance) 〇 I * j綜上所述’根據本發明之多晶片堆疊封裝構造特徵在於 j晶片間設有複數個導電凸塊’其可在晶片間提供空隙以防 I止上層晶片損傷下層晶片之銲線。此外，藉由控制該凸塊 I之高度即可獲得一穩定之膠層厚度（bond u J 4 . . v m I cs ,, ne (UopUnarity)不良之問題Λ裝後不會…起共平面性 thickness) 因而 I雖然本發明已以前述較佳實施例揭示1其並㈣以限 丨定本發明，任何熟習此技藝者，力 範圍内，當可作各種之更勒離本發 園當視後附之申請專利範圏所&定去，此本發教壹纪襄 々严心馬準。-4 ---:-VASiRTCR'ilwckup, Taiwan patent in tj · suo \ two-ball bar code description, \ p〇〇- 〇49. Ptd page 12 44g876 ear, invention description (10) '! Attachment). Please refer to Figures-and Twelve Figures * According to the wire bonding method disclosed in US Patent No. +735030, when one end of the bonding wire 2 20 is imprinted and bonded to the conductive protrusion 200 on the i-chip pad 210, it is formed The connection structure i is roughly horizontal because there is no way to help provide the clearance required for the fresh line 220 '(^ clearance). In contrast, according to the present invention, when one end of the fresh wire 36 is imprinted and bonded to the conductive bump 350 on the wafer paddle 310, the connected structure has a columnar protrusion 350b, thereby providing a bonding wire. Clearance required for 360 ° I * j In summary, the 'multi-chip stacked package structure according to the present invention is characterized in that a plurality of conductive bumps are provided between the wafers', which can provide spaces between the wafers to prevent I Prevent the upper wafer from damaging the bonding wires of the lower wafer. In addition, by controlling the height of the bump I, a stable glue layer thickness (bond u J 4.. Vm I cs ,, ne (UopUnarity) is not good. After installation, it will not… cause coplanarity thicknessness. ) Therefore, although the present invention has been disclosed with the foregoing preferred embodiments, and it is not limited to the present invention, anyone skilled in the art can, within the scope of his power, make various modifications to the present park. The applicant for the patent application & is scheduled to go.

VSSepVmbackup1^漕尊利f請索\二緣條馮說明會NP00-O49. ptd 第丨3頁 44S876 ，式簡單說明 i圖示說明： 丨第 1 圖 : 習 知 多 晶 片 封 裝 構 造 之 剖 面圖； 卜第 J 2 圖 其 係 用 以 說 明 美 國 專 利 第5735030號揭示之打 丨線方 法 9 丨第 j 3 圖 • 根 據 本 發 明 第 m. 較 佳 實 施 例之多晶 片封裝構造 移除 封 膠 體後 之 剖 示 圖 丨第 4 圖 • 根 據 本 發 明 第 二 較 佳 實 施 例之多晶 片封裝構造 '岭除 封 膠 體 後 之 剖 示 圖 > ;第 5 圖 至 第 7 圖 其 係 用 以 說 明 根 據本發明 第3圖多晶 i片封 裝 構 造 之 製 造 方 法 丨第 8 圖 至 第 1 0 圖 • 其 係 用 以 說 明 根據本發 明第4圖多 丨晶片 封 裝 構 造 之 製 造 方 法 '第 1 1 圓 .· 其 係 為 一 放 大 立 體 圖 用 以說明根 據本發明之 導電 凸 塊 以 及 一 銲 線 以 端 壓 印 接 合於另一 凸塊；及 第 1 2 圖 * 其 係 為 W 放 大 立 體 圖 用 以說明根 據美國專利 i第5 7 3 5 0 3 0號揭示之導電突起 ，以及- -銲線以- -端壓印 命於 另 _ 1 — 突 起 0 圖號 說 明 * 丨1 1 0 [ 晶 1 20 基 板 130 晶片 i 140 膠 層 1 50 銲 線 200 突起 丨210 晶 >1 銲 墊 220 銲 線 230 基板銲墊 300 多 晶 片 封 裝 構 造 310 晶 片 ! 31 0< a 晶 片 銲 墊 320 晶 片 3 2 0 a 晶片鲜塾VSSepVmbackup1 ^ 漕 Zhongli f please ask \ Two margin article Feng explanation meeting NP00-O49. Ptd 44S876 on page 丨 3, the simple description i illustrates: 丨 Figure 1: Sectional view of the known multi-chip package structure; Figure J 2 is a diagram illustrating the wiring method 9 disclosed in U.S. Patent No. 5,735,030. Figure j 3 is a cross-sectional view of the multi-chip package structure according to the m. Preferred embodiment of the present invention after the sealing compound is removed.丨 FIG. 4 • A cross-sectional view of a multi-chip package structure according to the second preferred embodiment of the present invention after removing the sealing compound >; FIGS. 5 to 7 are diagrams for explaining the third figure according to the present invention Manufacturing method of polycrystalline i-chip package structure 丨 Figure 8 to Figure 10 · This is used to explain the manufacturing method of the multi-chip package structure according to Figure 4 of the present invention '1st circle. It is an enlargement A perspective view for illustrating the conductive bumps and a bonding wire according to the present invention are embossed with ends. And attached to another bump; and FIG. 12 is an enlarged perspective view of W for illustrating a conductive protrusion disclosed in US Patent No. 5 7 3 5 0 3 0, and--bonding wire with--end pressure Destined for another _ 1 — protrusion 0 Description of drawing number * 丨 1 1 0 [crystal 1 20 substrate 130 wafer i 140 adhesive layer 1 50 bonding wire 200 projection 丨 210 crystal> 1 bonding pad 220 bonding wire 230 substrate bonding pad 300 Multi-chip package structure 310 chips! 31 0 < a chip pad 320 chip 3 2 0 a chip fresh

\\S^TER\bacln«A台灣專利申請索\二雄條碼说明ρΐιΐ 第14頁 442876\\ S ^ TER \ bacln «A Taiwan Patent Application Claim \ Erxiong Barcode Instructions ρΐιΐ Page 14 442876

Claims (1)

i 442876 六、申請專利範圍 其係包 i 、一種多晶片封裝構造（multichip module 含： 用以承載晶片之裝置，其設有導電引線； 第一晶片，設於譎用以承載晶片之裝置，該第一晶片 具有複數個晶片銲墊設於其正面； 第二晶片，位於該第一晶片上方，該第二晶片具有複 數個晶片銲墊設於其正面； 複數個導電凸塊，其具有基部.以及柱狀突_出部，該凸 塊以其基部接合於第一晶片之晶片銲墊，並且以其柱狀突 出_部連接該第二晶片之底部以支樓該第二晶片，一勝層設 於該第一晶片與第二晶片之間；複數條第一銲線，其一端 以球接合方式（ballbonding)連接至該導電引線，其另一 端以壓印接合方式（stitch bonding)連接至第一晶片銲塾 上導電凸塊之基部；及 複數條第二銲線，其連接該導電引線至第二晶片銲 塾， 糜 其中該凸塊之柱狀突出部係有助於提供第一銲線所需 之空隙（clearance)。 2、 依申請專利範園第1項之多晶片封裝構造，其另包含 一封膠體包覆該第一、第二晶月，該第一、第二銲線以及 該用以承載晶片之裝置的一部分。 3、 依申請專利範圍第1項之多晶片封裝構造，其中該第一 銲線係彎曲而大致形成一直角。 4、 依申請專利範圍第1項之多晶片封裝構造，其中該膠層i 442876 VI. The scope of patent application is package i. A multi-chip package structure (multichip module includes: a device for carrying a chip, which is provided with conductive leads; a first chip, which is provided in a device for carrying a chip, the The first wafer has a plurality of wafer pads disposed on its front surface; the second wafer is located above the first wafer, the second wafer has a plurality of wafer pads disposed on its front surface; a plurality of conductive bumps having a base. And a columnar protrusion, the bump is bonded to the wafer pad of the first wafer by its base, and the bottom of the second wafer is connected by its columnar protrusion, to support the second wafer, a victory layer Is provided between the first chip and the second chip; one end of the plurality of first bonding wires is connected to the conductive lead by ball bonding, and the other end is connected to the first lead by stitch bonding The base of a conductive bump on a wafer pad; and a plurality of second bonding wires connecting the conductive lead to the second wafer pad, wherein the columnar protrusions of the bump are helpful to provide the first Clearance required for wires. 2. The multi-chip package structure according to item 1 of the patent application park, which further includes a gel covering the first and second crystal moons, and the first and second bonding wires. And a part of the device for carrying a wafer. 3. The multi-chip package structure according to item 1 of the patent application scope, wherein the first bonding wire is bent to form a substantially right angle. 4. According to item 1 of the patent application scope Multi-chip package structure, wherein the adhesive layer V\SERVER\backup\台灣專利中1奢衆\二雎條碼說叨*\P0O-0<iS.ptd 第？.6頁 442876 六 係. 5 銲 壓 6 承 7 含 申請專利範圍 為不導電膠。 、依申請專利範圍第1項之多晶片封裝構造 線之一端以球接合方式連接至該導電引線 印接合方式連接至第二晶片上之晶片銲墊 、依申請專利範圍第1項之多晶片封裝構造 載晶片之裝置係為一基板或一導線架。 * 一種多晶片封裝構造（multichip module 其中該第二 其另一端以 其中談用以 ，其係包 用以承載晶片之裝置，其設有導電引線； 具 數 引 導 且 墊 第一晶片，設於該用以承載晶片之裝置，該第一晶片 有複數個晶片銲墊設於其正面； 第二晶片，位於該第一晶片上方，該第二晶片具有複 個晶片銲墊設於其正面； 複數個導電突起設於該第^晶片之晶Ji銲墊； 卽 複數條第一銲線，其一端以球接合方式連接至該導電 線，其另一端以壓印接合方式連接至第一晶片銲墊上之 電突起； 複數個導電凸塊，設於該第一銲線之壓印接合端，並ϋ 連接至該_第二晶片之底部以支撐該第二晶片， 一膠層設於該第一晶片與第二晶片之間；及 複數條第二銲線，其連接該導電引線至第二晶片銲 J 其中該導電凸塊係有助於提供第一銲線所需之空隙。 依申請專利範圍第7項之多晶片封裝構造，其另包含-V \ SERVER \ backup \ Taiwan Patent 1 Luxe \ II 雎 Barcode says 叨 * \ P0O-0 < iS.ptd No? Page 6 442876 Six series. 5 Welding pressure 6 bearing 7 inclusive Patent application scope is non-conductive glue. 1. One end of the multi-chip package construction line according to item 1 of the scope of the patent application is connected to the conductive pads on the second die by ball bonding, and the multi-chip package according to item 1 of the scope of patent application The device for constructing the wafer is a substrate or a lead frame. * A multichip package structure (multichip module in which the other end is used to talk about it, it is a device for carrying a chip, which is provided with conductive leads; a number of guides and pads of the first chip are provided in the A device for carrying a wafer, the first wafer has a plurality of wafer pads disposed on the front surface thereof; the second wafer is located above the first wafer, and the second wafer has a plurality of wafer pads disposed on the front surface thereof; A conductive protrusion is provided on the crystal pad of the first wafer; 卽 a plurality of first bonding wires, one end of which is connected to the conductive wire by ball bonding, and the other end of which is connected to the first wafer bonding pad by imprint bonding. Electrical protrusions; a plurality of conductive bumps are provided on the embossed joint end of the first bonding wire, and are connected to the bottom of the second wafer to support the second wafer, and an adhesive layer is provided on the first wafer and Between the second wafers; and a plurality of second bonding wires connecting the conductive leads to the second wafer bonding J, wherein the conductive bumps help to provide the gap required for the first bonding wires. Xiangzhi Multi-chip package structure, which further includes- \\SERVES\badwp\台灣專利申讀窠\二維條场說明書\?00-0494士(1 第17頁 4428 7 θ 六、申請專利範圍 第二銲線以及該 封膠體包覆該第一、第二晶片，該第一 用以承載晶片之裝置的一部分。 9、依申請專利範圍第7項之多晶片封裝構造，其中該複數 個導電ώ塊具有基部以及柱狀突出部，該凸塊以其基部接 • · _. ,丨. 合於第一銲線之壓印接合端，並且以其柱狀突出部連接該 第'一晶片之底部。 1 0、依申請專利範圍第7項之多晶片封裝構造，其中該第 一鲜線係彎曲而大致形成一直角。 其中該膠 其中該第 其另一蟑 I 其中該用 1 1 、依申請專利範圍第7項之多晶片封裝構造 層係為不導電膠。 1 2、依申請專利範圍第7項之多晶片封裝構造 二銲線之一端以球接合方式連接至該導電引線 以壓印接合方式連接至第二晶片上之晶片銲墊 1 3、依申請專利範圍第7項之多晶片封裝構造 以承載晶片之裝置係為一基板或一導線架。 14、_種多晶片封裝構造製造方法，其包含下列步驟： 固定第一晶片至一用以承載晶片之裝置，該第一晶片 具有複數個晶片銲墊設於其正面，該用以承载晶片之裝置 設有導電引線； 形.成複數個導電凸塊，其具有基部以及柱狀突出部， 該凸塊.以其基部接合於第一晶片之晶片銲墊; 以球接合方式連接複數條第一銲線之一端於該導電引 線，以壓印接合方式連接其另一端至第一晶片銲墊上導電 凸塊之基部；\\ SERVES \ badwp \ Taiwan patent application reading \ Two-dimensional strip specification \ 00-0494 士 (1 page 17 4428 7 θ VI. Patent application scope second welding wire and the sealing gel covering the first, The second chip is a part of the first device for carrying the chip. 9. The multi-chip package structure according to item 7 of the patent application scope, wherein the plurality of conductive blocks have a base portion and a columnar protruding portion, and the protruding portion is Its base is connected to the imprinted joint end of the first bonding wire, and its column-shaped protrusion is connected to the bottom of the first chip. 10, according to item 7 of the scope of patent application The chip package structure, in which the first fresh wire is bent to form a substantially right angle. Among the glue, the first and second cockroaches I, which should be used 1 1, and the multi-chip package structure layer according to item 7 of the patent application scope is Non-conductive adhesive 1 2. According to the multi-chip package structure No. 7 of the patent application scope, one end of the bonding wire is connected to the conductive wire by ball bonding, and the bonding pad of the second chip is connected by embossing. 3 As many chips as the scope of patent application No. 7 The device for carrying a package in a package structure is a substrate or a lead frame. 14. A method for manufacturing a multi-chip package structure includes the following steps: Fixing a first wafer to a device for carrying a wafer, the first wafer has A plurality of wafer pads are provided on the front side, and the device for carrying the wafer is provided with conductive leads; formed into a plurality of conductive bumps having a base portion and a columnar protruding portion, and the bumps are bonded to the first portion by the base portion. A wafer pad of a wafer; one end of the plurality of first bonding wires is connected to the conductive lead by ball bonding, and the other end thereof is connected to the base of the conductive bump on the first wafer pad by imprint bonding; 、\SERVER\backup\台灣專利申請*\二維條碼耽明書\?00-049. ptd 第18頁 442876 申請專利範園 塗佈一膠層於該第一晶片之正面； 提供一第二晶片，其具有複數個晶月銲墊設於其正 面 I 電 ΘΗ 15 其 該 16 其 17 其 18 其 其 19 其 20 具 設 將第二晶片置入該膠層直到接觸該第一晶片銲墊上導 凸塊之柱狀突出部； 固化該膠層；及 連接複數條第二銲線至該導電引線以及第二晶片上之 片銲墊。 〇 、依申請專利範圍第1 4項之多晶片封裝構造製造方法， 另包含包覆該第一、第二晶片，該第一、第二銲線以及 用以承載晶片之裝置的一部分於一封膠體内之步驟。 、依申請專利範圍第1 4項之多晶片封裝構造製造方法， 中該第一銲線係臀曲而大致形成一直.角。 、佟申請專利範圍第1 4項之多晶片封裝構造製造方法， 中該膠層係為不導電膠。 、依申請專利範圍第1 4項之多晶片封裝構造製造方法， 中該第二銲線之一端以球接合方式連接至該導電引線， 另一端以壓印接合方式連接至第二晶片上之晶片銲墊 、依申請專利範圍第1 4項之多晶片封裝構造製造方法 中該用以承載晶片之裝置係為一基板或一導線架。 、一種多晶爿封裝構追装造万法，其包古下列少_ : 固定第一晶片至一用以承载晶片之裝置，該第一晶片 有複數個晶片銲墊設於其正面，該用以承載晶片之裝置 有導電引線；、 \ SERVER \ backup \ Taiwan patent application * \ Two-dimensional barcode delay specification \? 00-049. Ptd page 18 442876 Apply for a patent Fan Yuan applies an adhesive layer on the front side of the first wafer; provides a second wafer It has a plurality of crystal moon pads on its front surface. I Θ Η 15, 16, 17, 18, 19, 20, and 20. The second wafer is placed in the adhesive layer until it contacts the first wafer pad to be convex. A columnar protruding portion of the block; curing the adhesive layer; and connecting a plurality of second bonding wires to the conductive lead and a bonding pad on the second wafer. 〇 The method for manufacturing a multi-chip package structure according to item 14 of the scope of patent application, further comprising enclosing the first and second wafers, the first and second bonding wires, and a part of the device for carrying the wafers in a single piece. Steps in the colloid. According to the method for manufacturing a multi-chip package structure according to item 14 of the scope of the patent application, in which the first bonding wire is bent at the hip to form a substantially straight angle. 2. The method for manufacturing a multi-chip package structure according to item 14 of the patent application, wherein the adhesive layer is a non-conductive adhesive. According to the method for manufacturing a multi-chip package structure according to item 14 of the scope of the patent application, one end of the second bonding wire is connected to the conductive lead by ball bonding, and the other end is connected to the wafer on the second chip by imprint bonding. In the method for manufacturing a multi-chip package structure according to Item 14 of the application for a bonding pad, the device for carrying a chip is a substrate or a lead frame. A method for retrofitting a polycrystalline silicon package structure, including the following: _ Fixing a first wafer to a device for carrying the wafer. The first wafer has a plurality of wafer pads on its front surface. The device carrying the wafer has conductive leads; \\SERVER\baclrtjp、台灣專利咿请*\二维條鸡說明當\P0fl-049. ptd 第19頁 442876 六、申請專利範圍' 形成複數個導電突起於該第一晶片冬晶片銲塾； 以球接合方式連接複數條第一銲線之一端至該導電引 線，以壓印接合方式連接其另一端至第一晶片銲墊上之導 電突起； 形成複數個導電凸塊於該第一銲線之壓印接合端； 塗佈一膠層於該第一晶片之正面； μ供一第二晶片'，ϋΛ有複數個晶片銲墊設於其正 面； 將第二晶片置入該膠層直到接觸該導電凸塊； 固化該膠層；及 連接複數條第二銲線至該導電引線以及第二晶片上之 晶片銲墊。. 21 、依申請專利範圍第2 0項之多晶片封裝構造製造方法， 其另包含包覆該第一、第二晶片，該第一、第二銲線以及 該用以承載晶片之裝置的一部分於一封醪體内之步驟。 2 2、依申請專利範圍第2 0項之多晶片封裝構造製造方法， 其中該複數個導電凸塊具有基部以及柱狀突出部，該凸塊 以其基部接合於第一銲線之壓印接合端，並且以其柱狀繁^ 出部連接該第二晶片之底部=> ^ 2 3、依申請專利範圍第2 0項之多晶片封裝構造製造方法， 其中該第一銲線係彎曲而大致形成一直角。 2 4、依申請專利範圍第2 0項之多晶 >；封裝構造製造方法， 其中該膠層係為不導電膠。 2 5、依申請專利範圍第2 0項之多晶片封裝構造製造方法，\\ SERVER \ baclrtjp, Taiwan patent 咿 Please * \ Two-dimensional bar chicken description \ P0fl-049. Ptd page 19 442876 VI. Application scope of patents' Forming a plurality of conductive protrusions on the first wafer winter wafer solder joint; Ball bonding is used to connect one end of the plurality of first bonding wires to the conductive lead, and embossing bonding is used to connect the other end to the conductive protrusion on the first wafer pad; forming a plurality of conductive bumps on the pressure of the first bonding wire Print the bonding end; apply an adhesive layer on the front side of the first wafer; μ for a second wafer, there are a plurality of wafer pads on the front side; place the second wafer in the adhesive layer until it contacts the conductive A bump; curing the adhesive layer; and connecting a plurality of second bonding wires to the conductive lead and a wafer pad on the second wafer. 21. The method for manufacturing a multi-chip package structure according to item 20 of the scope of patent application, which further includes covering the first and second chips, the first and second bonding wires, and a part of the device for carrying the chip. Steps inside a letter. 2 2. The manufacturing method of a multi-chip package structure according to item 20 of the scope of the patent application, wherein the plurality of conductive bumps have a base and a columnar protrusion, and the bump is bonded to the first bonding wire by an embossed joint. End, and connected to the bottom of the second chip with its columnar fan-out part = > ^ 2 3. According to the multi-chip package structure manufacturing method of claim 20 in the patent application scope, wherein the first bonding wire is bent and Roughly forming a right angle. 24. Polycrystalline according to item 20 of the scope of patent application > Manufacturing method of packaging structure, wherein the adhesive layer is a non-conductive adhesive. 2 5. Manufacturing method of multi-chip package structure according to item 20 of the scope of patent application, 八SSRVER\badwp\台灣摹到申婧索\二维碼说明書、Ρ00-&49· ptd 第20頁 $4^876 六'申請專利範圍 其中該第二銲線之一端以球接合方式連接至該導電引線 其另一端以壓印接合方式連接至第二晶片上之晶片銲墊 2 6、依申請專利範圍第2 0項之多晶片封裝構造製造方法 其中該用以承載晶片之裝置係為一基板或一導線架。Eight SSRVER \ badwp \ Taiwan 摹 to Shen Jingsuo \ Two-dimensional code manual, P00- & 49 · ptd Page 20 $ 4 ^ 876 Six 'application for patent scope where one end of the second wire is connected to The other end of the conductive lead is connected to the die pad on the second die by means of embossing bonding. 6. The manufacturing method of a multi-die package structure according to item 20 of the patent application scope, wherein the device for carrying the die is a A substrate or a lead frame. VvSERVmbadniiA 台 W 專对 於二睢條碼《明 ptil 91VvSERVmbadniiA Taiwan W is dedicated to the second bar code "Ming ptil 91
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7285864B2 (en) 2004-02-13 2007-10-23 Kabushiki Kaisha Toshiba Stack MCP
US7394147B2 (en) 2004-05-05 2008-07-01 Orient Semiconductor Electronics, Limited Semiconductor package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7285864B2 (en) 2004-02-13 2007-10-23 Kabushiki Kaisha Toshiba Stack MCP
US7482695B2 (en) 2004-02-13 2009-01-27 Kabushiki Kaisha Toshiba Stack MCP and manufacturing method thereof
US7833836B2 (en) 2004-02-13 2010-11-16 Kabushiki Kaisha Toshiba Stack MCP and manufacturing method thereof
US7394147B2 (en) 2004-05-05 2008-07-01 Orient Semiconductor Electronics, Limited Semiconductor package

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