JPH0778934A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH0778934A
JPH0778934A JP22119593A JP22119593A JPH0778934A JP H0778934 A JPH0778934 A JP H0778934A JP 22119593 A JP22119593 A JP 22119593A JP 22119593 A JP22119593 A JP 22119593A JP H0778934 A JPH0778934 A JP H0778934A
Authority
JP
Japan
Prior art keywords
wiring board
needle
semiconductor device
semiconductor
semiconductor elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22119593A
Other languages
Japanese (ja)
Inventor
Tadaaki Mimura
忠昭 三村
Kenzo Hatada
賢造 畑田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP22119593A priority Critical patent/JPH0778934A/en
Publication of JPH0778934A publication Critical patent/JPH0778934A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the mounting efficiency and packing density of a semiconductor device and, at the same time, to simplify the manufacturing process of the semiconductor device. CONSTITUTION:A semiconductor device is provided with multiple semiconductor elements 1, laminated at intervals, wiring boards 2 provided along the lateral side faces of the elements l, electrodes provided on the surface of each element 1, and needle-shaped terminals 3 projected from the substrates 2 and connected to the electrodes 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、複数の半導体素子を
3次元的にスタックしてなる半導体装置およびその製造
方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of semiconductor elements are three-dimensionally stacked and a manufacturing method thereof.

【0002】[0002]

【従来の技術】近年、複数の半導体素子を1枚の配線基
板上に実装して1つの機能ブロックを構成する、マルチ
チップモジュール(MCM)が、システムの性能向上
(高速動作,高機能動作)、小型,軽量化を進める上で
の有効な手段として、盛んに開発がなされている。特
に、機器の小型化を図るために、半導体素子を3次元的
に積み重ねた実装構成に関して、例えば、トムソン社か
ら開発がなされている(91,92 Proceedings of symposi
um on ISHM) この技術は、ベアチップ、あるいはTSOPパッケージ
を一旦ワイヤーボンドでテープキャリアに接続し、これ
を積み重ねて全体を樹脂モールドし、モールドの外部で
相互接続を行うものである。
2. Description of the Related Art In recent years, a multi-chip module (MCM) in which a plurality of semiconductor elements are mounted on one wiring board to form one functional block has improved system performance (high-speed operation, high-function operation). , Has been actively developed as an effective means for promoting miniaturization and weight reduction. In particular, a mounting structure in which semiconductor elements are three-dimensionally stacked in order to reduce the size of the device has been developed by, for example, Thomson (91,92 Proceedings of symposi).
um on ISHM) In this technology, bare chips or TSOP packages are once connected to a tape carrier by wire bonds, these are stacked and the whole is resin-molded, and interconnection is performed outside the mold.

【0003】また、メモリ等の半導体素子をTAB技術
でテープキャリアに接続し、これを適当な間隔で積み重
ねて、外部リードをフォーミング加工し、ボード上に接
続する方法も開発されている。
A method has also been developed in which semiconductor elements such as a memory are connected to a tape carrier by the TAB technique, the tape carriers are stacked at appropriate intervals, and external leads are formed and connected on a board.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、従来の
テープキャリアを介する実装方法では、チップサイズに
対してかなりの実装領域を必要とするため、実装効率が
悪く、3次元的にスタックしたことによる実装密度の向
上が制限されるという問題がある。また、製造工程も複
雑となるため、材料コスト,製造コストも上昇してしま
うという問題がある。
However, the conventional mounting method using a tape carrier requires a considerable mounting area with respect to the chip size, so that the mounting efficiency is poor and the mounting is performed by stacking three-dimensionally. There is a problem that the increase in density is limited. Further, since the manufacturing process becomes complicated, there is a problem that the material cost and the manufacturing cost also increase.

【0005】この発明の目的は、実装効率ならびに実装
密度の向上が図れ、かつ製造工程の簡略化が図れる半導
体装置およびその製造方法を提供することである。
An object of the present invention is to provide a semiconductor device and a method of manufacturing the same which can improve the mounting efficiency and the mounting density and can simplify the manufacturing process.

【0006】[0006]

【課題を解決するための手段】この発明の半導体装置
は、互いに間隔を開けて積層した複数の半導体素子と、
これら各半導体素子の側端面に沿って設けた配線基板
と、各半導体素子の表面に設けた電極と、配線基板に突
設するとともに電極に接続した針状端子とを備えたもの
である。
A semiconductor device according to the present invention comprises a plurality of semiconductor elements stacked at intervals.
A wiring board provided along the side end faces of each of these semiconductor elements, an electrode provided on the surface of each semiconductor element, and a needle terminal protruding from the wiring board and connected to the electrode.

【0007】電極は、半導体素子の表面の端縁に並設し
た電極群からなり、これら電極群に対応して針状端子群
を配線基板に突設したものでもよい。各針状端子は、配
線基板の外面に形成された半導体素子間を接続する相互
配線パターンに接続されて、配線基板に貫通して設けら
れている。また、電極と針状端子が、ハンダバンプによ
り接続されているものでもよい。
The electrodes are composed of electrode groups arranged side by side on the edge of the surface of the semiconductor element, and needle-like terminal groups may be provided on the wiring board so as to correspond to these electrode groups. Each needle terminal is connected to an interconnection pattern formed between the semiconductor elements formed on the outer surface of the wiring board, and is provided so as to penetrate the wiring board. Further, the electrodes and the needle terminals may be connected by solder bumps.

【0008】さらに、半導体素子の裏面に、弾性絶縁膜
を形成してもよい。この発明の半導体装置の製造方法
は、各々表面に電極を設けた複数の半導体素子を所定の
間隔を開けて積層し、各電極に対応する針状端子を突設
した配線基板を各半導体素子の側端面に沿って設け、各
針状端子がそれぞれ対応する電極に重なるように配線基
板を位置決めし、積層した半導体素子の上下より加圧し
て針状端子と電極を接続するものである。
Further, an elastic insulating film may be formed on the back surface of the semiconductor element. According to the method of manufacturing a semiconductor device of the present invention, a plurality of semiconductor elements each having an electrode on the surface thereof are laminated at a predetermined interval, and a wiring board having a needle-shaped terminal corresponding to each electrode is projected from each semiconductor element. The wiring board is provided along the side end face, the wiring board is positioned so that the needle terminals overlap the corresponding electrodes, and the needle terminals are connected to the electrodes by applying pressure from above and below the stacked semiconductor elements.

【0009】[0009]

【作用】この発明の半導体装置およびその製造方法によ
ると、複数の半導体素子を積層した実装構造であるた
め、実装密度を大幅に高めることができる。また、半導
体素子間の相互配線は、側端面に配置した配線基板にて
行うため、非常に実装効率の良い配線ができる。さら
に、半導体素子の電極との接続は、配線基板に形成した
針状端子との接触、あるいはハンダバンプにて行うた
め、比較的簡易に接続することができ、製造工程の簡略
化が図れる。
According to the semiconductor device and the method of manufacturing the same of the present invention, since the mounting structure is formed by stacking a plurality of semiconductor elements, the mounting density can be significantly increased. Moreover, since interconnection between the semiconductor elements is performed by the wiring board arranged on the side end face, wiring with extremely high mounting efficiency can be performed. Further, since the connection with the electrode of the semiconductor element is made by contact with the needle-like terminal formed on the wiring board or by solder bump, the connection can be made relatively easily and the manufacturing process can be simplified.

【0010】[0010]

【実施例】この発明の一実施例を図1,図2および図3
を用いて詳細に説明する。図1は、この実施例における
半導体装置の構造を示す断面図である。複数の半導体素
子1を図に示すように、互いに間隔を開けて平行に重ね
て積層する。このとき、半導体素子1の側端面に、例え
ばポリイミド等の絶縁樹脂による配線基板2を、半導体
素子1に垂直に配置する。この配線基板2には、半導体
素子1の表面の側縁に並設した複数の電極4と電気的接
続を取るために、例えばW(タングステン)等の所定の
材料で作られた針状端子3が、あらかじめ半導体素子の
電極4のピッチに応じた所定の間隔で形成されている。
この針状端子3は配線基板2の外面(主面側)から内面
(他面側)に突出して(例えば長さ100−200μ
m、径20μm程度)形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention is shown in FIGS.
Will be described in detail. FIG. 1 is a sectional view showing the structure of a semiconductor device according to this embodiment. As shown in the figure, a plurality of semiconductor elements 1 are stacked in parallel with each other with a space therebetween. At this time, the wiring board 2 made of an insulating resin such as polyimide is arranged perpendicularly to the semiconductor element 1 on the side end surface of the semiconductor element 1. The wiring board 2 has needle-like terminals 3 made of a predetermined material such as W (tungsten) for electrical connection with a plurality of electrodes 4 arranged in parallel on the side edges of the surface of the semiconductor element 1. Are formed in advance at predetermined intervals according to the pitch of the electrodes 4 of the semiconductor element.
The needle terminal 3 projects from the outer surface (main surface side) of the wiring board 2 to the inner surface (other surface side) (for example, a length of 100 to 200 μm).
m, diameter about 20 μm).

【0011】この針状端子3は、半導体素子1の電極群
4(例えばm個)と、積層する半導体素子列の数(例え
ばn個)に対応して、m×nのマトリクス状に形成され
ている。針状端子3と電極4の電気的接続部分の詳細
を、図2に示す。半導体素子1の裏面には、適当な弾性
を持つ弾性絶縁膜8をあらかじめ所定の膜厚で均一に形
成しておく。つぎに、針状端子3と電極4とを位置合わ
せしながら、配線基板2を内側(半導体素子1方向)に
移動させる。そして、位置合わせ完了後、半導体素子1
の最上部と最下部から挟み込むように、モジュール全体
に上下方向から適当な荷重を加える。そうすることによ
り、複数列の針状端子群3と複数列の半導体素子1の電
極群4を圧接により一括コンタクトさせる。このとき、
弾性絶縁膜8により針状端子3は電極4と適当な接触圧
で圧接され、しかも隣接の電極4とは電気的に絶縁され
る。
The needle terminals 3 are formed in a matrix of m × n corresponding to the number of electrode groups 4 (for example, m) of the semiconductor element 1 and the number of semiconductor element rows to be stacked (for example, n). ing. The details of the electrical connection between the needle-shaped terminal 3 and the electrode 4 are shown in FIG. On the back surface of the semiconductor element 1, an elastic insulating film 8 having an appropriate elasticity is uniformly formed in advance with a predetermined film thickness. Next, the wiring board 2 is moved inward (toward the semiconductor element 1) while aligning the needle terminals 3 and the electrodes 4. Then, after the alignment is completed, the semiconductor element 1
Apply an appropriate load from above and below the entire module so that it is sandwiched from the top and bottom of the module. By doing so, the needle-shaped terminal groups 3 in a plurality of rows and the electrode groups 4 of the semiconductor elements 1 in a plurality of rows are collectively brought into pressure contact with each other. At this time,
Due to the elastic insulating film 8, the needle-shaped terminal 3 is pressed against the electrode 4 with an appropriate contact pressure, and is electrically insulated from the adjacent electrode 4.

【0012】なお、配線基板2には、図3に示すように
半導体素子1間の相互配線パターン6、ならびにモジュ
ールと外部を接続するためのモジュール電極7が形成さ
れている。マトリクス状に形成されたm群×n列の針状
端子群3は、モジュール内配線の仕様に応じて相互配線
パターン6と接続されている。このように構成された半
導体装置およびその製造方法によると、複数の半導体素
子1を3次元的に積層して実装できるため、実装密度を
大幅に上げることができる。
As shown in FIG. 3, an interconnection pattern 6 between the semiconductor elements 1 and a module electrode 7 for connecting the module and the outside are formed on the wiring board 2. The m groups × n rows of needle-shaped terminal groups 3 formed in a matrix are connected to the mutual wiring pattern 6 according to the specifications of the wiring in the module. According to the semiconductor device having such a configuration and the method for manufacturing the same, since the plurality of semiconductor elements 1 can be three-dimensionally stacked and mounted, the mounting density can be significantly increased.

【0013】また、半導体素子1間の相互配線は、側端
面に配置した配線基板2上に形成した配線パターン6に
より行うため、非常に実装効率の良い配線が可能であ
る。しかも、半導体素子1間の相互配線とコンタクトを
配線基板2のみで行うため、実装部材のコストの削減も
可能である。さらに、半導体素子1の電極4との接続
は、配線基板2に形成した針状端子3との接触により行
うため、高密度な接続が可能であり、かつ比較的簡易に
接続することができ、製造工程の簡略化が図れる。
Further, since interconnection between the semiconductor elements 1 is performed by the interconnection pattern 6 formed on the interconnection substrate 2 arranged on the side end face, interconnection with very high mounting efficiency is possible. Moreover, since interconnection and contact between the semiconductor elements 1 are performed only by the wiring board 2, the cost of the mounting member can be reduced. Furthermore, since the connection with the electrode 4 of the semiconductor element 1 is made by contact with the needle-like terminal 3 formed on the wiring board 2, a high-density connection is possible, and the connection can be made relatively easily. The manufacturing process can be simplified.

【0014】したがって、例えば大容量のメモリモジュ
ールを構成する場合には非常に有効である。すなわち、
半導体素子をキャリア等を介さずに直接3次元的に積層
した構造を持つため、多くの半導体素子で構成するよう
なモジュール、例えば大容量のメモリモジュールを実装
密度を低下させることなく、かつ通常のパッケージ品の
積層構造と比較して薄型に実現することが可能である。
また、あらかじめ外形サイズの規定された、ゲートアレ
イ等のASICによる機能モジュールの実現においても
非常に有効な製造方法である。
Therefore, it is very effective when, for example, a large capacity memory module is constructed. That is,
Since it has a structure in which semiconductor elements are directly three-dimensionally stacked without interposing a carrier or the like, a module composed of a large number of semiconductor elements, for example, a large-capacity memory module, can be used without reducing the mounting density, and It can be made thinner than the laminated structure of the packaged product.
It is also a very effective manufacturing method for realizing a functional module using an ASIC such as a gate array whose external size is defined in advance.

【0015】なお、配線基板2の材料は、ポリイミド等
のフィルムのみならず、例えばセラミックや他の有機材
料によるラミネート基板でもよい。この発明の他の実施
例を図4,図5および図6を用いて詳細に説明する。す
なわち、この実施例は、針状端子3と電極4の電気的接
続を、ハンダバンプ等を介して行うことを特徴とするも
のである。この場合、半導体素子1の電極群4にあらか
じめ公知の手法によりハンダバンプ5を形成しておき、
適当なスペーサ(図示せず)で半導体素子1間の間隔を
保ちながら、雰囲気温度をはんだが所定の硬度まで柔ら
かくなるよう調整する。そして、この実施例では、右方
向より配線基板2を半導体素子1方向へ移動する。
The material of the wiring board 2 is not limited to a film such as polyimide, but may be a laminated board made of, for example, ceramics or other organic materials. Another embodiment of the present invention will be described in detail with reference to FIGS. 4, 5 and 6. That is, this embodiment is characterized in that the electrical connection between the needle-shaped terminal 3 and the electrode 4 is performed via a solder bump or the like. In this case, the solder bumps 5 are previously formed on the electrode group 4 of the semiconductor element 1 by a known method,
The atmosphere temperature is adjusted so that the solder is softened to a predetermined hardness while maintaining the space between the semiconductor elements 1 with an appropriate spacer (not shown). Then, in this embodiment, the wiring board 2 is moved from the right direction toward the semiconductor element 1.

【0016】配線基板2に形成された針状端子群3が、
電極群4上で柔らかくなったハンダバンプ5を突き抜け
た状態で、雰囲気温度を降下させる。これで半導体素子
1と配線基板2の電気的接続と同時に、複数の半導体素
子1と配線基板2相互の固定も行うことができる。この
ように構成された半導体装置およびその製造方法におい
ても、前記第1の実施例と同様の効果が得られる。
The needle terminal group 3 formed on the wiring board 2 is
The atmosphere temperature is lowered while penetrating the softened solder bumps 5 on the electrode group 4. With this, simultaneously with the electrical connection between the semiconductor element 1 and the wiring board 2, the plurality of semiconductor elements 1 and the wiring board 2 can be fixed to each other. Also in the semiconductor device having such a structure and the method for manufacturing the same, the same effect as that of the first embodiment can be obtained.

【0017】[0017]

【発明の効果】この発明の半導体装置およびその製造方
法によると、複数の半導体素子を平行に積層した実装構
造であるため、実装密度を大幅に高めることができる。
また、半導体素子間の相互配線は、側端面に配置した配
線基板にて行うため、非常に実装効率の良い配線ができ
る。さらに、半導体素子の電極との接続は、配線基板に
形成した針状端子との接触、あるいはハンダバンプにて
行うため、比較的簡易に接続することができ、製造工程
の簡略化が図れるという効果がある。
According to the semiconductor device and the method of manufacturing the same of the present invention, since the mounting structure has a plurality of semiconductor elements stacked in parallel, the mounting density can be greatly increased.
Moreover, since interconnection between the semiconductor elements is performed by the wiring board arranged on the side end face, wiring with extremely high mounting efficiency can be performed. Furthermore, since the connection with the electrodes of the semiconductor element is made by contact with the needle terminals formed on the wiring board or by solder bumps, the connection can be made relatively easily and the manufacturing process can be simplified. is there.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例における半導体装置を示す
断面図である。
FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

【図2】この発明の一実施例における半導体装置を示す
部分断面図である。
FIG. 2 is a partial cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

【図3】この発明の一実施例における半導体装置を示す
斜視図である。
FIG. 3 is a perspective view showing a semiconductor device according to an embodiment of the present invention.

【図4】この発明の他の実施例における半導体装置を示
す断面図である。
FIG. 4 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

【図5】この発明の他の実施例における半導体装置を示
す部分断面図である。
FIG. 5 is a partial cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

【図6】この発明の他の実施例における半導体装置を示
す部分平面図である。
FIG. 6 is a partial plan view showing a semiconductor device according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 配線基板 3 針状端子 4 電極 5 ハンダバンプ 6 相互配線パターン 8 弾性絶縁膜 1 semiconductor element 2 wiring board 3 needle terminal 4 electrode 5 solder bump 6 mutual wiring pattern 8 elastic insulating film

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 互いに間隔を開けて積層した複数の半導
体素子と、これら各半導体素子の側端面に沿って設けた
配線基板と、前記各半導体素子の表面に設けた電極と、
前記配線基板に突設するとともに前記電極に接続した針
状端子とを備えた半導体装置。
1. A plurality of semiconductor elements stacked at intervals, a wiring board provided along side end faces of each of these semiconductor elements, and an electrode provided on the surface of each of the semiconductor elements.
A semiconductor device, comprising: a needle-shaped terminal projecting from the wiring board and connected to the electrode.
【請求項2】 電極は半導体素子の表面の端縁に並設し
た電極群からなり、これら電極群に対応して針状端子群
を配線基板に突設したことを特徴とする請求項1記載の
半導体装置。
2. The electrode comprises a group of electrodes arranged side by side on the edge of the surface of the semiconductor element, and a group of needle-like terminals corresponding to the group of electrodes is provided on the wiring board so as to project therefrom. Semiconductor device.
【請求項3】 配線基板の外面に半導体素子間を接続す
る相互配線パターンを形成し、針状端子を前記相互配線
パターンに接続するとともに前記配線基板に貫通して設
けたことを特徴とする請求項1記載の半導体装置。
3. An interconnection pattern for connecting semiconductor elements is formed on an outer surface of a wiring board, and needle terminals are provided so as to connect to the interconnection pattern and penetrate the wiring board. Item 1. The semiconductor device according to item 1.
【請求項4】 電極と針状端子が、ハンダバンプにより
接続されていることを特徴とする請求項1記載の半導体
装置。
4. The semiconductor device according to claim 1, wherein the electrode and the needle terminal are connected by a solder bump.
【請求項5】 半導体素子の裏面に弾性絶縁膜を形成し
たことを特徴とする請求項1,2,3または4記載の半
導体装置
5. The semiconductor device according to claim 1, wherein an elastic insulating film is formed on the back surface of the semiconductor element.
【請求項6】 各々表面に電極を設けた複数の半導体素
子を所定の間隔を開けて積層し、前記各電極に対応する
針状端子を突設した配線基板を前記各半導体素子の側端
面に沿って設け、前記各針状端子がそれぞれ対応する電
極に重なるように前記配線基板を位置決めし、前記積層
した半導体素子の上下より加圧して前記針状端子と前記
電極を接続する半導体装置の製造方法。
6. A wiring board, on which a plurality of semiconductor elements each having an electrode on the surface thereof are stacked at a predetermined interval, and needle terminals corresponding to the respective electrodes are projected, is provided on a side end surface of each of the semiconductor elements. Manufacturing of a semiconductor device which is provided along with the needle-shaped terminals, positions the wiring board so as to overlap the corresponding electrodes, and pressurizes the stacked semiconductor elements from above and below to connect the needle-shaped terminals to the electrodes. Method.
JP22119593A 1993-09-06 1993-09-06 Semiconductor device and its manufacture Pending JPH0778934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22119593A JPH0778934A (en) 1993-09-06 1993-09-06 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22119593A JPH0778934A (en) 1993-09-06 1993-09-06 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH0778934A true JPH0778934A (en) 1995-03-20

Family

ID=16762964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22119593A Pending JPH0778934A (en) 1993-09-06 1993-09-06 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH0778934A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3619523B2 (en) * 1996-12-04 2005-02-09 株式会社ルネサステクノロジ Semiconductor device
US6900074B2 (en) 1999-07-30 2005-05-31 Renesas Technology Corp. Method of manufacturing a semiconductor device having plural semiconductor chips, wherein electrodes of the semiconductor chips are electrically connected together via wiring substrates of the semiconductor chips
JP2007166899A (en) * 2007-02-09 2007-06-28 Hitachi Ltd Automobile controller
WO2024045329A1 (en) * 2022-09-02 2024-03-07 长鑫存储技术有限公司 Semiconductor structure and method for manufacturing same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3619523B2 (en) * 1996-12-04 2005-02-09 株式会社ルネサステクノロジ Semiconductor device
US7138722B2 (en) 1996-12-04 2006-11-21 Renesas Technology Corp. Semiconductor device
US6900074B2 (en) 1999-07-30 2005-05-31 Renesas Technology Corp. Method of manufacturing a semiconductor device having plural semiconductor chips, wherein electrodes of the semiconductor chips are electrically connected together via wiring substrates of the semiconductor chips
JP2007166899A (en) * 2007-02-09 2007-06-28 Hitachi Ltd Automobile controller
WO2024045329A1 (en) * 2022-09-02 2024-03-07 长鑫存储技术有限公司 Semiconductor structure and method for manufacturing same

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