TW441034B - Method to form insulation spacer of a single polysilicon gate of EEPROM - Google Patents

Abstract

The present invention provides a method to form the insulation spacer of a single polysilicon gate of EEPROM, wherein a high temperature oxide layer is deposited after forming an oxide insulation material on the surface of a single polysilicon to reduce the stress damage of the silicon nitride spacer formed later to the silicon oxide insulation layer, so that the electron transition to the silicon nitride spacer is prevented. Thus the electrons stored originally in a single polysilicon gate can be further preserved and the loss of the memory data is prevented.

Description

4 41 03 4 V. Description of the invention (1) The present invention relates to a single compound silicon gate of an electrically erasable programmable read-only memory, and particularly to an electrically erasable programmable read-only memory Method for forming insulating spacer of single polycrystalline silicon interrogator. Electrical erasable programmable read-only memory (hereinafter referred to as EEPR0M) is a widely used memory element in today's information electronics. Among them, it includes an EEPROM with a single compound silicon gate, and the process is applicable to a traditional CMOS process with a single compound silicon gate. Here, please refer to Figures 1A ~ 1C for a clearer view of the general structure of an EEPROM cell with a single polysilicon gate and its programming and erasing operations; of which Figure 1A shows the EEPR0M's layout 'Figure 1B shows a cut-out view along line 1B--1B in Figure 1 A, and Figure 1C shows a cross-section view along line 1C--1C in Figure 1A . As shown in FIGS. 1A to 1C, the EEPROM cell 100 is formed on a p-shaped silicon substrate 112 and includes a pair of source regions 114 and a drain region 116 which are separated from each other. In the source region 1 1 The silicon substrate 11 2 between 4 and the drain region 116 is a channel region 118. Above the channel region 118, a gate oxide layer 130 is included, and a floating gate (f 10a t i ng ga t e) 1 3 4 is formed thereon. In addition, the EEPROM cell 100 further includes a TIM well region 12 and an isolation material, such as field oxide FOX or shallow trench isolation STI. Here, the shallow trench isolation ST I is taken as an example; and The shallow trench isolation ST I is used to isolate the source region 114, the drain region 116, the channel region 118 and the TIM well region 120. The D1! | {Well region 120 further includes an N-type ion-concentrated doped region 124 for contact, and on the other side is a control gate region (contr〇1).

Page 5 441 03 4 V. Description of the invention (2) ga t e reg i on) 1 2 8 ′ Here, the surface of the silicon substrate 1 1 2 of the control gate region 1 28 is a control gate oxide layer 132. Please refer to Figs. IB and 1C. "When programming is performed, a relatively high voltage is added to the N-type ion doped region 124, and a relatively low voltage is added to the drain region 116." In addition, the silicon substrate 112 and the source region 114 are grounded to allow electrons to be injected into the floating gate 134 from the drain region 116 through the gate oxide layer 130 due to a tunneling effect; on the contrary, when EEPR0M 1 00 is performed, When erasing, a relatively high voltage is added to the drain j 6, and a relatively low voltage is added to the N-type ion doped region 1 24, so that the electrons are removed from the floating gate due to the tunneling effect. 1 3 4 passes through the gate oxide layer 130 and is implanted into the drain region 116. In the step of forming a single polycrystalline silicon gate of EEPR0M, an insulating spacer is usually formed on the side wall of the polycrystalline silicon gate, as shown in FIG. 2: on a silicon substrate A shallow trench isolation STI is formed on 20, and a gate oxide layer 21 and a single polycrystalline silicon gate 22 ′ are formed thereon. After the ion is lightly doped (LDD) into the silicon substrate 20, the single polycrystalline silicon is formed. The silicon gate 22 is oxidized to form a silicon oxide insulating layer (not shown) on the surface, and a silicon nitride spacer 23 is generated on the sidewall. After that, heavily doped ions are allowed to enter the silicon substrate 20 'to form A pair of source / drain electrodes 24. However, such a silicon nitride spacer 23 has a large stress on a silicon oxide insulating layer or a material made of stone material surrounded by the silicon nitride spacer 23, and therefore, the oxide sand insulating layer is likely to be damaged. Since a single polycrystalline silicon gate in the EEPROM cell is used to store electrons to memorize data during operation, if the silicon oxide insulating layer surrounding it is damaged, it is very easy to cause a single polycrystalline silicon gate

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89102209_ 年月 日 __ Trap the silicon oxide insulation layer and jump further into the silicon nitride spacer. This results in the loss of data previously stored in a single polycrystalline silicon gate, resulting in the failure of the data retention function (d a ΐ a r e t e η ΐ i ο η faii). In view of this, an object of the present invention is to provide a method for forming an insulating spacer of an i-multiplexed silicon gate of an electrically erasable programmable read-only memory > which can reduce the silicon nitride spacer and give silicon oxide The stress of the green insulation layer can prevent the electrons stored in a single polycrystalline silicon gate from sinking into the silicon oxide insulating layer and jumping into the silicon oxide spacer. Therefore, the loss of data can be avoided. "In order to achieve the purpose of the present invention, A method is provided for depositing a high-temperature oxide layer after the formation of an oxidative insulating material on the surface of a mono-polycrystalline silicon to reduce the stress damage of the silicon nitride spacer to the silicon oxide insulating layer to prevent electronic transitions. To the silicon nitride spacer, the electrons originally stored in the single compound silicon gate are further stored, and then the data is saved to prevent it from being lost. This method is suitable for a semiconductor substrate, and a control gate region and a tunneling oxide layer on the surface of the control gate region are formed in the semiconductor substrate. The method includes the following steps: forming a gate oxide layer on the semiconductor The surface of the substrate; a complex silicon gate is formed on the surface of the oxide layer of the gate, and

The I-Si gate is connected to the tunneling oxide layer; an oxide layer is formed on the surface of the Si-Si gate; a pair of spaced apart ion-doped regions is formed near the Si-Si gate. In the semiconductor substrate on both sides of the gate; forming a buffer layer on the surface of the oxide layer; forming a nitride layer on the surface of the buffer layer; and etching the nitride layer and the buffer layer to the polycrystalline silicon gate A! Insulation spacer is formed around.

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1 ^ -Ming (4) Correction " Supplement 89102209 44103 4 ± _η means to make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable. = The following is a preferred embodiment and cooperates with the accompanying drawings. The detailed description is as follows: Brief description of the diagram: Figure 1 A- 1 C shows the structure of a conventional EEPROM with a single complex silicon gate: Figure 2 shows the conventional single complex with a spacer Figure 3A and 3B show structure diagrams of general EEPROMs with single crystal silicon gates; and Figures 4A to 4F show single silicon gates manufactured according to the present invention Cross-sectional view of the manufacturing process of the pole spacer. | Symbol Explanation 100, 300 ~ EEPROM cells; 112, 312 ~ P type silicon substrates; 114, 314 ~ source regions; 116, 316 ~ drain regions; 118, 318-channel regions; 120, 320 ~ Τ Μ well regions 124'324 ~ N-type ion-doped heavily doped region; 128, 328 ~ control gate region; 13〇 '3 3 0 ~ inter-oxide layer; 132,332 ~ control gate oxide layer; 134,334 ~ floating gate; ST Bu Shallow trench isolation; 20, 4〇〜 沙 # plate; 21 ~ gate oxide layer; 22 ~ polycrystalline silicon gate; 23 ~ nitride evening soil • 24 ~ source / drain; 4bu floating gate; 4 1 0 ~ gate oxide layer; 4 j 丨 ~ allium oxide; layer; 42, 42 oxide oxide layer; 43 source / doped erbium-doped region complex crystal source / drain-rich doped region: 44 441 ~ high temperature gasification layer; ^ ~ 432 ~ gasification stone layer; 46 ~ insulating spacer; 47 ~ source / drain 3, 45b

441 03 4 V. Description of the invention (5) First, "see Figs. 3A and 3B" to explain the conditions before the formation of the insulating spacer of the present invention, where "3B" is shown along the 3A A cross-sectional view of line 3B--3B; as shown, the EEPR0M unit 300 is formed on a p-shaped stone substrate 312 'which includes a pair of source regions 314 and a drain region 3 1 6' spaced apart from each other. Between the source region 3 1 4 and the drain region 3 16, there is a channel region 318 in the epsilon substrate 31 2. Above the channel region 118, a gate oxide layer 3 3 0 is included, and a floating gate (ie, a single-complex silicon gate) 3 3 4 is formed thereon. In addition, the EEPROM cell 300 further includes a TIM well region 320 and a shallow trench isolation ST I ', and the shallow trench isolation ST I is used to connect the source region 3 1 4 and the electrode region 316, the channel region 318 and TIM well area 320 is isolated. In the UIM well region 320, an N-type ion-doped region 324 is further included for contacting; on the other side, a gate region 3 2 8 is controlled, and a silicon substrate of the gate region 3 2 8 is controlled here. The surface of 3 1 2 is a control gate oxide layer (ie, tunneling oxide layer) 3 3 2. Next, for the sake of convenience, please refer to FIGS. 4A to 4F, which are cross-sectional views taken along line 3C--3C in FIG. 3A and show a single polycrystalline silicon forming an EEPROM according to the present invention. Gate spacer method; first 'see Figure 4A' is to provide a semiconductor substrate 40, such as a silicon substrate 'and a shallow trench isolation mi is formed on the surface of the silicon substrate 40 for each Insulation between components; a floating gate 41 is formed therebetween, which includes a gate oxide layer 410, such as a fragmented oxide layer, and a single poly-layer layer 411, where A part of the single polycrystalite layer 411 is in contact with the tunnel oxide layer 332 in FIG. 3B. Next, please refer to FIG. 4B ′ to form an oxide layer on the polysilicon gate.

-^ 10 3 4 V. Description of the invention (6) The surface of the electrode; for example, the surface of the polycrystalline silicon is oxidized by thermal oxidation to form a layer of oxidized stone on the surface of the floating gate 41 4 2 . Then, lightly doped ions are introduced into the sand substrate 40 to form a pair of lightly doped regions (LDD) 431 of the source / drain in the silicon substrate 40 below the sides of the floating gate 4 i, as shown in FIG. 4C. As shown. Next, referring to FIG. 4D, to perform the most critical step of the present invention, that is, forming a buffer layer on the surface of the oxide layer: for example, depositing a layer of high temperature at a high temperature of 400 ~ 800 ° C The oxide layer (HT0) 44 is on the surface of the silicon oxide layer 42 and has a thickness of approximately 100A or more. Afterwards, please refer to FIG. 4E to form a nitride layer on the surface of the buffer layer; for example, using ammonia gas (NH3) as a reaction gas to perform plasma enhanced chemical vapor deposition (PECVD) to deposit a layer of nitride A silicon layer 45 is on the surface of the high-temperature oxide layer 44 and has a thickness between 500 and 2000 A. Next, please refer to FIG. 4F. The nitride layer and the buffer layer are etched to form an insulating spacer around the polycrystalline silicon gate; for example, a plasma containing fluoride gas is used to nitride the nitride layer. The silicon layer 45 and the high-temperature oxide layer 44 are dry-etched to form an insulating spacer 46 around the floating gate 41. The insulating spacer 46 includes a silicon oxide layer 421, a high-temperature oxide layer 441, and a silicon nitride layer. 451. Immediately. Using the insulating spacer as a cover, ions are implanted into the silicon substrate 40 to form a pair of source / drain electrodes 47 ′ including a lightly doped region 431 and a heavily doped region 432 of the ion. The formed insulating spacer, under the premise that the insulation purpose is reached, "because the high-temperature oxide layer 441 has a certain thickness, this" existence can translate the stress of the nitrogen-cut layer 451 to the oxygen-cut layer 421 to

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r —-- ^ 41 〇SA correction ^ Beer April 1st / f No. 89102209_year month__; == £ = i * mscifc The direction farther from the floating gate 4 i, that is, reducing silicon nitride The stress damage of the layer 45 1 on the silicon oxide layer 421 further reduces the amount of charge trapped in the silicon oxide layer 42 1 and further prevents electrons from jumping into the nitride layer 4 5 1, so that the original existence of the floating gate 4 can be saved. The electrons in I, so the stored data can be prevented from being lost. In addition: the manufacturing process of the present invention is simple, so it will not result in manufacturing; j complexity and complexity (c 0 m p 1 e X i 1: y) increase. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

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Claims (1)

丨 4 4 1 Ο 3 4 ：::: ^ ~ ^-^: ^ Article No. 89102209 h ^ "F fl revised version, _ please patent scope " " ~ '' ~ ^ 1. A form of electrical The method of erasing programmable read-only memory with a single compound and an insulating spacer of a silicon gate is applicable to a semiconductor substrate. ^ The semiconductor base formation system is formed to control the gate area 'and a gate located in the readout city. The tunneling oxide layer on the surface of the area includes the following steps: forming a gate oxide layer on the surface of the semiconductor substrate; forming a polycrystalline silicon gate electrode on the surface of the gate oxide layer; The pole system is in contact with the tunneling oxide layer; ^ forms an oxide layer on the surface of the polycrystalline silicon gate; forms a pair of lightly doped regions of ions spaced apart from each other on both sides of the polycrystalline silicon A conductor substrate ', in the middle; forming a buffer layer on the surface of the oxide layer; forming a nitride layer on the surface of the buffer layer; and engraving the nitride layer and the buffer layer around the polycrystalline silicon gate Consider insulating spacers. 2. The method according to item 1 of the scope of patent application, wherein the buffer layer is a high-temperature oxide layer deposited at a high temperature of 400 to 850 t, and the thickness is generally between 10 ΙΟΟΟ A. 3. The method according to item 1 in the scope of the patent application, wherein the nitride R is silicon nitride deposited by plasma enhanced chemical vapor deposition with atmosphere wind 1 as the gas of sigh, and its The thickness is generally between 500 ~ 200A. 4. The method according to item 1 of the patent application park, wherein the oxide layer is formed by thermally oxidizing the surface of the polycrystalline silicon gate to form an oxide layer on the surface of the polycrystalline silicon gate. An oxide layer with a thickness between 10 and 2 0 A. 4 4 1 0 3 4 _Case No. 89102209_Year Month Date__ VI. Patent Application Range 5. The method described in item 1 of the patent application range, in which a plasma containing fluorine gas is used for nitriding The layer and the buffer layer are dry-etched to form the insulating spacer. 6. The method as described in item 1 of the patentable scope, wherein the semiconductor substrate is a silicon substrate. 7. —A method for forming an insulating spacer of a single polycrystalline silicon gate of an electrically erasable programmable read-only memory, which is suitable for a silicon substrate, and a control gate region is formed in the semiconductor substrate, and a The tunneling oxide layer on the surface of the control gate region includes the following steps: forming a gate oxide layer on the surface of the dream substrate; forming a polycrystalline silicon gate electrode on the surface of the gate oxide layer, and part of the i compound crystal On the 5th, the gate electrode is connected to the through oxide layer 1; i | forms a silicon oxide layer on the surface of the complex silicon gate; I forms a lightly doped region of ions separated from each other so as to be close to the complex In the silicon substrate on both sides of the silicon gate; forming a high-temperature oxide layer on the surface of the oxide layer; forming a silicon nitride layer on the surface of the high-temperature oxide layer; etching the nitride layer and the buffer layer to Forming an insulating spacer around the complex silicon gate; and forming a pair of densely doped regions of ions spaced apart from each other in the silicon substrate near the two sides of the complex silicon gate. 8. The method as described in item 7 of the patent application scope, wherein the high-temperature oxide layer is deposited at a high temperature of 400-850 ° C, and the thickness is generally between 100 and 100. Between A. 0503-508〇η · Ρ1.ρΐο Page 13 4 41 03 4-Case No. 891f) 2? FlQ __ ^ __ β-Said — Amendment_ VI. The scope of Shenqi's patent 9. As described in item 8 of the scope of patent application The method is characterized in that the nitrided layer is deposited by plasma enhanced chemical vapor deposition method using ammonia as a reaction gas, and the thickness is generally between 500 and 2000 A. 10. The method as described in item 9 of the scope of the patent application, wherein the oxidized stone layer is formed by thermally oxidizing the surface of the polycrystalline silicon gate and performing oxidation on the surface of the polycrystalline silicon gate. Formed, and its thickness is generally between 10 ~ 20 0 A. 1 1. The method according to item 10 of the scope of the patent application, wherein the insulating spacer is formed by dry etching the silicon nitride layer and the high-temperature oxide layer with a plasma containing fluorine gas.