4369 8 1 4062twf,doc/006 五、發明説明（I ) 本發明是有關於一種積體電路的製造方法，且特別是 有關於一種淺溝渠隔離結構（Shallow Trench Isolation) 的製造；方法。 元件隔離區係用以防止載子（Carrier)通過基底而 在相鄰之元件間移動，比如於相鄰的金氧半場效應電晶體 (M0SFET，以下簡稱M0S電晶體）間形成元件隔離區，藉 以減少由M0S電晶體所產生的電荷遺漏（Charge Leakage) ◊在VLSI或ULSI的製程中，由於電晶體的數 目非常龐大且非常密集，爲了防止相鄰的電晶體間發生短 路（Short CMrcuU)，必須在這些相鄰的電晶體間形成隔 離的結構；隨著元件積集度的提高以及線寬的縮小，當製 程進入0.25微米以下時，淺溝渠隔離結構已是必須之元 件隔離結構。 習知淺溝渠隔離結構的形成方式是利用非等向性的蝕 刻法（Anisotropic Etching)，在基底中挖出溝渠，之 後利用熱氧化法，於溝渠所暴露出的基底表面形成一層襯 氧化層，然後再於其中塡滿無摻雜的氧化物（Non-doped Oxide)，經密實化（Densification)製程以及一些後續 的製程，因而形成了元件隔離區。 在進行淺溝渠隔離的製程之後，通常會以離子佈植的 方式，對基底進行摻雜，在基底上植入離子形成N型或P 型離子，以使基底具有預期的導電型態；在植入的過程中， 離子會撞擊基底的表面，使基底的晶格結構受到破壞。另 外，對線寬小於〇.25μιη的半導體元件而言，淺溝渠開口 3 木紙认尺度译州屮（（'NS ) Λ心兄梠（210x 297公漦) ' --I I-;----、裝------訂------' β (邛先間讀背面之：>χ意事項再填寫本頁) 4369 8 1 4〇62twf.doc/006 A7 __________B7 _____ 五、發明説明（〉） '之尖銳的邊角附近是應力集中處，使用淺溝渠隔離結構會 較傳統區域氧化法的結構留下更大的應力，因而使基底產 生插排；上述兩種狀況均會造成元件的漏電。 有鑑於此，本發明的主要目的就是在提供一種淺溝渠 隔離的製造方法，消除在形成半導體元件時造成晶格差排 以及遺漏電流的現象，藉以提供元件的效能。 根據本發明的上述及其他目的，提出一種淺溝渠隔離 的製造方法，提供已形成溝渠之基底，利用熱氧化法在溝 渠所暴露出之基底表面形成一層襯氧化層；再進行一高溫 回火的步驟，藉以釋放蝕刻形成溝渠時，在溝渠轉角之基 底產生的應力。之後，在此溝渠中的襯氧化層上塡入絕緣 層，並去除溝渠以外的絕緣層。進行一密實化製程，用以 將溝渠中之絕緣插塞密實化，將密實化的溫度提高，藉以 進一步的釋放淺溝渠隔離結構中的應力。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1A圖依照本發明一較佳實施例，在基底中形成溝渠 之剖面簡示圖； 第1B圖繪示係在第1A圖繪示之溝渠中形成一層襯氧 化層之剖面簡示圖； 第1C圖繪示係在第1B圖的結構上覆蓋一層絕緣層的 剖面圖；以及 4 4、紙汰尺政询川'Γϋΐϋϋ—( rNsTw規梠（2丨0X297公釐) - 气 (讳先閱讀背而之注意事項再硪巧本頁) #ί--Γ十次 5έ"Λ,5η π;ί,ί^Α";ίτ.ΐ印1;r I Δ369 8 1 4 Ο 6 2 twf . doc /0 0 6 A7 ___B7 _ _ 五、發明説明（>) 第ID圖繪示係去除溝渠以外之絕緣層之結構剖面。 圖示標記說明： 10,0 基底 102 墊氧化層 104 溝渠 106 襯氧化層 108 絕緣層 108a 絕緣插塞 實施例 第1A圖至第1D圖繪示依照本發明一較佳實施例的一 種淺溝渠隔離之製造流程圖。 首先，請參照第1A圖，提供基底100，較佳的是P型 半導體基底或是N型半導體基底。在此基底100表面形成 墊氧化層102，此墊氧化層102的形成，比如利用熱氧化 法，其厚度約爲50〜500A。在墊氧化層102上形成一層罩 幕層（未繪示於圖中），比如厚度約爲1000-2000埃的氮化 矽層，進行微影與蝕刻的製程，去除部分的墊氧化層102 與基底100，以在基底100中形成溝渠104，罩幕層可用 於保護基底100免於遭受後續製程的破壞。去除部分墊氧 化層102與基底1〇〇的較佳蝕刻方法是非等向性蝕刻。 請參照第1B圖，於溝渠110中的基底100表面形成 一層襯氧化層106，此襯氧化層106會延伸至與墊氧化層 102接觸，其中襯氧化層1〇6的形成方法比如是乾式熱氧 化法’溫度約爲攝氏900-1100度，厚度約爲100〜600A左 5 本紙张尺度迖州屮标肀（) λ心兄招（210X297公漦) -----^----^ ΐ裝------訂------，線 (銷先閲請背面之注^^^^項再读寫本頁) ' 4369 8 1 4062twf . d〇c/006 A7 _B7______ 五、發明説明（f) 右。在襯氧化層106形成後，進行一道回火的步驟，藉以 消除產生在基底的應力，回火的溫度約爲攝氏1100度-1200 度，在I氮氣的環境下進行的時間約爲15-60分鐘。另外， 此道回火的步驟也可與形成襯氧化層106的步驟同時進 行，採用回火使用的溫度，供應氧氣進行熱氧化法，當氧 化形成的襯氧化層106到達預定厚度時，即將氧氣轉換成 氮氣，直到回火步驟完成。 請參照第1C圖，形成一層絕緣層108於基底100上， 並塡入溝渠106中，絕緣層108的較佳材質比如爲二氧化 矽。進行密實化的製程，使絕緣層108的結構變的緻密， 習知密實化製程所用的溫度爲攝氏1000度，而本發明在 密實化製程中，將其溫度提高至約攝氏1050度- 1200度， 使密實化製程同時具有回火的效果，藉以將於淺溝渠隔離 製程中產生的應力釋放。 請參照第1D圖，去除溝渠106以外的絕緣層108以及 罩幕層，僅留下塡充在溝渠106之中的絕緣插塞l〇8a。其 中，去除絕緣層10S的方法比如爲化學機械硏磨法 (Chemical Mechanical Polishing, CMP)。 本發明利用至少一道的高溫回火製程，消弭離子植入 步驟對基底產生的破壞，以及在淺溝渠隔離製程中產生的 應力。 本發明的特徵之一爲進行形成襯氧化層的熱氧化步驟 時，或於襯氧化層形成以後，進行一道回火的步驟，藉以 消除形成襯氧化層時，襯氧化層與基底界面產生的應力。 6 本紙ίΑ尺度这川屮阀阀家榀呤（) f\4m& ( 21〇X 297/>f ) ^ ~ --1 —-----，、裝------訂------線 (誚先閱讀背TFJ之注項再填寫本頁) 4 Ο 6 2 twf . doc /0 0 6 A7 B7 五、發明説明（女） 本發明的另一特徵爲將絕緣材質塡充在溝渠以後，將 密實化步驟的溫度提高，使溫度高出習知溫度50〜200度， 使此步,驟不僅具有密實化的效果，有同時具有高溫回火的 效果，藉以更進一步的釋放淺溝渠隔離結構的應力。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 I ikih Jtl Ί; 1¾ 1¾ a II；( (-NS ) ΜΪΰΓΪ2\〇·χ29Ί^0~) --—·!---- 裝------訂------ί % (对先閱讀背a之注意事項再填穹本頁)4369 8 1 4062twf, doc / 006 V. Description of the Invention (I) The present invention relates to a method for manufacturing an integrated circuit, and more particularly, to a method for manufacturing a shallow trench isolation structure (Shallow Trench Isolation); a method. The element isolation region is used to prevent carriers from moving between adjacent elements through the substrate. For example, an element isolation region is formed between adjacent metal-oxide-semiconductor field-effect transistors (M0SFETs, hereinafter referred to as M0S transistors). Reduction of Charge Leakage Generated by M0S Transistors V In VLSI or ULSI processes, because the number of transistors is very large and very dense, in order to prevent short circuits between adjacent transistors (Short CMrcuU), An isolation structure is formed between these adjacent transistors. With the increase of the component accumulation and the reduction of the line width, when the process goes below 0.25 microns, the shallow trench isolation structure is already a necessary component isolation structure. A conventional method for forming a shallow trench isolation structure is to use Anisotropic Etching to dig a trench in a substrate, and then use a thermal oxidation method to form a liner oxide layer on the surface of the substrate exposed by the trench. Then, a non-doped oxide (Non-doped Oxide) is filled thereon, and after a densification process and some subsequent processes, an element isolation region is formed. After the shallow trench isolation process is performed, the substrate is usually doped by ion implantation, and ions are implanted on the substrate to form N-type or P-type ions, so that the substrate has the expected conductivity type. During the insertion process, ions will hit the surface of the substrate, causing the lattice structure of the substrate to be damaged. In addition, for semiconductor devices with line widths less than 0.25 μm, shallow trench openings 3 wooden paper recognition scale translation state (('NS) Λ heart brother (210x 297 cm))' --I I-;- -、 Equipment ------ Order ------ 'β (I read the back side first: > χ Italian matter and fill in this page) 4369 8 1 4〇62twf.doc / 006 A7 __________B7 _____ V. Description of the invention (>) The stress concentration is near the sharp corners. Using shallow trench isolation structure will leave more stress than the structure of the traditional regional oxidation method, which will cause the substrate to produce a row; the above two conditions In view of this, the main purpose of the present invention is to provide a manufacturing method of shallow trench isolation, which eliminates the phenomenon of lattice difference and leakage current when forming a semiconductor element, thereby providing the efficiency of the element. The above and other objects of the present invention provide a method for manufacturing a shallow trench isolation, providing a substrate on which the trench has been formed, and forming a lining oxide layer on the surface of the substrate exposed by the trench using a thermal oxidation method; and then performing a high-temperature tempering step. To release the etch When a trench is formed, the stress is generated on the base of the corner of the trench. Then, an insulating layer is inserted on the lining oxide layer in the trench, and the insulating layer outside the trench is removed. A compaction process is performed to insulate the trench. The plug is densified, and the temperature of the densification is increased, so as to further release the stress in the shallow trench isolation structure. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below. In conjunction with the attached drawings, the detailed description is as follows: Brief description of the drawings: FIG. 1A is a schematic cross-sectional view of a trench formed in a substrate according to a preferred embodiment of the present invention; FIG. 1B is shown in FIG. Figure 1A is a schematic cross-sectional view of an oxide-lined layer formed in the trench shown in Figure 1A; Figure 1C is a cross-sectional view of an insulating layer over the structure of Figure 1B; and 4 4. Γϋΐϋϋ— (rNsTw Regulations (2 丨 0X297 mm)-Qi (to read the precautions of the back first and then to clever this page) # ί--Γ 十 次 5έ " Λ, 5η π; ί, ί ^ Α "; ίτ.ΐ 印 1; r I Δ369 8 1 4 Ο 6 2 twf .doc / 0 0 6 A7 ___B7 _ _ V. Description of the invention (>) Figure ID shows the cross section of the structure that removes the insulation layer other than the trench. Symbol description: 10,0 substrate 102 pad oxide layer 104 trench 106 lined oxide layer 108 insulation layer FIG. 1A to FIG. 1D of the embodiment of the insulating plug embodiment show a manufacturing flow chart of a shallow trench isolation according to a preferred embodiment of the present invention. First, please refer to FIG. 1A to provide a substrate 100, preferably P Type semiconductor substrate or N-type semiconductor substrate. A pad oxide layer 102 is formed on the surface of the substrate 100. The pad oxide layer 102 is formed, for example, by a thermal oxidation method, and has a thickness of about 50 to 500 A. A mask layer (not shown) is formed on the pad oxide layer 102, such as a silicon nitride layer having a thickness of about 1000-2000 angstroms, and a lithography and etching process is performed to remove a part of the pad oxide layer 102 and The substrate 100 is used to form a trench 104 in the substrate 100, and a mask layer can be used to protect the substrate 100 from being damaged by subsequent processes. A preferred etching method for removing a portion of the pad oxidation layer 102 and the substrate 100 is anisotropic etching. Referring to FIG. 1B, a lining oxide layer 106 is formed on the surface of the substrate 100 in the trench 110, and the lining oxide layer 106 will extend to contact the pad oxide layer 102. The formation method of the lining oxide layer 106 is, for example, dry heat Oxidation method 'temperature is about 900-1100 degrees Celsius, thickness is about 100 ~ 600A, left 5 paper sizes (Zhouzhou standard) () λ heart brother strokes (210X297 Gong) ----- ^ ---- ^ Outfitting ------ order ------, line (pin read first, please read the note on the back ^^^^ before reading and writing this page) '4369 8 1 4062twf. d〇c / 006 A7 _B7______ 5 Description of the invention (f) Right. After the formation of the liner oxide layer 106, a tempering step is performed to eliminate the stress generated in the substrate. The tempering temperature is about 1100 degrees Celsius to 1200 degrees Celsius, and the time is about 15-60 degrees in the nitrogen atmosphere. minute. In addition, this tempering step can also be performed at the same time as the step of forming the lining oxide layer 106. The temperature used for the tempering is used to supply oxygen for thermal oxidation. When the lining oxide layer 106 formed by oxidation reaches a predetermined thickness, that is, oxygen Switch to nitrogen until the tempering step is complete. Referring to FIG. 1C, an insulating layer 108 is formed on the substrate 100 and inserted into the trench 106. A preferred material of the insulating layer 108 is, for example, silicon dioxide. The densification process is performed to make the structure of the insulating layer 108 dense. It is known that the temperature used in the densification process is 1000 degrees Celsius, and in the densification process, the present invention increases its temperature to about 1050 degrees to 1200 degrees Celsius. , So that the compaction process also has the effect of tempering, so that the stress generated in the shallow trench isolation process is released. Referring to FIG. 1D, the insulating layer 108 and the cover layer other than the trench 106 are removed, leaving only the insulating plug 108a filled in the trench 106. Among them, a method for removing the insulating layer 10S is, for example, a chemical mechanical polishing method (Chemical Mechanical Polishing, CMP). The invention utilizes at least one high-temperature tempering process to eliminate the damage to the substrate caused by the ion implantation step and the stress generated in the shallow trench isolation process. One of the features of the present invention is that during the thermal oxidation step of forming the liner oxide layer, or after the liner oxide layer is formed, a tempering step is performed to eliminate the stress generated at the interface between the liner oxide layer and the substrate when the liner oxide layer is formed. . 6 This paper ίΑ scale this Chuanxiong valve valve Jiazhixuan () f \ 4m & (21〇X 297 / > f) ^ ~ --1 —-----, installed ------ order- ----- Line (read the note of TFJ first, then fill in this page) 4 〇 6 2 twf .doc / 0 0 6 A7 B7 V. Description of the invention (female) Another feature of the present invention is the insulating material After filling in the ditch, the temperature of the compaction step is increased to make the temperature 50 to 200 degrees higher than the conventional temperature, so that this step not only has the effect of compaction, but also has the effect of high temperature tempering, so as to further Relieves stress in shallow trench isolation structures. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. I ikih Jtl Ί; 1¾ 1¾ a II; ((-NS) ΜΪΰΓΪ2 \ 〇 · χ29Ί ^ 0 ~) --- ·! ---- 装 -------- 订 ------ ί% ( (Notes for reading the back a before filling in the dome page)