TW436690B - Modulo address generating device and method for accessing a ring buffer - Google Patents

Abstract

The present invention provides a device and method for generating a modulo address for accessing a ring buffer. In accordance with the method and device, a buffer length (L), a current access address (A) and a difference magnitude (M) of the current access address and the next access address are input. The difference magnitude (M) can be positive or negative. In the operating process, the current address (A) is first decomposed into a base (B) and an offset (a). Then, based on the length (L) and difference magnitude (M), the present invention generates an absolute offset and a wrap offset. One of these two offsets is added to or combined with the base (B) to generate the next access address. The selection of the offset is determined by one of the two comparison operations. In details, based on the sign of the difference magnitude (M), the absolute offset is compared with a predefined value representing the starting address of the buffer, or the absolute offset is compared with a predefined value representing the ending address of the buffer. In a second embodiment, the selection of the offset to be added to the base (B) is based on a wrap flag produced by the circuit.

Description

Printed by the employee ’s consumer cooperative of the t-labelled bureau of the Ministry of Economic Affairs A7 ____5L__ 5. Description of the invention (I) The present invention relates to a device and method 'for generating a modulo address, especially a method for accessing a ring buffer. Device and method for generating analog address. The basic concept of using an analog-to-digital address generator to access a ring buffer is a known and conventional technique. Generally, a ring buffer has a predetermined length L. In the traditional ring buffer, the next access address is generated by adding the current address A plus the difference M ° When the difference M is added again and again, the access address will eventually exceed the ring type The address of the buffer end corresponds to the address 位. When this happens, the 'modulo addressing method will force the access address to wrap automatically to the starting position. Similarly, if the difference is negative, the final access address will be smaller than the address corresponding to the starting position of the ring buffer — address 値. When this happens, the 'modulo addressing method will force the access address to automatically return to the end position. Modulo address generation often operates in software. However, the generation of analog address by software is quite slow, and it is not suitable for some applications, such as digital signal processing (DSP) applications, because it requires fast address generation. The modular address generation method also operates in hardware. For example, U.S. Patent No. 4,800,524 discloses-a modular address generator that operates in hardware. The figure does not explain-the first diagram is a logic diagram of the circuit of the first embodiment of the present invention. The second figure is a logic diagram of a circuit according to a second embodiment of the present invention. The second figure shows a ring buffer accessed by modulo address method. Detailed description: The first figure reveals that the circuit 100 of the present invention includes a register 10, 12 and 14; together a leading one element 16; and (AND) gates 18, 20; an inverter 22;-a selector 26;-adder 28;-selector 30; 1

This paper uses China National Standard (CNS) A4 specifications (210X_i ^ 5 &quot; T ---------- ^ ------ ΐτ ------ ^) (Please read the (Note the $ items and then fill out this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 66 9 0 A7 __________B7_ V. Description of the invention (i) A comparator 32;-Adder 34 and μ; A selector 38, 40 And 42; an exclusive OR gate 44; and an OR gate 46. The register 10 stores a 値 A ', which represents the current access address of the ring buffer σ and the register 12 stores One L 'represents the length of the ring buffer. The buffer stores one μM, which represents the difference between the next access position and the current address a. The difference M can be positive or negative. The above a, L M and M will be described in conjunction with the third figure in the following description. The third figure reveals a ring buffer 300, which has a base address ZB and a length L. For a known ring buffer, The base address 値 β is the same. The base address 値 B, the length L, and the current access address A have the following properties: i) 2 (n &lt; L &lt; = 2n ', where n is an integer 103 and 111 2 &quot; of which 1 11,11 is an integer iii) B &lt; = A <(B.L) In the following example, all addresses and lengths are represented by binary. For example, if the length L is “100,” (that is, 8), the current address A is “10 10”, and the difference M is +1, then the next access address is α + M = "1011" and no address reversal action occurs. If the length L is "1000", the current address A is "1000" and the difference M is -1, the next access address is a + M Second, "1001" and no address reversal action occurs. Furthermore, assume that the length L is "1D00", the current address A is, 1010 ", and the difference M is +6, if 6 is compared with the current position Add the address A, and the obtained access address will be outside the ring buffer, that is, the access address is greater than the maximum address 値 (1111). Therefore, the generated address must be folded back to the starting position of the ring buffer. In the current example, when the turn-back action occurs, _2 papers are used; dit uses CNS (210X297 mm) ---------- f ------ ^ --- --- ^ (Please read the precautions on the back before filling in this page} Α7 Β7 43 66 9 Ο V. Description of the invention (3) (Please read the precautions on the back before filling in this page) An accessed bit The address is large + 1 * 4 = "1〇1〇" + 6-8 = "1000". Similarly, if the length L is "1 000", the current address 値 A is "1 〇1 (Γ and the difference When M is -6, the next accessed address is WM + L = ”1 010” + (-6) +8, 1100 ”, because the address has been returned to the end of the ring buffer. For example Explain how to calculate n, m, and B in equations i), ii), and iii): Suppose L = 1100 (that is, 12), A = 1000101 (that is, 69), and M = 101 (that is, 5). = 4 'from equations ii) and iii), υ = 4, and B = 1 0 0 0 0 0 0 0 (that is, 6 4). The operation of the circuit 100 in the first figure will be described below. The circuit 100 performs four main functions: (1) it decomposes the current address A into B components 値 (component) and a component): (2) it generates an absolute offset 値 (absolute offset) and a return offset Wrap offset: (3) According to one of two comparison actions, it adds one of the two offsets 値 to the base address 値 B; (4) It generates a foldback flag. The circuit 100 decomposes the current address A into a base address 値 B and an offset 値 ”a”, and the offset 値 is an offset between the current address A and the base address B. In the embodiment 'B' and a 'both are 14 bits wide. However, other different bit widths can be used. Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. The first one-bit element 1 β outputs a mask signal S, which is BU in the low bit and 0 in the high bit. In detail, the number of 1 値 in the mask signal S depends on the length 値 L. In an embodiment, the first one-bit component 16 may be a memory, such as a read-only memory (ROM), which contains an index table and generates an output value according to the input l 値. This paper size is applicable to China National Standard (CNS) A4 (210X297)

q η! LI A7 B7 Consumption cooperation between employees of the Central Bureau of Standards of the Ministry of Economic Affairs Du Yinfan 5. Description of the invention (4) The details are shown in the following table: L = 〇〇0000 0000 0000 Then S: 00 0000 0000 0000 L = 0〇0000 0000 0001 S S 200000 00 00 00 00 001 L-00 0000 0000 0010 S = 00 0000 0000 0001 L = 00 0000 0000 0011 S = 00 0000 0000 0011 L-00 0000 0000 0100 S = 00 0000 0000 0011 L = 00 οοοο 〇〇〇〇01 ?? Then S = 00 0000 0000 0111 L = 00 0000 0000 1000 Then S = 00 0000 0000 0111 L-00 0000 0000 1 ??? Then S = 00 0000 0000 1111 L = 〇〇0000 0001 0000 then S = 00 0000 0000 1111 L L-0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 then S = 0 0 0 0 0 0 0 0 0 1 mi L = 0 0 0 0 0 0 0 1 ???? then S = 0 0 0 0 0 0 0 0 1 1 mi L- 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Then S = 01 1111 1111 mi L = l? ???????? ???? Then S = ll 1111 1111 1111 In the above embodiment, a question mark? The representative bit must not be at the same time. For example, if L, 1 〇 Ο Γ (that is, 9), the output of the mask signal S is then 0 0 0 0 0 0 0 0 0 1 1 1 1. Similarly, if L? 1 000 0 ”(that is, 16), the output signal S is 00 0000 0000 1111. The cover signal s and the current address A are both inputs of the AND gate 20, and the gate 20 output bias. Shift 値 a. The offset 値 a is determined by the lowest n bit 値 of the current address A 其中, where 2 (n — n &lt; L &lt; = 2n. The inverse 値 of the current address A and the mask signal s is Input to the AND gate 18, and thus output the base address 値 B. From equation ii), it can be known that the lowest n bits of the base address 値 B are all 0. The following is an example to explain the calculation of B 値 and a 値: Suppose L = 1100 , I get S ^ llll, so a = "S and (AND) A, this paper size applies the Chinese national standard (CMS &gt; A4 specification (210X297 mm) —i. —I— I i L · ni -i ^ (Please read the notes on the back of the trace before filling out this page) 4 3 66 9 0 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs «. V. Description of the invention (5) II" 0001 1 1 1 and ΙΟΟΙΙΙΙΟΟΟΙΙΙ " And B = "NOT (S) and A" = "1110 0 0 and 1000 101, '=" 100 000 000 "The present invention generates an absolute offset 値 (a + M) and a fold Offset-shift- 値 U + M + -L). The adder 34 generates an absolute offset 値 (a + M). The selector 26 has a first input terminal that receives the inverse L 値 from the inverter 22 And a second input terminal input L 値. Based on a positive and negative bit signal 24 of a difference M, the selector 26 selects its first input or second input respectively. In the embodiment, 'M is 2 -2's-complement type storage, but other suitable types of storage can also be used. If M is negative, signal 24 is "1", and if .M is positive, signal 24 is "0" Therefore, when M is positive 値, selector 26 outputs negative L 値, and when M is negative ，, it outputs positive L 値. A first input signal of adder 28 is the output of selector 26 and a second The input signal is the difference M. Therefore, when M is positive, the output K signal of the adder 28 is ML, and when M is negative, the output K signal is K + L. The first input signal of the adder 36 is biased. Shift a, a second input signal is the output K signal of the adder 28. Therefore, when M is positive ，, the adder 36 outputs a rollback offset 値 (a + ML), and when M is negative 値When M is negative, the selector 30 outputs "0". When M is positive, the selector 30 outputs the length L. The comparator 32 compares a first and a second input, and When the first input is smaller than the second input, "Γ (眞) is output. Since the output of the selector 30 depends on the sign of M, the operation of the comparator 32 also depends on the sign of M. In detail, when M is negative, the comparator 32 compares "0" with (a + M). Therefore, when M is negative and 0 &lt; (a + M), the comparator 32 outputs “Γ. This is equivalent to: when the absolute offset of (a + M) 値 causes an address within the limit of the ring buffer, Comparator 3 2 outputs “Γ”. Therefore, when ΪΙ is positive, the comparator 32 compares "L," and 5 paper sizes to apply the Chinese National Standard (CNS) A4 specification (21 × 297 mm) (Please read the note on the back before filling this page. )-搫.

, 1T line A7 B7 5. &amp; Invention Description (a + M). Therefore, when μ is positive and L &lt; (a + M), the comparator 32 outputs "Γ. This is equivalent to: when (a + (j) 's absolute offset 値 results in an address outside the limit of the ring buffer The comparator 32 outputs "1". Depending on whether the outputs C and M of the comparator 32 are positive or negative, the selectors 38, 40, and 42 operate to determine the offset 値 na. The offset 値 na may be an absolute offset 折 or a return Offset 之一 One of the two. The output C of the comparator 32 is input to the selector 42 through the selection signal line 33, and its output is offset 値 na. The signal 24, which represents the sign of M, is input to the selector 38. The inverting input is input to the selector 40. The operations of the selectors 38, 40, and 42 are summarized in the following table: Positive and negative comparison output C of the offset C (negative two 1, positive two) 1 0 &lt; (a + M) 1 0 &lt; (a + M) 〇L &lt; (a + M) 〇L &lt; (a + M) 眞 False pseudo 眞 Γν / IV / fv ^ ίν 1 ο ο 1

a + M a + Μ + L a + M a + M — L ---------- Dream-(Please read the note on the back before filling this page) Consumption cooperatives printed as shown in the table, the output C does not indicate whether the absolute offset 値 will produce an address within the bounds. Similarly, the output C does not directly indicate whether the absolute offset 値 or the rollback offset 値 is adopted as the offset 値 na. According to the sign of Μ, the meaning of output C is confirmed. The OR gate 46 adds the base address B and the offset 値 na to generate a next access address on the signal line 48. The signal line 48 is stored in the A register 10 by the signal line 50 and becomes the new current address. The exclusive OR gate 44 inputs a first input signal c and a second input signal 24. The output of the mutex OR gate 44 represents the next address line. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297). ^ 3669 0 A7 B7 V. Description of the invention (Whether the return process occurs. Therefore, if the return Occurrence, the time 44 outputs 1 on the signal 49 'if it does not occur' the gate 44 is output on the signal 49, 0. "This signal 49 can be used by other components not shown in the figure-the present invention also It can be implemented in software, firmware, or similar methods. The preferred embodiment is to store the software in read-only (ROM) or random-access memory (Mm) and run by the central processing unit of a general-purpose computer, or It is executed by the central processing unit of a special-purpose computer system. When operating in software, it is explained by the following pseudo script: Break A into B and a if M &lt; 0 then if (a + M &gt; = 0) then na = a + M else na = a + M + L else if (a + M &gt; = L) then else

na = a + M-L na = a + M I --------- ^-(Please read the note on the back before filling in this X) Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs

Next—A + na + B Wrap = sign—bit xor C As those familiar with this industry know, the process of the above virtual code is equivalent to the operation of the circuit in the first figure. The second figure reveals that the circuit 200 of the present invention includes a register 210, 212, and 214:-the first one-bit element 216; and (AND) gates 218, 220: an inverter 222;-a selector 226;-an adder 228 -Adder 234 and if this paper Wit instructs Lai Family Materials (CNS) Qx 297 (publication) 4366 9 ο Α7 Β7__ 5. Description of the invention (8) 236;-Selectors 260, 262; or gate 246. The register 210 stores a 値 A, which represents the current access address of the ring buffer. The register 212 stores one L, which represents the length of the ring buffer. The register 214 stores a μM, which represents the difference between the next access location and the current address A. The difference M can be positive or negative. The above A 'L and M 値 will be explained in conjunction with the third figure in the following two paragraphs. The operation of the circuit 200 in the first figure will be described below. The circuit 200 performs four main functions: (1) it decomposes the current address A into B components 値 (component) and a component 値; (2) it generates an absolute offset 値 and a folded-back offset 値; (3) it A foldback flag is generated; (4) According to the foldback flag, it adds one of the two offsets 値 to the base address 値 B. The operation of some components in the second diagram is the same as that of the corresponding components in the first diagram, and their related operations will not be repeated. A second embodiment of the present invention includes a circuit that generates a retrace flag 264. When the difference M is negative, if a foldback occurs, the carry bit 270 'of the adder 234 is "1". This is because the adder 234 is underflow. If no turn-back occurs, the adder 234 does not cause an underrun, and the carry bit 270 has 値. When M is positive, if a turn-back occurs, the carry bit 272 of the adder 236 has "0", because no underrun occurs. If no foldback occurs, the adder 236 causes an underbit, so the carry bit 272 has "1". The carry bit signal 272 is subjected to an inverse phase operation before being input to the selector 260. When M is positive, M positive and negative signals 224 have “0” 値, and when M is negative, M positive and negative signals 224 have “Γ”. Depending on whether M is positive or negative, selector 260 selects the carry bit 270. And inverse 値 272, which becomes the retracement flag 264. Therefore, the retracement flag 264 indicates that the retracement offset should be adopted 逍 8_ This paper is scaled to the Chinese National Standard (CNS) Α4 size (210X297 ^ 7 --------- ^ ------ 1Τ ------ ^ (Please read the precautions on the back before filling out this page) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4366 9 〇 Α7 Β7__ 5. Description of the invention (Clever) Or use absolute offset 値. According to the return flag 264, the selector 262 selects to output the absolute offset 値, or the return offset 値 to the OR gate 246 for the base. Add B. The present invention can also be implemented in software, firmware or similar methods. The preferred embodiment is to store the software in read-only (ROM) or random access memory (ram) ' The CPU is executed by the central processing unit of a special-purpose computer system. When running by software, the following virtual (p seudo) instruction code to explain:

Break A into B and a if M &lt; 0 then if (a + M &lt; 0) then

wrap = 1 na = a + M + L else

wrap two 0 na = a + M else if (a + M_L <0) then wrap = 0

na: a + M else

wrap = l na = a + M-L

Next—A = na + B As the person familiar with this industry knows, the above virtual code flow is equivalent to the operation of the circuit in the second figure. This paper size applies to China National Standard (CNS) Α4 specification (210X297 mm) ---------- ^ ------ tr ------ ♦ (Please read the (Notes need to be filled in this summer) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives

Claims (1)

Charge ^ 6 3 4 〇 8 〇 0 88 ABICD Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Application for Patent Scope Amendment of Patent Scope (2000/9 / 1) 1 · —A kind of access to ring buffer The next address generating device includes: a circuit for storing a length L of the ring buffer; a circuit for storing a current address A of the ring buffer; a circuit for storing the current address A and the next A decomposing circuit to generate the difference between addresses; _ decomposition circuit for decomposing the current address A into a base address B and an offset 値 a from the base address, the decomposition circuit includes a first-bit component, which Take L 値 as an input signal for outputting a mask signal S. This mask signal has &quot; K 値 in its lowest (nI) bit, where 2s · 1 &lt; LS 2 &quot;; a circuit according to the length L And the difference M to determine an absolute offset 値; a circuit to determine a folding offset 依照 according to the length L and the difference M: a first comparison circuit that operates when the difference M is negative 供 for determining the absolute Whether the offset 产生 produces a single bit address in the ring buffer; Circuit, which operates when the difference M is positive, for determining whether the absolute offset 产生 generates a bit address outside the ring buffer; the addition circuit, according to one of the first and second comparison circuits It operates for adding one of the base address 値 B to the absolute offset 値 and the folded-back offset 产生 to generate the next address. 2. The device as described in item 1 of the scope of the patent application, wherein the decomposition circuit further includes a logic gate, which is connected to the circuit storing Α ，, and is connected to the first-order component, and outputs an offset 値 a 3. If applied The device described in the first paragraph of the patent specification, wherein the decomposition circuit further includes a logic gate, which is connected to the circuit storing the A 适用, and applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) to this paper size. ------------ · -------- Order --------- Line {Please read the notes on the back before filling this page) 43 66 9 0 Jaw C8 D8 6. The scope of patent application starts from the first-bit component connection, and the output base 値 B. (Please read the back of the page; I will fill in this page first)-^ --------- Order · -------- ~ Printed paper scale Applicable to China National Standard (CNS) A4 (210 X 297 mm)