TW434900B - Insulated gate bipolar transistor with controllable latch - Google Patents

Abstract

A kind of insulated gate bipolar transistor with controllable latch includes the followings. A thyristor has a first region with the first conduction type, a second region with the second conduction type formed on the first region, a third region with the first conduction type formed on the second region, and a fourth region that has the second conduction type and contacts with the third region.A P-N junction is formed on the fourth region. The first and the third regions individually contact with the first and the second electrode regions. The functional means of the first field effect transistor can conduct the fourth region to the second region by responding to a turning-on bias signal. The functional means of the second field effect transistor is set between the fourth region and the second region, and can turn-off the thyristor by responding to a cutting-off bias signal. The insulated gate bipolar transistor provided by this invention is characterized in having a high-voltage tolerance, a low conducting voltage drop, and a controllable latch.

Description

4349〇 V. Description of the Invention ⑴-Field of the Invention The present invention relates to a power electronic device, and more particularly to an insulated gate bipolar semiconductor device capable of controlling a flash lock. BACKGROUND OF THE INVENTION The development of semiconductor devices for high-power applications such as motor drive circuits and lighting equipment began with bipolar junction transistors (BJT). Although bjT can meet many requirements, there are also many basic defects that make it difficult to meet all high-power applications. For example, ‘B J T is a current control element whose driving circuit is more complex and expensive, and the input impedance is still too low. Power metal-oxide-semiconductor field-effect transistors (POWER, MOSFET) have been proposed to solve the existing difficulties. In a power MOFET, a gate electrode bias is used to control the opening and closing elements. Although the power MOSFET has many advantages, it is canceled by its rather high on-resistance. This is due to its lack of a minimum carrier transmission, and as a result, the forward current density of the device is limited. Based on the characteristics of power BJT and M0SFET, a hybrid element combining bi-carrier current conduction and Mos control current flow has been developed and offers significant advantages over β or M0SFET 'Insulated Gate Bipolar Transistor (Insulated Gate Bipolar Transistor) Transistor (IGBT) and Emitter Switching Thyristor (EST) are two of them. '' A typical IGBT is shown in the first figure 'It includes p + collector region 10' N + buffer layer 12, N-drift layer 14, P-type base region 6 and ... emitter region-domain 1 8 ' A gate electrode 20 is provided above the base region 16 and a free oxide layer 22 is formed between the two. The metal layers 24 and 26 on the two sides of the element are the emitter and collector respectively.

Page 5 43 49 〇 〇

V. Description of the invention (2) Polar region. Due to the conductivity modulation of the drift region of the IGBT in the on-state, its on-state loss (⑽103) is much lower than the power MOSFET. Even so, 'lower conduction losses are still expected to be achieved with gate fluids' because the gate fluids provide a higher degree of conduction modulation and lower forward pressure drop than IG β τ when opened.

The second figure provides a schematic diagram of the structure of EST, which includes p + anode region 30, N + buffer layer 32, N-drift layer 34, P-type base region 36, N + floating region 38, and N + cathode region 40. 'The gate 42 is located above the floating region 38 and the cathode region 40' and the gate oxide layer 44 is interposed therebetween, and the metal layers 46 and 48 are the cathode, anode, and electrode regions, respectively. Unfortunately, due to the presence of a parasitic fluid, this element may latch up and fail to close, resulting in burnout. · As shown in the third figure, 'I GBT can suppress the flash-lock phenomenon after using the trench gate 20', but its on-resistance modulation effect is still difficult to compare with EST 'and its trench needs to withstand higher Voltage. However, due to the characteristics of the EST, it is impossible to form a gate with a trench, so the latch-up effect is inevitable. There are many other efforts to improve the lack of IGBT or EST. Bauer et al. Embedded a recombination layer in the IGBT in U.S. Patent No. 4,985,74 to prevent latch-up. Sakurai also suppresses IG BT in U.S. Patent No. 5,0 8,9,8 6 4 Latch-up,

Fu j lhira et al. Detected load current in U.S. Patent No. 5, 〇97,302 to avoid IGBT burnout 'Sakurai improved conduction modulation in U.S. Patent No. 5,200,632, Hiraki et al. And Iwamura respectively Specialized in the U.S.

Page 6 434c V. Description of the invention (3) Profit numbers 5, 2 8 2, 0 1 8 and 5, 6 5 9, 1 8 5 Increase the trench depth and double gate to reduce the IGBT on-resistance, Ba 1 The ESTs proposed by iga in U.S. Patent No. 5,306,930 and She kar et al. in U.S. Patent Nos. 5,293,055 and 5,2 94,8 1 6 use a variety of different mechanisms to suppress the For the latch-up effect, Otsuki et al. Integrated IGBT and EST in US Patent No. 5, 378, 90 3, and Shekar et al. Also in US patent. Tiger code 5, 471,075 using a dual channel trench FET to suppress the interlocking effect of EST & Sakurai et al., Seki and Iwamura use double gates in U.S. Patent Nos. '5,459,339, 5,349,212 and 5,644,150 respectively Drag the fluid structure and the IGBT state to reduce the on-state voltage drop of the device. Aj 丨 'corpse, Patent No. 5, 719, 41 1 Eliminate the interstitial fluid of EST's parasitic fluid ^ In US Patent No. 5, 844, 258 In the control of the hole current flowing into the cathode of the main fluid before entering the main fluid to avoid the parasitics of the EST, the fluid cannot be eliminated. These techniques cannot solve all the problems mentioned above at the same time. Double-resistance, low-conductance, low-conductance, = dusting, high-conduction-current-density, and unaffected by flash-lock are expected. Electricity is still the purpose and summary of the invention. In view of the above-mentioned shortcomings, the present invention provides an insulated gate bipolar transistor for controlling flash locks. For direct applications, it can be said in detail that this gate fluid has a first lead and a second lead. Body structure, the second report of the second conductivity type on the first region-the third region of the first conductivity type formed on the first region, formed in the second region to contact the third region to form N Receiving one conductive one type of the fourth and first two areas respectively

43 4 V. Description of the invention (4) Contacting the first and second electrode regions; the other two field effect transistor structures are used to control the opening and closing of the gate fluid. Among them, the first field effect transistor responds to an open bias signal. And the fourth region to the second region is turned on, and the second field effect transistor is interposed between the fourth region and the second electrode region, and the gate fluid is closed in response to a cutoff of the bias signal. Both field-effect transistors can use planar gates or trench gates. When the two field-effect transistors are turned on, the gate fluid formed by the first to fourth regions is turned on, and the voltage drop thereon is very low; and by changing the gate voltage of the second field-effect transistor, the electrons of the gate fluid can be cut off. The flow path forces the sluice fluid to close so that this semiconductor element has the ability to control the latch. Therefore, the present invention can achieve the objectives of high input impedance, low on-voltage drop, high voltage resistance, high on-current density, and controllable latch-up. Brief Description of the Drawings For those skilled in the art, the present invention will be more clearly understood from the detailed descriptions made with the accompanying drawings, and its various purposes and advantages will become more apparent. 1. Schematic description: The first diagram is a cross-sectional view of a typical IG B T. The second figure is a cross-sectional view of a conventional EST. The third figure is a cross-sectional view of a conventional trench type I G B T. The fourth figure is a sectional view of a preferred embodiment of the present invention. The fifth figure is a sectional view of another embodiment of the present invention. The sixth figure is a sectional view of another embodiment of the present invention. 2. Drawing number description:

Page 8 434900 V. Description of the invention (5) 10 Collector 1¾ Domain 14 Drift layer 18 Emitter region 22 Gate oxide layer 26 Collector electrode region 32 Buffer layer 36 Base region 40 Cathode region 44 Gate oxide layer 48 Anode Electrode region 52 P + substrate 12 Buffer layer 16 Base region 2 0/20 * Gate 24 Emitter electrode region 30 Anode region 34 Drift layer 38 Float region 42 Gate 46 Cathode electrode region 50 Drift layer 54 Buffer layer 58 N-type Well 62 N + region 66 Insulating layer 70 Insulating layer 74 Second electrode region 78 Planar gate

56 P-type well 60-P-type base region 6 4 Planar gate 6 8 Trench gate 72 First electrode region 76 N + region 8 0 Trench gate Detailed description The fourth figure provides a cross-sectional view of a preferred embodiment of the present invention . The formation of this element is to deposit an N-drift layer 50 on a P + substrate 52, and to form an N + buffer layer 54 between the drift layer 50 and the substrate 52 as in the general IGBT or EST structure. A p-type well 56 is formed on the other side of the drift layer 50, and then? Wells 58 of two opposite conductivity types are sequentially formed in the well 56? Base region

Page 9 4349 Ο ο V. Description of the invention (6) The surface 60, the P-type base region 60 and the N + region 62 are formed on the surface of the type well 56 and the surface adjacent to the drift layer 50 to form a planar gate 64. An insulation layer 66 is interposed between the gate electrode 64 and the surface of the P-type well 56, and the area near the gate electrode 64 on the surface of the P-type well 56 forms a channel controlled by the gate electrode 64. Another control function of this element is through the trench gate 68. The trench passes through the N + region 62 and the P-type base region 60 from the surface of the N + region 62 and enters the N-type well 58. The trench has a bottom surface. And a side wall, an insulating layer 70 is formed between the gate 68 and the gate 68, so that a channel controlled by the gate 68 is formed outside the side wall of the trench. As shown in the figure, in this embodiment, the gate electrodes 6 4 and 6 8 are connected to the same electrode signal. This can be achieved by connecting the gate electrodes 64 and 68 with a conductive layer (not shown in the figure). Those who are generally familiar with integrated circuit technology should understand that it will not be described in detail. In different embodiments, the gates 64 and 68 can also be controlled by two different electrodes G1 and G2, respectively, so as to obtain different transistor characteristics. Finally, metal layers 72 and 74 are formed above and below the element as electrode regions of the element, respectively, wherein the first electrode region 72 contacts the P-type well 5 6, the P-type base region 60 and the N + region 62 above. Surface, and the second electrode region 74 contacts the P + substrate 52. The operating principle and process of this element will now be explained. When a suitable voltage is applied to the gate electrodes G1 / G2, the channels controlled by the gates 64 and 68 are opened, and electrons are injected from the N + region 62 through the channel controlled by the gate 68 into the N-well 58 'and then The channel controlled by the gate electrode 64 is injected into the drift layer 50. On the other hand, the “hole” follows the opposite direction of the electron path, and is injected into the P-type well 56 from the drift layer 50 and then flows out from the metal contact of the ρ-type well 56, thereby initiating the ρ-type

Page 10 V. Description of the invention C7) The junctions of the well 56 and the N-type well 58 are forward biased, which in turn causes the sluice fluid formed by the base 52, the drift layer 50, the P-type well 56 and the N-type well 58 to conduct. Once the brake fluid is turned on, a latch-up phenomenon occurs, and the pressure drop thereon will be very low. On the other hand, the gate fluid can use the gate 68 to intercept its electronic flow path and close the element. In other words, the insulated gate bipolar transistor has the ability to control the latch. Compared with trench type I GBT, the transistor provided by the present invention does not need a trench withstand south voltage, and has a lower on-state voltage drop d. Compared with £ 3, the transistor provided by the present invention not only has a lower The on-state voltage drop, and the uncontrollable latch-up will not cause the component to burn out. The embodiment shown in the fourth figure is based on a P-type substrate to form this semiconductor element. In other embodiments, an N-type substrate can be used to manufacture this element. At this time, the N-type substrate is used as a drift layer. An N + buffer layer and a P + layer are sequentially formed on one side, and the structure on the other side of the N-type substrate is formed as in the previous embodiment. h The description of the device shown in the fourth figure can find the characteristics of the present invention. An insulated gate bipolar transistor with a controllable latch includes a gate fluid f structure and at least two field effect transistor structures. The gate electrode 64 Correspondence—The N-well 58 is electrically connected to the drift layer 50 through the channel by turning on the bias signal, and another field-effect transistor is located between the electrode region 72 and the N-well 58, and its gate 68 can be cut off according to a The bias signal blocks the electronic flow path of the gate fluid, forcing the gate fluid to close, thereby preventing uncontrollable latch-up. In order to cut off the electronic flow path of the gate fluid, the second field-effect transistor can also use a planar gate. The fifth figure shows a cross-sectional view of the embodiment. In this component

Page 11 4 3 49 ^ 0 V. Description of the invention (8) ~ '— In the structure of the gate fluid and the first field-transmitting crystal is the same as that shown in the fourth figure, but the second field-effect transistor is replaced by a planar gate. 78, which is located above the surface of the p-type base region 60 and controls two paths from ... region 76 to 1 ^ -type well 58. The gates 64 and 78 of the two field-effect transistors can be formed using the same layer of polycrystalline silicon. This simplifies the manufacturing process. "Although the previous embodiment uses a planar gate 64, those skilled in the art know that in the embodiment, The planar gate 6 4 can be replaced by a trench gate. The sixth figure shows this situation. In this transistor, the gates 68 and 80 of the two field-effect transistors use trench gates. The above description of the preferred embodiment of the present invention is for the purpose of clarification, and is not intended to limit the present invention to exactly the disclosed form. Modifications or changes are possible based on the above teaching or learning from the embodiments of the present invention. The embodiments are selected and described in order to explain the principles of the present invention and allow those skilled in the art to utilize the present invention in practical applications in various embodiments. The technical idea of the present invention is intended to be covered by the following patent applications and their equivalents. Decide.

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Claims (1)

434900 VI. Scope of patent application Patent scope: Body guide half: Includes the body area crystal body electric body · 'Sub guide surface half surface double one two gate first edge one of the absolute state and type one lock electric latch Guide one system, one control, one field, one field, one field, one field, one half of the half and two fields, and one side surface type meter The state of the electric field; the electric field of the electric field, the electric field of the electric field, the electric field of the electric field, the electric field of the electric field, the electric field of the electric field, the electric field of the electric field, and the electric field of the electric field. " The first one should have and the upper domain body guide *, the half-field three-area body should lead to the semi-quaternary state type & * & ^ 3, the second second body should have the upper domain The four-dimension body of the semi-domain should be in the form of a semi-five-shaped dipole. The first-dimension conductor of the five-section body should have the upper-dimension body. S = ° and crystal 'electrode effect gate field one by one The fourth and third body guides are sixty-sixth to the fourth. The fourth body and the pole gate day 0a, the second electric field in the field, the second ditch, the first and the eleventh, are formed in the domain-shaped area. The first contact domain region is first pole and the first domain M body region is a conductor M half and a half. The first and the U domain contact region 1J is connected to the body zone guide region. Shen, 1 such as 2 and its neighboring electron region Page 3--Article 43490 ο 5. The scope of patent application is for those who are in favor of others. As described in item 范围 of the scope of patent application, it includes a functional means for electrically connecting the " j-edge bipolar transistor. In this, the second inter-electrode system—a planar open-phase insulating inter-bipolar transistor—is an insulated gate double gate trench gate capable of controlling latch-up. A second transistor having a first conductivity type includes: a second conductivity type formed on the first region and _, an electrical type, and a second conductivity type-formed on the second A first well in the region and having a core conductivity state is formed in the first well and a second well is formed in the second well and has a two conductivity type; A region one is formed on the surface of the third region and a summer region; is a first and second well and a second region electrode formed above the surface of the first well, the first gate electrode and one formed in a trench The second gate electrode / ^: the first field-effect transistor; and the third and fourth regions form a first intermediate electrode and the second well _ ^ A-shaped pleasure-field-effect transistor salt, and the second electrode electrode layer contacts the The second well and the third and fourth regions and a second electrode layer contact the third region. ^ In the insulated brake double carrier as described in item 5 of the scope of the patent application, the area adjacent to the second area and the second area is clear, the fourth one is the conductive type, and the fourth one is 4349. Patent application scope 7. The insulated gate bipolar transistor described in item 5 of the patent application scope further includes a functional means for electrically connecting the first and second gate electrodes. 8. An insulated gate bipolar transistor with controllable latch formed on a semiconductor substrate. The insulated gate bipolar transistor with controllable latch includes: a gate fluid having a first A first region of a conductive type, a second region of a second conductive type formed on the first region and opposite to the first conductive type, a second region of a conductive type formed on the second region and having The third region of the first conductivity type and a fourth region with the second conductivity type contact the third region and form a PN junction. The third region and the first region respectively contact a first region. An electrode region and a second electrode region; a first field-effect transistor function means having a first gate plant, which turns on the fourth region to the second region in response to an open bias signal; and-has a second The second field effect transistor function of the gate is interposed between the fourth region and the second electrode region, and the gate fluid is closed in response to a cutoff bias signal. 9. The insulated gate bipolar transistor as described in item 8 of the scope of the patent application, wherein 1 the first interpole is a plane interpole or an edge trench gate. I 0. The insulated gate bipolar transistor as described in item 8 of the scope of patent application, wherein the second gate is a planar gate or a trench gate. II. The insulated gate bipolar transistor described in item 8 of the scope of patent application, further comprising a functional means for electrically connecting the first and second gate electrodes. Page 15