4348 ㈣五、發明説明（ 發明箱Μ : Α7 Β7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 本發明與一種半導體製程有關，特别是一種罩幕唯讀 記憶體（mask read only memory ; mask ROM)之製程。 發明背景： 由於新應用領域與未來的驅動著"I己憶元件不斷地發展 ，在電腦與通訊相關產業中需要大量之記憶元件，例如電 腦之介面未來朝影音控制方面發展，上述之控制介面將需 要大量之記憶元件。爲了獲得高性能的積體電路並提高晶 圓的構裝密度，在超大型積體電路（ULSI)技術中，半導體 元件的尺寸不斷的縮小。 一般之軍幕唯讀記憶體具有兩種不同之啓始電壓 (threshold voltage)於記憶元件陣列之中。第一種元件形 成於一 區之中，另一種元件具有不同之啓始電壓則形 成於另一主動區之中。例如，第一種元件爲一般之元件具 有啓始電壓vu，第二種元件則具有啓始電壓Vt2，其中上 述之啓始電壓Vtl與啓始電壓Vt2不同。因此第二種元件在 製作過程時需要一1墓用來進行離子植入以達到不同啓始 電壓之θ的。此方法涉及在電晶體中摻雜一高量之硼離子 以提昇啓始電壓，一般稱爲啓始電壓編程 (threshold voltage programming) ° 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） ----丨；---”裂------ίτ------—Μ' 一 . (請先閱讀背面之注意事項再填寫本頁) 34348 ㈣5. Description of the Invention (Invention Box M: Α7 Β7 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs This invention is related to a semiconductor process, especially a mask read only memory (mask ROM) Background of the Invention: As new application fields and the future drive “I ’ve continued to develop components, a large number of memory components are required in the computer and communication related industries, such as the interface of computers in the future toward audio and video control. The control interface will require a large number of memory components. In order to obtain high-performance integrated circuits and increase the density of wafers, the size of semiconductor components in the ultra-large integrated circuit (ULSI) technology continues to shrink. The read-only memory has two different threshold voltages in the memory element array. The first element is formed in one area, and the other element has a different start voltage in another active area. For example, the first element is a general element with a starting voltage vu, and the second element has The starting voltage Vt2, where the above-mentioned starting voltage Vtl is different from the starting voltage Vt2. Therefore, during the manufacturing process, a tomb is used for ion implantation to achieve different starting voltages θ. This method It involves doping a high amount of boron ions in the transistor to increase the starting voltage, which is generally called threshold voltage programming ° This paper size applies to China National Standard (CNS) A4 (210X297 mm)- --- 丨; --- "Crack ------ ίτ -------- Μ '1. (Please read the notes on the back before filling this page) 3
A7 B7 五、發明説明（） 習知製程用以達到上述之目的可以參閱美國專利 55〇6438號專利以及美國專利 55 3 89〇6號專利，分别 由Noda與Aoki提出。在R〇M之製程中通常利用高劑量 之硼離子摻雜來達到不同啓始電壓之目的。 當使用高劑量之硼離子摻雜’造成啟始電壓之上升 ，因此，需要在閘極上加更大之電壓以控制電晶體開關 ，高的閘極電壓易在位元線間容易產生較高之漏電流， 且高的閘極電壓，造成通道内横向電場增加，這使得通 道内電子從電場所獲得之能量增加，產生熱電+子，這熱 電子在撞擊其他電子，產生載子倍增現象，造成崩潰電 壓—T降。如同由She u所提出之美國專利5597753號專利 ，其中述及高漏電流將導致很高之等待電流 (standby current)。另外的問題則是與編程摻雜 (code implantation)有關。由習知技術所知，在編程樣雜 之後將會執行一熱處理用以將離子活化。而此通常造成 鄰近位元線的counter doping，因此增加位元線之電阻 而降地ROM之性能。一與上述議題有關之文獻可以參 閲美國專利5 5 7 1 7 3 9號專利。 發明目的及概述： 本發明之目的爲提供一種軍幕唯讀記憶體製程。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) .裝. 訂 經濟部智慧財產局員工消費合作社印製 434836 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 一氣化層形成在NMOS元件區域以及NMOS記憶胞區 域，一禕晶矽層利用化學氣相沈積法沈積於氧化層之上， 隨後一薄的f.化矽層沈積於上述之複晶矽層之上，一光阻 圖索形成在NMOS元件區域之上及暴露出JsTMDS記惰：胞_尾 域。利用蚀刻製程蝕刻在於NMOS記憶胞區域上之氣化矽 屉以及複晶矽層，再將光阻圖案去除。 經濟部智慧財產局員工消費合作社印製 隨後執行一全面性ϋ型離子換雜將離子植入上述之NMOS 元件區域以及NMOS記憶胞區域，形成輕微摻雜汲極（LDD) 區域。此低劑量之離子摻雜可以增加表面之硼離子濃度以 利編程（coding)。一鱗..程_,氣化層（coding oxide)利用一熱氧 化法於氧環境中形成於NMOS記憶胞^區媸之上，編程氧化 屠（coding oxide)之厚度約爲200至800埃，此厚度較閘極 氧化層厚。隨後利用i礎故氮化矽層去除。接著，一第 二.複晶矽層形成於NM0S元件區域以及NM0S記憶胞區域.形成 閩極_結構於NMOS元件區域以及該NM0S記憶胞區域上；接著 執行第二汝離子換雜以形成LDD於NM0S元件區域及NM0S記 憶胞區域中鄰接該閘極結構下方之底材内；並形成間 jf於該閘極結構之侧壁上；再執行篇-三dt.聋ϋ.. .雜以形成 汲極虡源極..於NM0S元件區域及NM0S記憶胞區域之底材内； 最後並執行一熱處理以活化摻雜之離子。 使用上述之間.極結構做爲一翼冪’對NMOS元件區域 以及NMOS記憶胞區域進行一第二次離子摻雜以形成n 本紙張尺度適用中國國家榇準（CNS ) A4規格（210X297公釐） 434agg 五、發明説明（） A7 B7 型LDDi及極區域於間極4士禮士咖△ .^ 極、構 < 附近。形成側壁間隙趴Μ Λ 結構之侧壁。執行第=次龜 像於閘極 币—次離子摻雜以成汲極 ’在、〇2或\〇之環谙φ决, 丹碟極區域 “ :2 2環境中進行—高溫熱回火程序，w 1 化離子形成淺接面元件。 斤，以活 .邏__式筋_單説朗： 藉由以下詳細之描述結合所附圖纟，將可輕 本發明之内容及此項發明之諸多優點，其中： 了解 經濟部智慧財產局員工消費合作社印製 第一圖爲本發明形成間極氧化層與複在 上之截面圖。 于等體底本 第二圖爲本發明形成氮化矽層於複晶矽層上之截面圖。 第三圖爲本發明形成光阻圖索之截面圖。 ° 第四圖爲本發明執行第一次離子植入之截面圖。 第五圖爲本發明形成編程氡化層之截面圖。 第六圖爲本發明形成第二複晶矽層之截面圖。 第七圖爲本發明執行第一次離子植入之截面圖。 第八圖爲本發明形成側壁間隙與執行第三次離子植入之； 面圖。 第九圖爲本發明執行熱處理之截面圖。 第十圖爲本發明不同編程條件下之電流電壓曲線圖。 發明詳細説明： 本發明提供一兩次編程（double coding processes)植入 本紙張尺度適用中國國家標準（CNS ) A4规格（210X2.97公釐） {請先聞讀背面之注意事項再填isf本頁} 、-=*. -絲— ϋ/A7 B7 V. Description of the invention () For the conventional process to achieve the above purpose, please refer to US Patent No. 5506438 and US Patent No. 55 3 8906, respectively, proposed by Noda and Aoki. In the ROM process, high-dose boron ion doping is usually used to achieve different starting voltages. When using a high dose of boron ion doping, the initial voltage is increased. Therefore, a larger voltage needs to be applied to the gate to control the transistor switch. The high gate voltage is easy to generate a higher voltage between the bit lines. Leakage current and high gate voltage cause the lateral electric field in the channel to increase, which increases the energy obtained by the electrons in the channel from the electrical field, generating thermoelectric + electrons. These hot electrons collide with other electrons, resulting in carrier multiplication, causing Breakdown voltage—T drops. As U.S. Patent No. 5,577,753 filed by Sheu, it is mentioned that a high leakage current will result in a high standby current. Another problem is related to code implantation. As is known in the art, a heat treatment is performed after the programming sample to activate the ions. This usually results in counter doping of adjacent bit lines, thus increasing the resistance of the bit lines and degrading the performance of the ROM. A reference to the above issues can be found in U.S. Patent No. 5,575,179,39. Object and summary of the invention: The object of the present invention is to provide a military curtain read-only memory system. This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page). Packing. Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives printed 434836 A7 B7 V. Invention Explanation () (Please read the precautions on the back before filling in this page) A vaporization layer is formed in the NMOS device region and the NMOS memory cell region. A crystalline silicon layer is deposited on the oxide layer by chemical vapor deposition. A thin f. Siliconized layer is deposited on the above-mentioned polycrystalline silicon layer, a photoresist pattern is formed on the NMOS device region and the JsTMDS register: cell_tail region is exposed. The etching process is used to etch the vaporized silicon drawer and the polycrystalline silicon layer on the NMOS memory cell area, and then the photoresist pattern is removed. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then a comprehensive ϋ-type ion doping is performed to implant the ions into the above NMOS device region and NMOS memory cell region to form a lightly doped drain (LDD) region. This low-dose ion doping can increase the boron ion concentration on the surface to facilitate coding. A scale .. Cheng_, a gasification layer (coding oxide) is formed on the NMOS memory cell ^ in a oxygen environment using a thermal oxidation method, and the thickness of the coding oxide is about 200 to 800 angstroms. This thickness is thicker than the gate oxide layer. Subsequently, the silicon nitride layer is removed using a silicon substrate. Next, a second. A polycrystalline silicon layer is formed on the NMOS device area and the NMOS memory cell area. A min-structure is formed on the NMOS device area and the NMOS memory cell area; then a second Ru ion doping is performed to form an LDD on The NM0S element area and the NM0S memory cell area are adjacent to the substrate below the gate structure; and the intermediate jf is formed on the side wall of the gate structure; and then the chapter-three dt. Deafness .. The source electrode is in the substrate of the NMOS device region and the NMOS memory cell region; finally, a heat treatment is performed to activate the doped ions. Use the above-mentioned pole structure as a wing power to perform a second ion doping on the NMOS element area and the NMOS memory cell area to form n. This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm). 434agg V. Description of the invention () A7 B7 type LDDi and pole area are near the pole 4 shi Lishi ca △. ^ Pole, structure < near. A sidewall gap is formed on the sidewall of the M Λ structure. Carry out the second turtle image on the gate coin-doping with secondary ions to form a drain electrode in the ring of 〇2 or \ 〇, Dan plate region ": 2 2 environment-high temperature thermal tempering In the procedure, the w 1 ion is used to form a shallow junction element. Jin, to live. Logic __type tendons_Shan Shuolang: By combining the following detailed description with the attached drawings, the content of the present invention and the invention can be lightened. Many advantages, among them: understand the first picture printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is a cross-sectional view of the formation of the interlayer oxide layer and the superimposed layer. A cross-sectional view on a polycrystalline silicon layer. The third view is a cross-sectional view of a photoresist pattern formed by the present invention. The fourth view is a cross-sectional view of the first ion implantation performed by the present invention. The fifth view is a view of the formation of the present invention. A cross-sectional view of a programming halide layer. A sixth view is a cross-sectional view of forming a second polycrystalline silicon layer according to the present invention. A seventh view is a cross-sectional view of performing the first ion implantation according to the present invention. The eighth view is forming a sidewall of the present invention. Gap and execution of the third ion implantation; a front view. The ninth view shows the implementation of the present invention Sectional drawing of processing. The tenth figure is the current and voltage curve diagram under different programming conditions of the present invention. Detailed description of the invention: The present invention provides one or two programming (double coding processes) implanted on the paper scale applicable to Chinese National Standard (CNS) A4 Specifications (210X2.97 mm) {Please read the precautions on the back and fill in the isf page} 、-= *.-丝 — ϋ /
五、發明説明（） 在半導體底材上製造罩幕唯讀記憶體之方法。因高劑量所 造成之counter doping將會被抑制。.本發明將利用一較佳 實例闡明如下，然其並非用以限定本發明精神與發明實體 ，僅止於此一實施例爾，熟習該項技藝者，在本發明之精 神之下，可以任意變更其設計。在一較佳之具體實施例中 ，提供一具 <】〇〇>晶向之單晶矽底材2，底材2被區分爲兩 個主要之部份，分别爲ΜΜΏ.&元件-區域200以及NMOS記憶 胞區域210，NMOS記憶胞區域210爲用來編入資料如1或〇 之區域。然後，藉著使用埶氳化法在預定之區域上製作厚 場氡化區（FOX)4。一般而言，利用氡化層以及氮化矽層 作爲氮化罩_基，藉著在蒸氣環境中進行熱氧化可形成厚度 約3 000至8 000埃的FOX區4，如第一圖所示。做後再用熱 磷酸及HF可以將上述之罩幕分别去除。 一氣化居6於氧環境之中氧化形成在NMOS先件區域 200以及NMOS記憶胞區域210做爲閘極氧化廣。溫度约8〇〇 至1 1 00度C，其次也可以利用化學氣相沈積法以te〇S爲反 應物在溫度600至800度C間形成上述之氧化層6，製程壓 力約爲0.1至10托耳。在此實施例中氡化層6厚度約爲15至 200埤。 在形成上述之氧化層6之後，一複—晶硬故利用化學 氣梱沈積法沈積於氧化層6之上。一薄的氮化發屉i 〇接 著沈積於上述之複晶矽層8之上。氮化矽層1 〇通常可以 利 用 低壓化 學氣相 沈積法 本紙張纽適用悄國家標準（CNS )八4祕（21〇x297公^厂 __；_ 請 先 閲 讀 背 © 之 注 意 事 項 再 裝 頁 經濟部智慧財產局員工消費合作社印製 43 Μ Α7 Β7 五、發明説明（） (Low Pressure Chemical Vapor Deposition ； LPCVD) 請 先 聞 讀 背 之 注 意 事 項 再 填 寫 本 頁 、 電漿增 強式化 學氣相 沈積法 (Plasma Enhance Chemical Vapor Deposition； PECVD) 、或其他適合之方法形成。氮化矽層10之厚度約爲 200 .至 1500埃。製程溫度約爲300-800。〇，反應之物質通 常爲 SiH4，NH3, N2, N20 或 SiH2Cl2, NH3, N2，N20。 參閲第三圖，一光J且屬_案12形成在JSIMOSL件區域200 之上及暴露出NMOS記憶胞區域2 1 0。在利用蝕刻製程蝕 里在於NMOS記憶胞區域23〇上之氣化矽屠1〇以及複晶矽 層8，再將光阻圖案12去除。 參閲第四圖，隨後執行一全面性型^雜..子將離子 植入上述之NMOS元件區域200以及NMOS記憶胞區域210 ，形成輕微摻雜汲極(IJDD)區域1J。此低劑量之離子摻雜 可以增加表面之硼離子濃度以利編程（coding)。可以在此 實施例中以摻雜輕微劑量之離子較佳，摻雜之雜質可以 爲BF2或硼。該離子植入之劑量約爲5E12至_ 5E14 atoms/cm2 ，且該步驟之能量大約爲5至120 KeV。 經濟部智慧財產局員工消費合作社印製 接著，請參照第五圖，一編程氡化層（codingoxide)16 利用一熱氧化法於氧環境中形成於NMOS記憶胞區域210 之上，上述之|_化..矽U 0在此步驟之中做爲一硬式罩幕。 該步驟之溫度大约是750至1100 "C，编程氧化層 (coding oxide)16之厚度約爲200至800埃，此厚度較閘楠 本紙張尺度適用中國國家標準（CNS ) A4规格（21〇X297公釐） 434§@$ ——————一 A7 ---------B7 五、發明説明（） 氡化層6厚。隨後利用熱磷酸將氮化矽層i 〇去除。接著， 一第魂晶欲形成於NMOS元件.區域200以及NMOS記 憶胞區域210之上當作字語線，如第六圖所示。 參閲第七圖，利用微影、蝕刻製程將上述之複晶矽 .層8、複晶矽層1 8、閘極氧化層6 及編程氧化層1 6蝕刻形 成閘極結構於上述之NMOS元件區域2〇〇以及NMOS記憶胞 區域210之上。化學氣梱沈積法形成氣化層於閘極結構之 上。使用上述之閘極結構做爲一罩冪，對NMOS元件區域 200以及NMOS 1己憶胞區域210進行—篇二次離子捲雜，以 較佳實施例而言，爲捧雜一 η型離子例如砷或磷以利於形 成η型LDD-及極區域20於閘極結構之附近。此步驟之劑量 較低，其植入劑量及離子植入能量分别爲1Ε12至 1R14 atoms/cm2、5至 100 KeV 〇 參閲第八圖，一氧化層沈積於閘極結構之上，利用非 等向性蝕刻形成侧胺22於閘極結構之側壁。下一步驟 爲形成汲極與源極區域24，因此執行第三次離年槔雜植入 離子於NMOS元件區域200以及NMOS記憶胞區域210中。 掺雜之離子爲η型可以爲磷或坤，離子植入之劑量約爲 m'6 經濟部智慧財產局員工消費合作社印製 一摊 5E14至5E16 atoms/cm2，且離子植入之能量大約爲0.5至 8 0 KeV。必須注意的是NMOS开‘咎^一域上表濃度高 於NMas記憶—她菡域21 〇，闺爲在篥一次離子i雜暗差入p 型離子於NM_OS記敗脱_區^_110。因此，NMOS元件區域200 與NMO S記憶胞區域2 1 0間具有不同之啓始電壓。 尺度逍用中國國家標準（CNS ) A4規格（210X297公楚）V. Description of the invention () Method for manufacturing a mask read-only memory on a semiconductor substrate. Counter doping due to high doses will be suppressed. The present invention will be explained using a preferred example as follows, but it is not intended to limit the spirit and the inventive entity of the present invention, but only to this embodiment. Those skilled in the art can be arbitrarily under the spirit of the present invention. Change its design. In a preferred embodiment, a single crystal silicon substrate 2 with <] 〇〇 > orientation is provided, and the substrate 2 is divided into two main parts, which are MM. &Amp; element- The area 200 and the NMOS memory cell area 210 are areas for programming data such as 1 or 0. Then, a thick field fluorination area (FOX) 4 is formed on a predetermined area by using a fluoridation method. Generally speaking, using a halide layer and a silicon nitride layer as a nitride mask substrate, by performing thermal oxidation in a vapor environment, a FOX region 4 having a thickness of about 3000 to 8 000 angstroms can be formed, as shown in the first figure. . After doing this, the above masks can be removed separately with hot phosphoric acid and HF. A gasification reactor 6 is oxidized in the oxygen environment and formed in the NMOS predecessor region 200 and the NMOS memory cell region 210 as gate oxidation. The temperature is about 800 to 1100 degrees C, and the chemical oxide vapor deposition method can also be used to form the above-mentioned oxide layer 6 at a temperature of 600 to 800 degrees C using teOS as a reactant. The process pressure is about 0.1 to 10 Thing. The thickness of the halide layer 6 in this embodiment is about 15 to 200 埤. After the above-mentioned oxide layer 6 is formed, a complex-crystalline crystal is deposited on the oxide layer 6 by a chemical gas deposition method. A thin nitrided hairpin i0 is then deposited on the polycrystalline silicon layer 8 described above. The silicon nitride layer 1 〇 can usually use low-pressure chemical vapor deposition method. This paper is suitable for National Standards (CNS) 8 4 Secret (21〇x297 公 ^ 厂 __; _ Please read the precautions of the back © before loading the page Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 43 Μ Α7 Β7 V. Description of Invention () (Low Pressure Chemical Vapor Deposition; LPCVD) (Plasma Enhance Chemical Vapor Deposition; PECVD), or other suitable methods. The thickness of the silicon nitride layer 10 is about 200 to 1500 angstroms. The process temperature is about 300 to 800. The reaction substance is usually SiH4, NH3, N2, N20 or SiH2Cl2, NH3, N2, N20. Referring to the third figure, a light J and belongs to the case 12 is formed on the JSIMOSL device area 200 and the NMOS memory cell area 2 1 0 is exposed. In the process etch, the vaporized silicon wafer 10 and the polycrystalline silicon layer 8 located on the NMOS memory cell region 23 are removed, and then the photoresist pattern 12 is removed. Referring to the fourth figure, a comprehensive type is then performed. Will ion Into the above NMOS device region 200 and NMOS memory cell region 210, a lightly doped drain (IJDD) region 1J is formed. This low-dose ion doping can increase the boron ion concentration on the surface for coding. It can be here In the embodiment, it is better to dope a small dose of ions, and the doped impurity may be BF2 or boron. The dose of the ion implantation is about 5E12 to _5E14 atoms / cm2, and the energy of this step is about 5 to 120 KeV. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, please refer to the fifth figure, a coding oxide layer 16 is formed on the NMOS memory cell region 210 in an oxygen environment using a thermal oxidation method, as described above | In this step, the silicon U 0 is used as a hard mask. The temperature of this step is about 750 to 1100 " C, and the thickness of the coding oxide 16 is about 200 to 800 angstroms. Thickness is larger than Zhannan. The paper size applies Chinese National Standard (CNS) A4 specification (21 × 297mm) 434§ @ $ —————— 一 A7 --------- B7 V. Description of the invention () The halide layer is 6 thick, and then the silicon nitride layer i 〇 is removed by using hot phosphoric acid. Next, a first crystal to be formed in the soul NMOS device. NMOS region 200 and the region 210 above the cells memorized words as word lines, as shown in FIG sixth. Referring to the seventh figure, the above-mentioned polycrystalline silicon is etched using a lithography and etching process. Layer 8, polycrystalline silicon layer 18, gate oxide layer 6 and programming oxide layer 16 are etched to form a gate structure on the above NMOS device. Region 200 and NMOS memory cell region 210. The chemical gas radon deposition method forms a gasification layer on the gate structure. Using the above gate structure as a mask power, perform a secondary ion doping on the NMOS element region 200 and the NMOS 1 memory cell region 210. In a preferred embodiment, for n-type ions, for example, Arsenic or phosphorus is advantageous for forming the n-type LDD- and the pole region 20 near the gate structure. The dose in this step is lower, and the implantation dose and ion implantation energy are 1E12 to 1R14 atoms / cm2, 5 to 100 KeV, respectively. Refer to the eighth figure, an oxide layer is deposited on the gate structure. Directional etching forms side amines 22 on the sidewalls of the gate structure. The next step is to form the drain and source regions 24, so the third doping implantation is performed in the NMOS device region 200 and the NMOS memory cell region 210. The doped ions are η-type, which can be phosphorus or kun. The dose of ion implantation is about m'6. The staff consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a booth of 5E14 to 5E16 atoms / cm2, and the energy of ion implantation is about 0.5 to 80 KeV. It must be noted that NMOS has a higher concentration on the surface than that of NMas memory—her 菡 domain is 21 °, and she is inferior to the p-type ions in the NM_OS and loses the __zone ^ _110. Therefore, the NMOS device region 200 and the NMO S memory cell region 210 have different starting voltages. Standards use Chinese National Standard (CNS) A4 specifications (210X297)
434SSI A7 B7 五、發明説明（） 在N2/〇2或N20之環境中進行一_^」!^戴见火程序，以 活化離子形成淺接面元件，此步驟之溫度大約是8〇〇至 1100°C，示之於第九圖。 因此’如第九圖中所示，本發明中之罩幕唯讀記憶 艘係形成於半導體底材2上，此一底材2上包含NMOS元件 區域200以及NMOS記憶胞區域210，罩幕唯讀記憶體可包 含：隔離结構4於NMOS元件區域200以及NMOS記憶胞區 域210之間；Μ極氧化層6於NMOS元件區域200上；編良 I、化―屋16於NMOS記憶胞區域210之上；主閛掻18分別形 成於NMOS元件區域200以及NMOS記憶胞區域210上；側 壁間隙22於主閘極1 8之侧壁上；源汲極區之第一摻雜區20 於侧壁間隙22下方之底材2内；源汲極區之第二摻雜區24 鄰近於第一摻雜區20之外側，第二摻雜區24之摻雜濃度較 第一摻雜區20為高；以及p型摻雜區14於碑，惫.彳匕換卞方 鄰近底材砉面處。 表一爲在不同編程製程下不同之啓始電壓之比較’編 程摻雜（coding implant)爲利用BF2以100 KeV穿遠250 經濟部智慧財產局員工消費合作社印製 埃之氧化層下執行。 表一 樣品 編程摻雜 編程氧化層 -- 啓始電壓（v) iatoms/cm2) fangstrom) 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） 3 4 4 η Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明説明（ A 無 無 0.69 B 1E14 無 2.81 C 1E14 300 7.41 _ D 無 300 1.84 E 5E14 無 3.95 _ F 5E13 300 6.16 __ 第十圖顯示本發明不同编程條件下，元件之電流-電 壓曲線。可以看出具有較低摻雜劑量與較厚之氧化層具有 較佳之特性。第九圖爲本發明中罩幕唯讀記憶體NMOS記 憶胞之電流-電壓曲線。本發明之優點爲（1)傳統製程知較 低崩潰電壓與高漏電流問題將被解決。（2)位元線之 counting doping問題也會被抑制。 本發明雖以一較佳實例闡明如上，然其並非用以限 本發明精神與發明實體，僅止於此一實施例爾。鉀 定 領域技藝者，在不脱離本發明之精神與範園内所伟、 ，均應包含在下述之申請專利範園内。 ％ 10 參紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）434SSI A7 B7 V. Description of the invention () In the environment of N2 / 〇2 or N20, perform a _ ^ "! ^ Dai see fire procedure to activate ions to form shallow junction elements, the temperature of this step is about 800 to 1100 ° C is shown in the ninth figure. Therefore, as shown in the ninth figure, the mask read-only memory boat of the present invention is formed on a semiconductor substrate 2. This substrate 2 includes an NMOS element region 200 and an NMOS memory cell region 210. The read memory may include: the isolation structure 4 between the NMOS device region 200 and the NMOS memory cell region 210; the M-pole oxide layer 6 on the NMOS device region 200; The main chirp 18 is formed on the NMOS element region 200 and the NMOS memory cell region 210, the sidewall gap 22 is on the sidewall of the main gate 18, and the first doped region 20 of the source-drain region is on the sidewall gap. 22 inside the substrate 2 below; the second doped region 24 of the source-drain region is adjacent to the outside of the first doped region 20, and the doping concentration of the second doped region 24 is higher than that of the first doped region 20; And the p-type doped region 14 is in the monument, exhausted. Change the square near the surface of the substrate. Table 1 shows the comparison of different starting voltages under different programming processes. The coding implant is implemented under the oxide layer printed by the consuming staff cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs with BF2 at 100 KeV through 250. Table 1 Sample programming doped programming oxide layer-starting voltage (v) iatoms / cm2) fangstrom) This paper size applies to Chinese national standards (CNS > A4 size (210X297 mm) 3 4 4 η Α7 Β7 Ministry of Economic Affairs wisdom Printed by the Consumer Cooperative of the Property Bureau V. Invention Description (A No No 0.69 B 1E14 No 2.81 C 1E14 300 7.41 _ D No 300 1.84 E 5E14 No 3.95 _ F 5E13 300 6.16 __ The tenth figure shows the different programming conditions of the present invention, The current-voltage curve of the device. It can be seen that the lower doping dose and the thicker oxide layer have better characteristics. The ninth figure is the current-voltage curve of the read-only memory NMOS memory cell in the present invention. The advantages of the invention are (1) the conventional process knows that the problems of lower breakdown voltage and high leakage current will be solved. (2) the counting doping problem of the bit line will also be suppressed. Although the present invention is explained above with a better example, then It is not intended to limit the spirit and the inventive entity of the present invention, but only to this embodiment. Those skilled in the art without departing from the spirit and scope of the present invention should all be included in the following In the patent application park. ％ 10 The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm)