TW434842B - Flash memory hot electron programming method that is suit for low drain voltage operation - Google Patents

Abstract

A new method for charging floating gate of flash memory is disclosed. The flash memory consists of source, drain, control gate, floating gate and substrate. Let the bias between source and drain smaller than 5 volts, the bias between floating gate and source larger than 2 volts, and the bias between substrate and source larger than 0.5 volt. Use the positive bias from the substrate to the source to inject large amount of holes into n-type channel and generate Auger re-combination. The Auger re-combination can raise the electron energy of n-channel and let electrons get enough energy to surmount the energy barrier of tunnel oxide and charge the floating gate.

Description

V. Explanation of the invention (1) The present invention relates to a method for charging a floating gate of a non-volatile memory, especially a floating gate capable of charging non-volatile memory to a non-volatile memory under low-voltage operation. How to charge. Non-volatile memory is a type of semiconductor memory that does not lose data when the power is turned off. It can be roughly classified into read-only memory (rea (i only memory, ROM), erasable and programmable read-only memory). (erasable programmable read only memory (EPROM)) and electronic erasable programmable read only memory (EEPR0M). EPROM and EEPROM both write signals electronically, eprom is irradiation Ultraviolet light erases data 'EEPR0M is electronically erasing data' and the conventional flash (Π ash) E EPROM is an electronic erasure of all or EE PROM data in one area at a time. For convenience of explanation, they are collectively referred to as EPROMs. Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a conventional EPROM. A general EPROM includes a substrate 10, and two sources with opposite electrical properties to the substrate 10 ( source region 12 and drain region 14, a floating gate electrode 18 and a control gate electrode 22. The substrate 10 of the EPROM channel is a p-shaped substrate. Region 12 and drain region 14 are two n-shaped doped regions. The voltages on substrate 10, source region 12, drain region 14, floating gate 18, and control gate 22 are expressed as Vb, Vs, Vd, Vi, and Vc. The voltage difference between the two electrodes is defined as the bias between the two electrodes. For example, Vds means the bias of the drain to Vs, which is Vd-Vs.

434842 V. Description of the Invention (2) ~ In terms of electrical properties, each EPROM has a threshold voltage (threshQld voltage, Vt). When the bias value Vcs of the control gate 22 to the source region 12 is greater than Vt, the source region 12 and the drain region 14 can be connected to each other. Whether the data stored in EpROM is logic 0 or logic 1 is determined by the mutual conduction between the source region 2 and the drain region 14. And v t will be affected by the amount of charge in the floating gate 丨 8 ’, so the amount of charge stored in the floating gate 18 is used to define logic 0 or logic 1. In EPROM, the charging process of sending a charged carrier into the floating gate 18 and trapping the charged carrier in the floating gate is called programming, and the charged carrier is moved out of the floating gate. The process of 18 is called erasing. In the conventional technique, the physical method used in the thermo-electron stylization method of the η-shaped channel EPROM can be roughly divided into two types. One is called channel hot electron injection (CHEI), and the other is called CHEI. Channel-initiated secondary electron injection (CISEI). Please refer to Figure 2A 'Figure 2A is a schematic diagram of the conventional CHE I. The purpose of channel hot electron injection is to heat the floating gate 18 The electrons in the lower channel 'so that some of the heated electrons have enough energy to cross the energy barrier formed by the difference between the conductive band of the first dielectric layer 16 and the substrate 10 Since the heated electrons have higher energy than the electrons under thermal equilibrium, they are called hot electrons. If the substrate 10 and the first dielectric layer 16 are made of silicon and silicon dioxide, respectively, then silicon / two The energy barrier formed by the interface of silicon oxide is about 3.2 electron volts (eV), that is, the energy of the hot electron in the n-channel must be connected

434842 V. Description of the invention (3) The first dielectric layer can be skipped to enter the floating idler μ near or greater than 3.2 eV, and the floating gate 18 is charged. If the influence of the electron scattering (sca 11 eri ng) in the η-shaped channel is ignored, the maximum energy that can be obtained by the electrons flowing from the source to the drain is approximately equal to q * (Vds), where q is an electron Battery. So 'ideally, the electrons in the channel will have enough opportunity to cross the first dielectric layer to the floating gate after V d s must be greater than 3 volts. However, in actual operation, 'Vds must be at least greater than 5 volts to provide sufficient energy for the electrons in the channel to cross the energy barrier of 3.2 electron volts. However, as the semiconductor process evolved, the size on the wafer continued to shrink, and the external power supply also decreased from 5 volts to 3.3 volts or even lower. In order to increase the accumulation of the EPROM array and reduce the difficulty of galvanic isolation of the drain region ', therefore, the voltage of the drain electrode is also expected to drop to about 3.3V during programming. The conventional CISEI ', as described in U.S. Patent No. 5,659,504, is a method of stylizing a low-voltage (Vd below 5 volts) n-channel EPROM. Please refer to FIG. 2B, which is a schematic diagram of the conventional CISEI. The biggest difference between CISEI and CHEI is that the Vds of CiSEI drops to about 3 volts. Vbs is less than zero; while the Vds of CHEI is about 5 volts and Vbs is equal to zero. In the CISEI's stylized method, the electron el from the source 12 cannot get enough energy in the channel to cross the energy barrier of S i / S i 02, but the bias voltage Vds without the source to the source is enough to make the electron ei has enough energy to generate impact ionization in the n-shaped channel near the drain region 14. Because the energy gap of Shi Xi is approximately 1,12 electron volts, as long as the electron el obtains energy exceeding i 12eV,

Page 6 4 3 4 8 4 2 V. Description of the invention (4) Electron-hole pair (e2 and h2) can be generated. The hole h2 is accelerated toward the substrate 10 by the electric field formed by Vbs. When sufficient energy is obtained in the hole h2, an electron hole pair, e3, and h3 are generated near the junction of the drain region 14 and the substrate 10. In the same electric field, the forces of the electrons and the holes are in opposite directions, so the electrons e3 accelerate toward the Si / Si02 interface. Once the energy of the electron e3 is close to or greater than 3.2 electricity! Ziaite's energy barrier ’has the opportunity to jump over the first dielectric layer 16 and fall into the floating gate 1 8 ′ to charge the floating gate. Because the secondary electrons produced by the impact ionization effect are caused by the electrons in the η-shaped channel, they are called channel-triggered secondary electron injection CISEI. It is suggested in the examples in US Patent No. 5,659,504 that Vs = 0, l.lvSVdS3_3v, and -3v SVbS-0.5v. The main object of the present invention is to provide another method for charging a floating gate of an n-channel channel memory with a low inverting voltage. Capable of charging EPROM floating gates with Vds below 5 volts. According to the above object, the present invention proposes a method for charging a floating gate of an n-channel channel memory. The memory includes a source, a drain, a control gate, a floating gate, and a substrate. The method of the present invention is called AUge.r_enhancecj channel hot electron injection (AECHEI). DAECHEI injects holes into the n-shaped channel near the source from the * Hai substrate, so that the holes and n The electrons generated in the open channel are combined with Ojie (recommbination) to increase the energy of the electrons in some conductive bands. After that, similar to chei, the high-energy electrons generated by the combination are then heated by the biased Vds of the set-to-source bias. When the energy of the electron is greater than a fixed energy barrier, the floating gate 'charges the floating gate. · "In the present invention, the source of the electrons entering the floating gate is that the energy biased by the drain to the source is two and the energy biased by the substrate to the source Vbs The minimum energy to cause the trap to enter the floating gate across the energy barrier is solid wood: He. Because the energy provided after recombination is increased, the energy required to accelerate is only used to reduce the bias voltage of the drain-shaped channel Vds to achieve the purpose of low voltage operation. ‘Μ original electrode ^ Invention ❺ The first embodiment provides various bias voltages for the η-shaped channel memory. In order to generate the Auger recombination, the substrate has a positive bias voltage to the source vbS in winter. The increase and increase in the pass increase is caused by the positive bias of the drain to the source = the electric voltage on the sub, by the closed circuit and the presence of electric motor: = to a degree greater than 4, the shape of the channel will be generated. Only heat is generated. The second embodiment of the present invention provides the structure of the η open channel 5 memory used in the execution of AECHEi. We use the bottom of the η channel to destroy _ heavy p-type doping The area is used to increase the amount of effective hole injection to enhance the recombination effect and increase the speed of stylization. * The third embodiment of the present invention provides a stylized floating open memory cell array. Partial memory The base of the element is connected to the first contact, and the base of some memory cells is connected to the second contact. The first contact and the second contact are electrically isolated from each other. Such a design can reduce programming.

Page 8 434842 V. Description of the invention (6) ^ Consumption of base current 'is used to increase the ambition of stylization In order to make the above item of the present invention a preferred embodiment is given below, the following: With the accompanying drawings, it can be more clearly understood. 'For a detailed description, the diagram is briefly explained: FIG. 1 is a schematic diagram of a conventional EPROM; FIG. 2A is a schematic diagram of a conventional CHEI; and FIG. 2B is Schematic diagram of the known CISEI;

Fig. 3 shows the principle diagram of AECHE I of the present invention. Fig. 4 is a schematic diagram of recombination of Oujie; Fig. 5 shows an experimental result diagram of the energy distribution of light emitted by a virtual memory cell when it is turned on; Fig. 6 FIG. 7 is a graph of gate current versus gate voltage of a virtual memory. FIG. 7 is a stylized characteristic diagram of AECHEI of the present invention and conventional CHEI on an EPROM. FIG. 8 is a graph of EPROM used by the AECHEI of the present invention Structure diagram

FIG. 9A and FIG. 9B are structural diagrams of the EMOM used by the two AECHEIs of the present invention; FIG. 10A shows a schematic diagram of the floating gate memory cell array of the present invention; and FIG. 10B is the IOA diagram An embodiment of a chip of a memory cell array; and FIG. 11 is a schematic diagram of a gated n-channel element. Symbol Description':

Page 9 3 4 β-:: 2 V. Description of the invention (7) 30 ~ substrate; 3 2 ~ source; 3 4 ~ drain; 36 ~ first dielectric layer; 3 8 ~ floating gate; 40 ~ Second dielectric layer; 4 2 ~ control gate; 44 ~ heavy doped region; 4 5 ~ bit line; 4 6 ~ word line; 4 8 ~ source line; 50 a ~ first connection Point; 50b ~ second contact; 6 1 ~ gate oxide layer; 6 2 ~ select gate. Example: Please refer to Fig. 3, which shows a schematic diagram of the principle of AECHEI of the present invention. The invention provides a method for charging a floating gate of an n-shaped channel memory (also called EPROM). As shown in FIG. 3, an EPROM 0M includes a source electrode 3 2, a drain_pole 3 4, a control gate electrode 4, a floating gate electrode 38, and a base 30. There is a first dielectric layer 36 between the floating gate 38 and the substrate 30. The first dielectric layer 36 is generally made of an oxide, so it is also called a penetrating oxide layer (1: U η n e 1 i n g o x i d e 1 a y e r). There is a second interface between the control gate 4 2 and the floating gate 3 8

Page 10 43 卯 3 ′ Ⅴ. Description of the invention (8) The electric layer 40 ′ serves as the electrical isolation between the control gate 42 and the floating gate 38. The AECHE I of the present invention includes the following steps: a first connection line is used to provide a first voltage (hereinafter referred to as Vd) to the drain 34 so that the bias voltage Vds between the drain 34 and the source 32 is less than 5 volts. A second connection line is used to provide a second voltage (hereinafter referred to as Vc) and the control gate 42 so that the bias voltage Vf s between the floating gate 38 and the source 32 is greater than 2 volts; and a third connection The line provides a third voltage (hereinafter referred to as Vb) and the base 30 so that the bias voltage Vbs between the substrate 30 and the source 32 is greater than 0.5 volts. Vf s enables an n-shaped channel to be formed on the surface of the substrate 30 under the first dielectric layer. Because 8 is greater than zero, there will be a hole h flowing from the substrate 30 to the source 32 and the n-shaped channel near the source 32, so the recombination occurs. The Auger recombination provides some energy, e, from the source 32 to the drain 34. After the electron e is accelerated by the electric field of Vds, it has a chance to get enough energy to cross the barrier formed by the first dielectric layer 36 and the substrate 30 and enter the floating gate 38 to charge the floating gate 38. As shown in Figure 4, Figure 4 is a schematic diagram of Ou Jie's recombination. To put it simply, ‘Auger recombination is the opposite process of impact ionization. Since vbs is greater than zero, the hole h in the substrate 30 diffuses into the n-shaped channel. After the hole h reaches the n-shaped channel, there is a great chance that it will merge with the electron e in the η-shaped channel and then merge and disappear. 'The energy (at least one band gap) will be provided to the remaining one) Electrons. In other words, the recombination of Ou Jie will cause some electrons to have higher energy when they initially move in the η-shaped channel, so as long as yds provides a lower energy to the electron e in the channel, there will be The opportunity allows the electron e to obtain enough energy to cross the energy barrier formed by the first dielectric layer 36 and the substrate 30.

Page 11 43i4gi4i V. Description of the invention (9) '' 'Please refer to Figure 5, which shows the experimental results of the energy distribution of light emitted by a virtual memory cell when it is turned on. The so-called virtual memory cell (dufflmy = U) is an EpROM that controls the short circuit between the gate and the floating gate. It is often used to measure the electrical properties on the floating gate. The ordinate of Figure 5 is the light intensity divided by the current, which is the light intensity after the normal K (n0rma). The abscissa is the light energy. The other meaning of the ordinate of Figure 5 is that the number of electrons is one The other meaning of k-block 是 is the energy carried by the electron. From Figure 5 = the line shows that when the substrate-source bias VbS gradually increases, the higher: the number of sub-substances gradually increases. That is to say, there are more electrons that can have enough energy poles. Among them, it is more noticeable that in the two lines of 16 and 1.5 volts earlier, the electron energy is equal to two, and the vicinity of the two special is equal. There is a hump, and the U electron volt is 1 < 5 times with a wonderful band gap (.12 electron volts). It is known from the components that the electrons of the conductive bands are most likely to obtain the energy of the gap of g 1 when recombination, which is a value of 疋 electron volts composed of silicon. In other words, the 5th Tu Shi Tu & k caused by Xue Erji, also provides a proof that Ou Jie recombined to supply energy to the electrons in the n-shaped channel. Xiaotong is under control. 〇 Refer to Figure 6, Figure β is a virtual closed-pole voltage. Here, define a virtual record ㈡ = inter-pole current pair e ^ ^, 〇tvds = 3: 5 Λ ^ 1 fi] " ^ the gate voltage gradually increases from zero, flowing into the gate Vbs = 0, then; The maximum value of the current will appear at the idle pole and will increase. idle

Ms, then gradually decrease with the increase of the gate voltage ==

434i4g V. Description of the invention (10) The commonly known gold-oxygen main raises the thermoelectric generation of the transistor when the voltage is 5 volts. When Vb decreases to the electric field, and then ^ is the body effect (b〇dy effect), the current decreases after the horizontal is greater than 0. 5 volts. However, when the base voltage is applied, the current flow at the gate voltage greater than Θ is greater than 3 When the part above 5 volts is at ^, especially at 2 volts, the interpolar current is even higher when Vb is greater than 0.5 volts, which is quite considerable. In other words, when it comes to Syria! Didan, #, ‘Jie recombination can make the electrons of the η-shaped channel sufficient. The dog enters the gate here to generate current. But Vbs can't be too big. In fact, the Pn junction between the substrate greater than 2 volts and the source will generate a large amount of current because of a κ β, which will reduce the efficiency of stylization. Therefore, the recommended value of Vbs is between 05 and 2 and the gate of Volcano u / 丨 between ϋ5 and ^ Hot. —The sub-European recombination has about the energy of 16 electron volts for one electron, eh. The required VdS may be more than 16 electron volts less than the Vds required by CHEI, and vds is preferably greater than 3 volts and less than 5 volts. As shown in Figure 6, the bias voltage VfS of the source between the floats must be greater than 2 volts for the gate current to occur. The voltage of the control gate depends on the coupling ratio of the control gate to the floating gate. The general coupling coefficient is about 50%, which means that the voltage of the control gate must be greater than 5 volts. The values of each bias are adjusted as shown in Table 1. Table 1

Vds Vbs Vfs Vcs Green value (Volts) 3-5 0.5-2 One-— 5-

43414 i V. Description of the Invention (11) Please refer to FIG. 7, which is a programmatic characteristic diagram of the AECEI of the present invention and the conventional CHEI on an EPROM. As can be seen in Figure 7, when the EPROM is programmed with the conventional CHEI at Vds = 3.5 volts, the threshold voltage is no matter whether the gate voltage is 12 volts or 15 volts. It only rises slowly after ten leap seconds (ms). The programming time of EPROM for general business is milliseconds or less. Therefore, as shown in Figure 7, when EPROM is programmed with C HE ί and Vds ~ 3.5, it is not commercially feasible at all. of. When an EPROM is programmed with the AECHEI of the present invention, when Vb = 2 volts, Vc = 12 or 15 volts, after one millisecond, the threshold voltage of the EPROM quickly rises to a saturation potential. That is to say, the AECHEI of the present invention can program an EPR 0 M under a condition of low voltage of Vds = 3.5 volts within a reasonable time. In addition, the AECHE I of the present invention can raise the threshold voltage of EPROM to more than 8 volts, as shown in FIG. 7 'to make logic 1 and logic 0 have a larger noise margin. In order to reduce the source The electronic current part of the current when conducting with the substrate, the present invention provides the structure of the n-channel memory used in the execution of AECHE I. Please refer to FIG. 8 'FIG. 8 is a structural diagram of an EPROM used in the AECHE I of the present invention. The EPROM for AECHEI of the present invention is a gate stacked n-shaped channel element, which includes a substrate 30, a source region 32, a drain region 34, a first dielectric layer 36, a floating gate 38, a first Two dielectric layers 38 and a control gate 42. As shown in FIG. 8 'the substrate 30 may be a p-shaped substrate (P substrate), the source region 32 and the drain region 34 are two n-type impurity regions, and the first dielectric layer 36 is usually about 100 angstroms thick. Silicon oxide layer, floating gate

Page 14 434i4g 5. Description of the invention (12) 38 is provided on the first dielectric layer 36, which can be formed by throwing polycrystalline silicon, the second dielectric layer 40 is provided on the floating gate 38, and the control gate 42 is provided on the second dielectric Electrical layer 40. The source region 32 may be a double diffused drain (double di f fusion d r a i η, D D D) structure. The formation of the source region 32 includes two steps. First, the surface of the source region 32 is ion-implanted with phosphorus (P) and arsenic (As), and then heat-treated. Because the diffusion rate of phosphorus is faster than that of arsenic, the impurities in the tank will form a lighter n-type impurity region 32b, and the broken dopants will form a deeper n-type impurity region 3 2 a. Figure 8 shows. The source region 3 2 of the DDD structure can reduce the proportion of the electronic current when the pn junction is turned on, and reduce the waste of unnecessary snow current. Please refer to FIG. 9A and FIG. 9B. FIG. 9A and FIG. 9B are structural diagrams of EPROMs used by the two AECHEIs of the present invention. In order to increase the probability of Oujie recombination, a heavily doped region 44 can be set under the electron flow from source 32 to drain 34, and the base current ratio is from i to 30; ^ 30 to the hole current ratio of source 32 As shown in the figure. Moreover, the injection place is where the electrons in the channel are just beginning to move from source 32 to drain 34. The probability of channel O generating recombination can be increased to generate more hot electrons and increase the speed of programming. . For the same reason, the structure of the g-th graph and the 9 / th graph can also be merged, so the 9th graph is generated. The source region 32 of FIG. 9B is a DDD,..., And D structure. Moreover, a heavy p-type doped region M in the substrate is provided below the n-shaped channel. -On the one hand, the DDD structure can reduce the proportion of electricity and sub-current when Vbs is positively biased. On the other hand, the heavy p-doped region 44 can increase the hole injection into the n-shaped channel, and increase the recombination of the channel in the channel. effect. In order to avoid generating a large amount of current when Vbs is a positive voltage, the present invention provides another

Page 15 434841 V. Description of the invention (13) A floating gate memory cell array is provided for AECHE I, as shown in Fig. 1A. The memory array contains at least two memory cells, which is the EPROM described previously. Each memory cell includes a substrate 30, a source region 32, an electrodeless region 34, a first dielectric layer 36, a floating gate 38, a second dielectric layer 40, and a control gate 42. . A plurality of control gates 42 of EPROM are connected together to form a word line, that is, a first connection line, as shown by 46a and 46b in FIG. 10A. The drain electrodes 34 of the plurality of EPROMs are connected together to form a bit line 45a to 45d, that is, a second connection line. The source electrodes 32 of the plurality of EPROMs are connected together to form a source line 48a and 48b. The substrate 30 of at least one EPROM is connected to a first contact 50a 'and the substrate 30 of at least one EPROM is connected to a second contact 50b', and the first contact 50a and the second contact 50b are electrically isolated from each other. The memory cell array in Fig. 10A can reduce unnecessary current consumption when performing AECHE I. For example, 'If you want to charge the floating gate of EPROM M1 with AECHEI, the word line 46a is 12 volts, the source line 48a is grounded, the bit line 4 5 a is 3.5 volts, and the first connection The point 50a is given 2 volts. From Figure 10A, it can be found that 'the substrate has positively biased epr0m from the source, only M1 and M2'. If source line 48a and source line 48b are electrically isolated from each other, M3 and M4 will not There is a problem with the current flowing from the substrate to the source. For the EPR0M (M5 ~ M8) in the right half, because the first contact 50b and the second contact 50b are electrically isolated from each other, the voltage on the first contact 50a will not be transmitted to the second contact at all. 50b 'Natural EPROMs of M5 to M8 will not have the problem of Vbs being positively biased. Please refer to FIG. 10B 'FIG. 10B is an embodiment of a chip of the memory cell array in FIG. 10A. The memory cell barrier of the present invention is characterized by some

Page 16 434842 V. Description of the invention (14) The EPROM substrate is separate from some EPROM substrates. In order to achieve the above characteristics, the present invention proposes a triple well structure, as shown in FIG. 10B. Each EPROM is set in a p-shaped well, that is to say, the base of each EPROM is a p-shaped well = for example, M1 to M4 in Figure 10A are set in a first p-shaped well, so the first The p-shaped well is the first contact 50a, and M5 to M8 in Fig. 10A are provided in a second p-shaped well: so the second p-shaped well is the second contact 50b. There is one between the first contact 50a and the first contact 50b; Zhu η-shaped well (dee ρ η-we 1 i > D n W) is used for electrical isolation, as shown in Figure 1 OB Show. The AECHEI of the present invention can also be applied to a gate-type n-channel element, as shown in FIG. 11. Figure 11 is a schematic diagram of an open SnB channel element. In addition to all the base, source, drain, floating gate, and control gates of a general stacked n-channel element, the opening n-channel element includes a gate oxide layer 61 and a select gate. The oxide layer 61 is provided on the surface of the substrate 30 between the square floating gate 38 and the source region 32, and the selection electrode ⑴f is on the gate oxide layer 62, as shown in Fig. 11. Selecting the gate electrode ⑸ can control the threat = source The amount of current flowing from the pole 32 to the pole 34 is the number of electrons controlled in the n-shaped channel. The hole injection generated by Vbs determines the number of recombination of the europium.

The number of combinations is 38 w β _ plus ^ 彳 ^ denga to the floating gate. Compared with the conventional method of n-shaped channel, the efficiency of Wang Jin Electronics can be increased. The charging method of the present invention has the force and force: two, the voltage Vbs of the extreme charge on the substrate, and the electrical holes of the substrate. ^ ;, ^ · 5 volts forward bias A into the source. Some holes will

V. Description of the invention (15) ^ ________ Meeting> Mainly enter the n-shaped channel and virtual amp & The energy of the electrons in the & -shaped channel, the electrons in \ are generated and recombined to increase the n pole between 3 ~ 5 Volt Circumference can therefore reduce the electric power on the poles to charge the battery. 'It is still possible to enter the floating gate of the η-shaped channel. Although the present invention is better, the present invention can be determined by anyone. Anyone familiar with this ^ embodiment is disclosed above.' However, it is not intended to be within the scope and scope. , Attached without departing from the spirit of the present invention; =; the protection of the present invention

Claims (1)

434 ^ 42 6. Scope of patent application '" a ~' — ^ "A kind of heat suitable for low-drain voltage operation in EPROM components; this component includes a source, a drain, a protection, a process, a floating open And the substrate, the method includes: a phase bias, a first voltage biased to the pole so that the bias voltage between the pole and the source gate is less than 5 volts; ~ < Two voltages to the control gate so that the bias between the floating gate and the fish poles is greater than 2 volts; and ... rain, providing a third voltage to the base to bias the substrate and the source Greater than 0.5 volts, in which the floating gate charges the source to the drain of the electron current generated., L is from ^ 2. The method according to item 1 of the scope of patent application, wherein the third Voltage :, the bias voltage between the substrate and the source is between 0.5 volts and 2 volts. J, 3. The method according to item 1 of the patent application range, wherein the first voltage is The bias voltage between the drain and the source is between 3 volts and 5 volts. 4. If the method of the first scope of the patent application, the The second voltage is such that the bias voltage between the floating gate and the source is between 2 volts and 7 volts. 5. For the method of claim 1 in the patent application range, wherein the second voltage is The bias voltage between the control gate and the source is greater than 5 volts. 6.-An n-shaped channel element formed on a substrate including: a source region and a drain region formed on the surface of the substrate. A first dielectric layer formed on the substrate; a floating gate formed on the first dielectric layer, and a portion of the floating gate 434S42 VI. Patent application range The moving gate overlaps the drain region; a second dielectric layer is formed on the floating gate; a control gate is formed on the second dielectric layer; a first connection line 'Connected to the drain region, so that the bias voltage between the drain and the source is less than 5 volts; a second connection line' is connected to the control gate, so that the floating gate and the source The bias voltage between the substrate and the source is greater than 0.5 volts; and a third connecting line is connected to the substrate to make the bias voltage between the substrate and the source greater than 0.5 volts; It is generated by the electron current from the source to the ί and 0 poles. '7. As for item 6 in the scope of patent application, the n-shaped channel element is a gate stacked n-channel device (stac [ed gate n-channei device) 〇 8. As in item 6 of the scope of patent application The n-shaped channel element further includes:-a gate oxide layer provided on the surface of the substrate between the floating gate and the source region; and-a selected gate electrode provided on the gate oxide layer for controlling The current from the source to the drain. &.) 9. According to item 6 of the scope of patent application, the source region is a double diffusion (DDD) structure. 10. As described in item 6 of the patent application, the n-channel element further includes a heavy P-shaped doped region, which is provided between the source and the drain. Page 20 434S4 2 6. Scope of patent application Below the sub-flow, it is used to increase the ratio of the hole current when the substrate is turned on to the source. 11 · A floating gate memory cell array comprising: at least two memory cells, each memory cell including a source region and a drain region provided on a substrate surface, a first dielectric layer formed on the substrate A 'floating gate' is formed on the first dielectric layer, a second dielectric * layer is formed on the floating gate, a control gate is formed on the second dielectric layer ', a first connection A line connected to the drain region to make the bias voltage between the drain and the source less than 5 volts, and a second connection line connected to the Control the gate, so that the bias between the floating gate and the source is greater than 2 volts, and a third connection line connected to the substrate to make the bias between the substrate and the source greater than 0 5 volts; where 'the current that charges the floating gate is generated by the flow of electrons from the source to the drain; The base of at least one memory cell is connected to a first contact, at least. The base of the memory cell is connected to a second contact, and the first contact and the second "point are electrically isolated from each other.丨 One 1 2. As in item i 丨 of the scope of patent application: the base of each memory 系 is a P-shaped well, and the p-shaped well connected to the first contact is: The P-shaped well connected to the second junction of Rong uses a deep η-shaped well as the electrical insulation of each other. Page 21