Γ·4 3 2 b A7 B7 五、發明説明（1 ) 本發明係有關於一種穩壓裝置，且特別是有關於一種 參考電壓產生裝置’其可在不增加Ml化^厚度且不影響 裝置可靠度的情況下產生穩定之參考電壓。 請參考第1A圖’此為習知參考電壓產生裝置之等效 電路圖。如圖中所示，電阻R1、R2、R3及NMOS電晶 趙ΤΙ 、T2係依序串聯並以電阻ri的一端連接正電源 EVCC ’電阻R2、R3之接點為輸出參考電壓VR2。NMOS 電晶體T1的閘極連接至電阻ri、r2之接點，nm〇S電 晶體T2的閘極係連接正電源evcc，而NMOS電晶體T2 的源極則連接負電源Vw另外，PMOS電晶體T3的閘極 連接NMOS電晶體τΐ之汲極、PMOS電晶體T3的源極連 接電阻Rl、R2之接點、而pm〇S電晶體T3的汲極則連 接負電源Vss 〇 接著，簡單說明此電路之操作如下。 經濟部中央標準局貝工消費合作社印聚 (請先閲讀背面之注意事項再填寫本頁) 假設外接電源(如第1A圖中EVCC)為3.3V，電阻R1、 R2、R3 為 300K、200K、500K 歐姆，NMOS 電晶體 ΤΙ、T2 之寬長比（W/L)為 1.6/67.5、1.6/60，且 PMOS 電 晶體T3之寬長比（W/L)為48/1，當外加電源EVCC慢慢增 加時，NMOS電晶體ΤΙ、T2首先會導通使電流Ip通過電 阻R2、R3並在PMOS電晶體T3之源極、閘極間產生一 壓降Vsg β若EVCC甚小時，由於此壓降VSG係小於PMOS 電晶逋的臨界電壓VTP(圖中未示），不足以使PMOS電晶體 T3導通，因此PMOS電晶體T3中並不會產生任何電流。 不過，一旦外接電源EVCC升高’此時由於電阻R2、R3 本紙張尺度適用中國囷家榡準（CNS ) A4规格（2丨0X297公釐） 經濟部中央標隼局員Η消費合作社印繁 臞4 32 6 8 2____五'發明説明（2) 通過之電流Ip亦會隨之增加，因此，PMOS電晶體T3之 源極、閘極間壓降VSG亦會隨之增加，使PMOS電晶體T3 在源極、閘極間壓降VSG超過臨界電壓VTP後導通。在這 種情況下，PMOS電晶體T3相當於一個低阻抗，可使大 部分通過電阻R2、R3的電流Ip轉向PMOS電晶體T3， 因此流經電阻R2、R3之電流Ip便可重新降低並使PMOS 電晶體T3之源極、閘極間壓降VSG控制於一範圍内，而達 到穩壓之作用。 請參考第1B圖，此為第1A圖參考電壓產生裝置之實 施電路圖。其中，電阻Rl、R2、R3係由很多個大小相 同之小電阻r串聯而成，並以不同數量組合調整其比例。 在此例中，電阻R1係由5個小電阻r串聯而成、電阻R2 係由2個小電阻r串聯而成、至於電阻R3則由3個小電阻 r串聯而成。又，NMOS電晶體ΤΙ、T2分別由數個不同 寬長比（W/L)之電晶體組成，如，NMOS電晶體Τ1係由一 個寬長比1.6/7.5及四個寬長比1.6/15之NMOS電晶體 (tl〜t5)串聯而成；NMOS電晶體Τ2則由三個寬長比1.6/20 之NMOS電晶體（t6〜t8)串聯而成。而電阻Rl、R2、R3 的比例則可以調整以控制或精調輸出參考電壓VR2之位 準，如設定於1.4V。 不過，在這個電路中，由於NMOS電晶體T2之閘極 係直接連至外接電源EVCC，也就是說，外接電源EVCC改 變會直接影響到NMOS電晶體T2閘氧化層所承受之壓 力，因此，習知技術中便增加NMOS電晶體T2之閘氧化 (請先閱讀背面之注意事項再填寫本頁) -" 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公嫠} 經濟部中央標準局員工消费合作社印來 1 ^43268 2 A7 B7 五、發明説明（3) 層厚度以抵抗外接電源EVCC增加而產生之額外壓力。不 過，這種方法卻會增加電路設計之難度及提高製程之複雜 度。 有鑑於此，本發明的主要目的便是在提供一種參考電 壓產生裝置，其可在閘氧化層厚度不變及可靠度不受影響 的情形下，使輸出參考電壓在外接電源增加時維持不變。 本發明之參考電壓產生裝置主要係串聯兩個（第一、第 二）電阻、兩個（第一、第二)NMOS電晶體並搭配一個回授 用之PMOS電晶體所形成。其中，第一電阻提供一分壓給 第二NMOS電晶體之閘極，藉以減低其承受之壓力。第二 電阻之壓降橫跨於PMOS電晶體之源極、閘極間，使PMOS 電晶體在NMOS電晶體通過電流過大時導通，藉以控制 NMOS電晶體通過電流於穩定之範圍内。另外，第二電阻 亦可予以調整，使其中間抽頭之輸出參考電壓位於設定範 圍内" 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式說明 第1A圖係習知參考電壓產生裝置之等效電路圖； 第1B圖係第1A圖參考電壓產生裝置之實施電路圖； 第2A圖係本發明參考電壓產生裝置之等效電路圖； 第2B圖係第2A圖參考電壓產生裝置之實施電路圖； 以及 (諳先閱讀背面之注意事項再填寫本頁) 訂 線. 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公嫠） i 驪4 326 8 2 A7 經濟部中央標率局負工消f合作社印製 B7 五、發明説明（4 ) 第3圖係本發明參考電壓產生裝置中外接電源與輸出 電壓之關係。 實施例 請參考第2A圖，此為本發明參考電壓產生裝置之等 效電路圖，其中，與習知技術（第1A圖）對應之元件係使用 相同之標號以利說明。 — 類似於第1A圖電路，此電路肀電阻Rla、Rlb、R2、 R3及NMOS電晶體ΤΙ、T2係依序串聯並以電阻Rla的一 端連接正電源EVCC。NMOS電晶體T1的閘極連接至電阻 Rlb、R2之接點，而NMOS電晶體T2的源極則連接負電 源Vss。另外，PMOS電晶體T3的閘極連接NMOS電晶體 T1之汲極、PMOS電晶體T3的源極連接電阻Rlb、R2之 接點、而PMOS電晶體T3的汲極則連接負電源Vss。 不同地是，NMOS電晶體T1的閘極此時並不直接連 接正電源EVCC，而是連接電阻Rla、Rlb之接點。此舉主 要目的是讓NMOS電晶體之閘極電壓下降（僅為正電源 EVCC之部分分壓），藉以使閘極所受壓力得以疏解。是以， 此電路在外接電源EVCC升高時便可以維持固定之輸出電 壓及穩定之輸出特性。 請參考第2Β圖，此為第2Α圖參考電壓產生裝置之實 施電路圖。其中，電阻Rla、Rlb、R2、R3係由很多個 大小相同之小電阻]:串聯而成，並以不同數量之組合調整 其比例。在此例中，電阻Rla係由3個小電阻r串聯而成、 電阻Rlb係由2個小電阻r串聯而成、電阻R2係由2個小 JI I *~~f 1 "訂 I , ^ (諳先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公嫠） P4 3268 2 A7 B7 經濟部中央標準局負工消费合作社印架 五、發明説明（5) 電阻r串聯而成、至於電阻R3則由3個小電阻r串聯而成。 又，NMOS電晶體ΤΙ、T2則分別由數個不同寬長比（W/I^ 之電晶體組成》在此例中，NMOS電晶體ΤΙ係由一個寬 長比1.6/7.5及四個寬長比1.6/15之NMOS電晶體（tl〜t5) 串聯而成。而NMOS電晶體T2則由三個寬長比1.6/20之 NMOS電晶體串聯而成（t6〜t8)。且，電阻R2、R3的比例 可以調整以控制或精調輸出電壓VR2之位準於預定之範 圍，如1.4V。而電阻Rla、Rlb的比例則可調整以控制 NMOS電晶體T2閘極所承受之壓力大小。 第3圖即為本發明參考電壓產生裝置在外接電源EVcc 時，電阻 Rl、R2、R3 為 300K、200K、500K 歐姆， NMOS電晶體ΤΙ 、T2之寬長比（W/L)為1.6/67.5 、 1.6/60，且PMOS電晶體T3之寬長比（W/L)為48/1時輸出 電塵之實驗結果。由圖中可知，本發明裝置在外接電源 1_5〜7_5V間均能穩定維持輸出電壓於1.4V上下。 综上所述，本發明參考電壓輸出裝置可在不改變閘氧 化層厚度、不增加設計及製程難度的情況下維持可靠之穩 塵輸出。且，電阻Rla、及電阻R2、R3可由兩個電 阻完成’或，分別由串聯之小電阻形成，因此在實施上十 分具彈性。 雖然本發明已以一較佳實施例揭露如下，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可做些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 1 U ^^ (讀先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中_家榡率（CNS) Α4· (21GX297公羡）Γ · 4 3 2 b A7 B7 V. Description of the invention (1) The present invention relates to a voltage stabilizing device, and in particular to a reference voltage generating device 'which can be used without increasing the thickness of the device and without affecting the reliability of the device. In the case of temperature, a stable reference voltage is generated. Please refer to FIG. 1A. This is an equivalent circuit diagram of a conventional reference voltage generating device. As shown in the figure, the resistors R1, R2, R3 and the NMOS transistors Zhao T1 and T2 are connected in series in series and one end of the resistor ri is connected to the positive power supply EVCC ', and the contact point of the resistors R2 and R3 is the output reference voltage VR2. The gate of the NMOS transistor T1 is connected to the contacts of the resistors ri and r2. The gate of the nmMOS transistor T2 is connected to the positive power source evcc, while the source of the NMOS transistor T2 is connected to the negative power source Vw. In addition, the PMOS transistor The gate of T3 is connected to the drain of the NMOS transistor τ 、, the source of the PMOS transistor T3 is connected to the contacts of the resistors R1 and R2, and the drain of the pMOS transistor T3 is connected to the negative power source Vss. The operation of the circuit is as follows. Printed by the Central Standards Bureau of the Ministry of Economic Affairs of the Bayer Consumer Cooperative (please read the precautions on the back before filling out this page) Assume that the external power supply (such as EVCC in Figure 1A) is 3.3V, and the resistors R1, R2, R3 are 300K, 200K, 500K ohms, the width-to-length ratio (W / L) of the NMOS transistors Ti and T2 is 1.6 / 67.5, 1.6 / 60, and the width-to-length ratio (W / L) of the PMOS transistor T3 is 48/1, when the external power supply EVCC When slowly increasing, the NMOS transistors T1 and T2 will first turn on so that the current Ip passes through the resistors R2 and R3 and a voltage drop Vsg β is generated between the source and gate of the PMOS transistor T3. If the EVCC is very small, due to this voltage drop VSG is less than the threshold voltage VTP (not shown) of the PMOS transistor, which is not enough to turn on the PMOS transistor T3. Therefore, no current is generated in the PMOS transistor T3. However, once the external power supply EVCC rises, at this time, because of the resistance R2 and R3, the paper size is applicable to the Chinese Standard for Household Standards (CNS) A4 (2 丨 0X297 mm), a member of the Central Standards Bureau of the Ministry of Economic Affairs, and a consumer cooperative. 32 6 8 2 ____ Five's description of the invention (2) The passing current Ip will also increase. Therefore, the voltage drop VSG between the source and the gate of the PMOS transistor T3 will also increase, so that the PMOS transistor T3 will The source-gate voltage drop VSG is turned on after exceeding the threshold voltage VTP. In this case, the PMOS transistor T3 is equivalent to a low impedance, and most of the current Ip through the resistors R2 and R3 can be diverted to the PMOS transistor T3. Therefore, the current Ip flowing through the resistors R2 and R3 can be reduced again and the The voltage drop VSG between the source and the gate of the PMOS transistor T3 is controlled within a range to achieve the function of voltage stabilization. Please refer to Fig. 1B, which is an implementation circuit diagram of the reference voltage generating device in Fig. 1A. Among them, the resistors R1, R2, and R3 are formed by connecting a plurality of small resistors r of the same size in series, and the proportions of which are adjusted in different combinations. In this example, the resistor R1 is composed of 5 small resistors r connected in series, the resistor R2 is composed of 2 small resistors r connected in series, and the resistor R3 is composed of 3 small resistors r connected in series. In addition, the NMOS transistors Ti and T2 are respectively composed of several transistors with different aspect ratios (W / L). For example, the NMOS transistor T1 is composed of one aspect ratio 1.6 / 7.5 and four aspect ratios 1.6 / 15. The NMOS transistor (tl ~ t5) is connected in series; the NMOS transistor T2 is formed by three NMOS transistors (t6 ~ t8) with a width / length ratio of 1.6 / 20. The ratio of resistors R1, R2, and R3 can be adjusted to control or fine-tune the output reference voltage VR2, such as 1.4V. However, in this circuit, because the gate of the NMOS transistor T2 is directly connected to the external power source EVCC, that is, the change of the external power source EVCC will directly affect the pressure on the oxide layer of the NMOS transistor T2. Therefore, Xi In the known technology, the gate oxidation of NMOS transistor T2 is increased (please read the precautions on the back before filling this page)-" This paper size is applicable to China National Standard (CNS) Α4 specification (210X297) 嫠 Central Bureau of Standards, Ministry of Economic Affairs Printed by the employee consumer cooperative 1 ^ 43268 2 A7 B7 V. Description of the invention (3) Layer thickness to resist the extra pressure caused by the increase of external power EVCC. However, this method will increase the difficulty of circuit design and increase the complexity of the process In view of this, the main object of the present invention is to provide a reference voltage generating device which can keep the output reference voltage unchanged when the external power source is increased under the condition that the thickness of the gate oxide layer is not changed and the reliability is not affected. The reference voltage generating device of the present invention is mainly composed of two (first, second) resistors and two (first, second) NMOS transistors connected in series. It is formed by a feedback PMOS transistor. Among them, the first resistor provides a divided voltage to the gate of the second NMOS transistor to reduce the pressure it bears. The voltage drop of the second resistor is across the PMOS transistor. Between the source and the gate, the PMOS transistor is turned on when the NMOS transistor passes a large current, so as to control the NMOS transistor to pass the current within a stable range. In addition, the second resistor can be adjusted to make the output of the middle tap The reference voltage is within a set range " In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Figure Figure 1A is an equivalent circuit diagram of a conventional reference voltage generating device; Figure 1B is an implementation circuit diagram of the reference voltage generating device of Figure 1A; Figure 2A is an equivalent circuit diagram of the reference voltage generating device of the present invention; Figure 2B It is the implementation circuit diagram of the reference voltage generating device in Figure 2A; and (谙 Please read the precautions on the back before filling this page). Alignment. This paper size applies to the Chinese National Standard (CNS ) A4 specification (2 丨 0X297) 嫠 骊 4 326 8 2 A7 Printed by B7 of the Central Bureau of Standards of the Ministry of Economic Affairs and Cooperative Fifth, the description of the invention (4) Figure 3 is the external connection of the reference voltage generating device of the present invention The relationship between the power supply and the output voltage. For an example, please refer to FIG. 2A, which is an equivalent circuit diagram of the reference voltage generating device of the present invention. The components corresponding to the conventional technology (FIG. 1A) use the same reference numerals to facilitate the description. — Similar to the circuit in Figure 1A, this circuit: resistors Rla, Rlb, R2, R3, and NMOS transistors TI, T2 are connected in series in series and one end of resistor Rla is connected to the positive power EVCC. The gate of the NMOS transistor T1 is connected to the contacts of the resistors Rlb and R2, and the source of the NMOS transistor T2 is connected to the negative power source Vss. In addition, the gate of the PMOS transistor T3 is connected to the drain of the NMOS transistor T1, the source of the PMOS transistor T3 is connected to the contacts of the resistors Rlb, R2, and the drain of the PMOS transistor T3 is connected to the negative power source Vss. The difference is that the gate of the NMOS transistor T1 is not directly connected to the positive power supply EVCC at this time, but is connected to the contacts of the resistors Rla, Rlb. The main purpose of this move is to reduce the gate voltage of the NMOS transistor (only part of the partial voltage of the positive power EVCC), so as to relieve the pressure on the gate. Therefore, this circuit can maintain a fixed output voltage and stable output characteristics when the external power supply EVCC rises. Please refer to Fig. 2B, which is an implementation circuit diagram of the reference voltage generating device in Fig. 2A. Among them, the resistors Rla, Rlb, R2, and R3 are composed of many small resistors of the same size]: formed in series, and the proportions of which are adjusted in different combinations. In this example, the resistor Rla is composed of 3 small resistors r in series, the resistor Rlb is composed of 2 small resistors r in series, and the resistor R2 is composed of 2 small JI I * ~~ f 1 " Order I, ^ (谙 Please read the notes on the back before filling in this page) This paper size applies to Chinese National Standards (CNS) A4 specifications (2 丨 0X297) 嫠 P4 3268 2 A7 B7 Offset Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Explanation of the invention (5) The resistor r is formed in series, and the resistor R3 is formed by three small resistors r connected in series. In addition, the NMOS transistors TI and T2 are composed of several different aspect ratios (W / I ^ transistors). In this example, the NMOS transistor TI is composed of one aspect ratio 1.6 / 7.5 and four aspect ratios. The NMOS transistor (tl ~ t5) with a ratio of 1.6 / 15 is connected in series. The NMOS transistor T2 is composed of three NMOS transistors with a width / length ratio of 1.6 / 20 (t6 ~ t8). In addition, the resistance R2, The ratio of R3 can be adjusted to control or fine-tune the output voltage VR2 to a predetermined range, such as 1.4V. The ratio of the resistors Rla and Rlb can be adjusted to control the pressure on the gate of the NMOS transistor T2. 3 is the reference voltage generating device of the present invention when the external power supply EVcc, the resistors R1, R2, R3 are 300K, 200K, 500K ohms, the width-to-length ratio (W / L) of the NMOS transistor TI, T2 is 1.6 / 67.5, 1.6 / 60, and the PMOS transistor T3 width to length ratio (W / L) of 48/1 output electric dust experimental results. As can be seen from the figure, the device of the present invention can stably maintain the output between the external power supply 1_5 ~ 7_5V The voltage is around 1.4V. In summary, the reference voltage output device of the present invention can change the thickness of the gate oxide layer without increasing the design. Reliable and stable dust output is maintained under difficult process conditions. Moreover, the resistor Rla and the resistors R2 and R3 can be completed by two resistors, or formed by small resistors in series, so it is very flexible in implementation. Although the present invention has been A preferred embodiment is disclosed as follows, but it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention 1 U ^^ (Read the precautions on the back before filling out this page) This paper is applicable _ furniture ratio (CNS) Α4 · (21GX297 public envy)