TW412858B - Input buffer of integrated circuit - Google Patents

Abstract

There is disclosed an input buffer of integrated circuit for receiving an input signal having TTL, LVTTL, SSTTL or GTL voltage level, buffering the input signal, and converting the input signal into an output signal capable of being received by an internal circuit. The input buffer has an adjustable threshold level. When the input signal is at the threshold, the output signal is allowed to switch between a first logic state and a second logic state. The adjustable threshold can be determined by an adjustable voltage circuit. The adjustable voltage circuit is not influenced by the parameters of semiconductor process, supplied power and operating temperature.

Description

--- I 412S58 A7 --- I 412S58 A7 Printed and gathered by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs --- B7, invention description (1) such as US patents 4,475,050 (Noufer), 5,304,867 (Moiris) As mentioned in 5,355,033 (jang), the design of input buffer circuits in integrated circuits is familiar to the public. This input buffer is an input signal that is used to receive electrical characteristics that are subject to logic techniques, such as TTL, LVTTL, SSTL, and GTL. The electrical characteristics of the above-mentioned logic technology are different from the electrical characteristics of the internal circuits in the integrated circuit. The input buffer should have a simple design, minimal time delay, low power loss, and high tolerance to external noise. In addition, the operating characteristics of the input buffer should not change with semiconductor processing parameters, power supply voltage, and temperature. The standard input buffer in a CMOS integrated circuit is usually a simple CMOS inverter (Smith's flip-flop) with or without hysteresis, as shown in Figure 1, or a differential amplifier, as shown in Figure 2. As shown in Figure 1, the CMOS inverter has a trip point or a temporary point, and the voltage level of the input signal at this trip point will cause the output to jump from a first logic state potential level to a second The logic state potential level jumps from a second logic state potential level to a first logic state potential level. This trip point can be governed by the proper design of the transistor in the input buffer, so that this trip point can correspond to the center point of the possible voltage swing of the turn-in signal. The CMOS inverter in Figure 1 is generally a faster method, because the input buffer is controlled by forcing the NMOS or PMOS transistor to turn on, and the other transistor is not controlled to control these two. The transistor (NMOS And PMOS). And the effective circuit J of this technology is very large. Very large. In the 13th paper scale, China's national standard rate (CNS > A4 specification (2 丨 〇 > < 297mm)) (谙 First read and read _ notes on the back before filling out this page) i k--1 ' Ding --5 Consumption cooperation between employees of the Central Bureau of Standards of the Ministry of Economic Affairs, printed 412858 A7 " ... B7 V. Description of the invention (2) The trip point of the CMOS inverter in the picture is based on the power supply voltage and processing parameters The above mentioned power supply voltage source and processing parameters will change the trip point of the CMOS inverter by approximately Q ^ V. Although this range is tolerable for logic technologies such as LVTTL, it is for SSTL It cannot be accessed. The differential amplifier input buffer in Figure 2 compares the voltage level of the input signal with a reference voltage Vref. In this way, the voltage of the input signal is a voltage greater than the reference voltage vref and a voltage greater than the reference voltage When the voltage between vref is low, the output will be switched between the first logic state (0) and the second logic state (1). Because the reference voltage vref can be precisely designed so that it does not affect the semiconductor processing parameters and power supply. Sensitive to changes in voltage and temperature Therefore, the trip point can be accurately controlled. For a more detailed description of the CMOS inverter with a Smith trigger, please refer to Figure 1. The above input signal is supplied to the input terminal INext. General input terminal INext is an input pad for a semiconductor chip and is connected to an external circuit as an input signal source. N-channel metal-oxide-semiconductor (NMOS) transistors N1 and N2 and P-channel metal-oxide-semiconductor (PMOS) transistors P2 and P3 form a CMOS Inverter. The gates of the NMOS transistors N1 and N2 and the gates of the PMOS transistors P2 and P3 are connected to the input terminal INEX1. The PMOS transistor P1 is used to activate and deactivate the CMOS. Inverter. An enable signal on the enable terminal is the gate connected to the PMOS transistor pi. If this enable signal is at the first logic state enable (0), it will cause the PM0S power Crystal P1 is turned on and NMOS transistor 4 is turned on ---------. 4 --------- --Order -------- SI--(Please read ## 的Note: Please fill in this page again.) This paper size applies to Chinese National Standard {CNS) A4 specification (210X297 mm) A7 B7 ^ 12858 V. Description of the invention (3) (Please read the precautions on the back of the page before filling out this page) N3 Stop Conduction ’and start the CMOS inverter. But 'if the enable signal is in the second logic state (1), the PM0S transistor P1 will stop conducting and the NMOS transistor N3 will be turned on, so the start of the CMOS inverter is cancelled' and the output becomes the first logic Status (〇). Printed by the Central Bureau of Standards, Ministry of Economic Affairs and Consumer Cooperatives when the CMOS inverter is activated and the input signal starts to transition from a low voltage level or a first logic state (0) to a high voltage level or a second logic state ( 1), NMOS transistors N1 and N2 will begin to conduct and PMOS transistors P2 and P3 will begin to cease to conduct. Once the input signal reaches the trip point, NMOS transistors N1 and N2 and PMOS transistors P1 and P2-all have the same At this time, the output is close to the middle range. The turn-in signal continues to be in the second logic state (1). When the load capacitor attached to the output terminal OUTint is discharged via the transistors N1 and N2, the voltage level at the output terminal OUTint will be close to the voltage level of the low-supply electric dust source. Conversely, when the input signal starts to transition from a high voltage level or a second logic state (1) to a low power waste level or a first logic state (0) * NMOS transistors think that N1 and N2 will start to stop conducting and The PMOS transistors P2 and P3 will start conducting. When the input signal passes through the trip point, the NMOS transistors N1 and N2 have the same continuity with the PMOS transistors P1 and P2. At this time, the output is close to the middle range. The input signal continues to be in the first logic state (0). The load capacitor on the output OUTint is charged to the voltage level of the high supply voltage source via the PMOS transistors P2 and P3. The trip point can be modified to provide the input signal from the first logic state (〇) to the second logic state (1) and from the second logic state (〇) to the first logic state. This paper applies the Chinese National Standard (CNS) ) A4 is present (2ί29 × 7mm)> The Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, India Poly 412Su8 V. Description of the invention (4) Hysteresis or change of the state of departure (1) ^ The above lag can be determined by NMOS transistor N4 or PMOS transistor P4 is established, and the transistor mentioned above can be arbitrarily added to the circuit to adjust the required hysteresis. When the input signal at the input terminal INext is in the second logic state (j) and When the output signal at the output terminal OUTint is in the first logic state, the PMOS transistor P4 is completely turned on (the gate-to-source voltage of the pMOS transistor P4 is equal to the negative high supply voltage p when the input signal iNext is changed from the second When the logic state (1) changes to the first logic state (0), the nmos transistors N1 and N2 start conducting. At this time, there will be a path from the drain to source of the series transistors pi, p2, P3, N1, and N2. Current flows because PMOS transistor P4 is fully turned on So basically the common node of PMOS transistor P2, P3 and P4 will be connected to the low supply voltage source. This common node is the source of PMOS transistor P3. As a result, PMOS transistor P3 is maintained in a non-conducting state. When input When the signal performance decreases toward the first logic state (0), the PMOS transistor 艎 Ρ2 starts to conduct and starts to increase the common node potential of the PMOS transistor P2, P3, and P4 from a low supply voltage level to a high supply voltage level. ^ The ratio of the PMOS transistor P2 and P4 sizes is such that when the input signal reaches the middle range of the signal amplitude, the PMOS transistor P3 is turned on (about 1/2 of the high supply voltage level). As long as the PMOS transistor P3 Completely on, the output signal on the output terminal OUTint immediately starts to rise from the first logic state (0) to the second logic state (1). At this time, the PMOS transistor P4 starts to stop conducting, and the PMOS transistor P3 is turned on .This will cause positive feedback, which will cause the output signal to rise to the second logic state quickly (1). Because the PMOS transistor 6 paper size applies to the Chinese national standard {CNS M4 specification U 丨 0X297 mm) --- -------,clothes- -^ ------- Order ------ 1% I (Please read the notes on the back of Mu before filling out this page) 412858 A7 B7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (5) The action of the body P4 is farther than the transition of the input signal from the second logic state (1) to the first logic state (〇) than if there is no pMOS transistor P4, that is, the buffer The trip point is a lower value for the transition from the second logic state (1) to the first logic state (0) than the transition from the first logic state (0) to the second logic state (1). The geometric ratio of PMOS transistors P2 and P4 can control the degree of hysteresis. For the entire symmetry and hysteresis adjustment, NMOS transistor N4 can be added arbitrarily. When the input signal on the input terminal lNext is in a first logic state (0) and the output signal on the output terminal OUTint is in a second logic state (1), the NMOS transistor N4 will be completely turned on (PMOS circuit The gate-to-source voltage Vgs of the crystal is equal to the low supply voltage level.) When the input signal INext changes from the first logic state (0) to the second logic state (1), the NMOS electrical sources N1 and N2 start conducting, So the current in the drain-to-source path of the series transistors PI, P2, P3, N1 and N2 will increase. Since the NMOS transistor N4 is fully on, basically the common node of the NMOS transistors N2, N1 and N4 is connected to a high supply voltage source. This common node is the source of the NMOS transistor N1. As a result, the NMOS transistor N1 remains non-conductive. When the input signal continues to rise toward the second logic state (1), the NMOS transistor N2 starts to conduct quickly and starts to make the common node of the NMOS transistor N2, N1 and N4 shift from the high supply voltage level to the low supply voltage level. The size ratio of the NMOS transistors N2 and N4 is a value that can make the NMOS transistor N1 turn on when the input signal has reached the middle range of the signal swing (about 1/2 of the high supply voltage level). When the NMOS transistor N1 is turned on, at the output terminal UTint 7 This paper size is applicable to the Chinese national standard 〇 (〇 奶) 8 4 wash grid (2) 0 > < 297 mm > ------- -'-„------- Order, ------ of 1-(#Please read the ii's on the back and fill in this page first.} The fifth, invention description (6), the output signal will start to fall from the second logic state (1) to the first logic state (0). At this time, the NOMS transistor N4 starts to stop conducting, and the NMOS transistor N1 is conducting. This will cause a positive feedback ', which will cause the output signal to fall to the first logic state quickly (0). Because of the action of the NMOS transistor N4, the input signal is lower than the first logic state if there is no NMOS transistor N4 ( 〇) The transition to the second logical state (1) is farther, that is, the jump point of the buffer is for the transition from the first logical state (0) to the second logical state (1) than the second logical state ( 1) The transition to the first logic state (0) is a lower value. The geometric ratio of NMOS transistors N2 and N4 can control the degree of hysteresis. Reference Figure 2 to understand the operation of the differential input buffer. The geometric ratio of PMOS transistor P1 to NMOS transistor N3 is equal to the geometric ratio of PMOS transistor P2 to NMOS transistor N4 (pi: N3 = P2: N4). Reference The voltage source Vref is connected to the gate of NMOS transistor N3 via NMOS transistor N1, but the input signal is coupled to the gate of NMOS transistor N4 via NMOS transistor N2. The reference voltage source Vref forces NMOS transistor N3 to be turned on, A bias point is established for PMOS transistor P1. The geometric ratio of PMOS transistor P1 to NMOS transistor N3 is selected so that the bias point is in the middle range between high and low supply voltages. PMOS transistors P1 and P2 The common connection of the gates will cause this bias point to be transferred to the section containing the circuit of the PMOS transistor P2 and the NMOS transistor N4. When the input signal at the input terminal INext is equal to the level of the reference voltage source Vref At the time, the output terminal OUTint is at the bias point. This will be based on the reference voltage source level and the 8 paper sizes of the buffer to the Chinese National Standard (CNS) A4 specification (2 丨 〇 > < 297) by 1 ^ 1 ^^^ 1 m »^^^ 1 ^ n— n ^ i In I ^ —-_l m 1-* — --a,. · ≫ J (please read the note on the back of the page first and then fill in this page before filling in this page) 412858 A7 B7 Printing policy of the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ) A close relationship is established between the trip points. If the input signal at the input terminal INext transitions between the first logic state (0) and the second logic state (1), the output signal at the output terminal OUTt will It will switch at the bias point established by the reference voltage source vref. The NMOS transistors N1 and N2 can ensure that any noise on the voltage reference source V'ref and the input terminal INext becomes as common mode as possible. It is also possible to decouple the NMOS transistors N1 and N2 to a high supply voltage source to some extent. An enable signal on the enable terminal is connected to the gate of the PMOS transistor P3. If the enable signal is at the first logic state (0), this will cause the PMOS transistor P1 to be turned on, thus starting the CMOS inverter. However, if the enable signal is in the second logic state (1), this will cause the PMOS transistor P1 to stop conducting, thus releasing the CMOS inverter. The PMOS transistor P4 is connected in parallel to the PMOS transistor P2 e. The gate of the PMOS transistor P4 is connected to the output terminal OUTint of the inverter Ir. The PMOS transistor P4 provides feedback by effectively changing the geometric ratio of the PMOS transistor P2 to the NMOS transistor N4 to generate a hysteresis phenomenon. A first object of the present invention is to provide an input signal in a integrated circuit that can receive a standard electrical characteristic voltage level such as TTL, LVTTL, SSTL, or GTL or a unique design characteristic voltage level, buffer the input signal, and The input signal is converted into an input buffer that an internal circuit can accept an output signal. 9 (Please read the notes on the back before filling this page) i Ding '-6 This paper size is applicable to China National Standards (CNS) A4 ^ (2 丨 〇X 297 mm) A7 B7 4I2S58 V. Description of the invention ( 8) A second object of the present invention is to provide an input buffer, and the critical trip point of the input signal in the input buffer will cause the output signal to change between a first logic state and a second logic state. A third object of the present invention is to provide an input buffer, and the critical trip point in the input buffer is determined by an adjustment voltage, and can be exempt from changes in semiconductor processing parameters, power supply voltage, and operating temperature. Shadow direction. To accomplish the above-mentioned object of the present invention, an input buffer circuit has an input terminal connected to an input / output pad, and the input / output pad is connected to an external circuit capable of generating an input signal. The buffer output terminal is coupled to an internal circuit to forward the output signal to the internal circuit. A voltage adjustment terminal is coupled to a voltage adjustment circuit. This voltage adjustment circuit can modify the voltage level characteristic trip point. At this trip point, the output signal will switch between the first logic state and the second logic state. 》 The input buffer has a first MOS transistor with a first on-state. The first MOS transistor in this first conduction mode has a gate connected to an input terminal, a drain connected to a buffer output terminal, and a source connected to a low supply voltage source. The input buffer has a first MOS transistor with a second on-state. The first MOS transistor of the second conduction mode has a gate connected to an input terminal, a drain connected to a buffer output terminal, and a source connected to a high supply voltage source. The input buffer has a second MOS transistor with a first on-state. The second MOS transistor in the first conduction mode has a gate connected to the input terminal, a drain connected to the output terminal of the buffer, and a source. This input buffer has a second paper size applicable to China's national standard (CMS > A4 specification "2 丨 〇X 297mm) Please read the note below and print it by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 412858 Α7 Β7 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Consumer Cooperatives, V. Invention Description (9) The second MOS transistor in the conduction mode. The second MOS transistor of the second conduction mode has a gate connected to the input terminal and a drain connected to the output terminal of the buffer wheel. The input buffer has a third MOS transistor in a first conduction mode. The third MOS transistor in the first conduction mode has a gate connected to a voltage adjustment terminal and a second MOS transistor connected to a first conductor. Source, and source connected to a low power supply. The input buffer has a third MOS transistor with a second conduction mode. The third MOS transistor of the second conduction mode has a gate connected to the voltage adjustment terminal, a gate connected to the second conduction mode, an anode of the MOS transistor, and a source connected to a high power supply. The voltage adjustment circuit consists of a replica wheel that reduces power proportionally: a buffer circuit, an amplifier, and an internal circuit inverter gate representing the integrated circuit.The amplifier has a buffer circuit coupled to a complex meter. The non-inverting spring at the output end of the buffer wheel and an output end connected to the voltage adjustment end of the replica input retarder circuit and the voltage adjustment end of other input buffer circuits. The inverter gate representing the internal circuit has an inverter input terminal connected to an inverter output terminal and the amplifier inverter terminal. Connecting the inverter input to the inverter output causes the voltage level on the inverting terminal of the amplifier to be set to an inverter critical level for the inverter gate. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the attached formula, a detailed description is as follows: A brief description of the circle type: 11 ---- ----- Take — „------ if ------- 1 Ί I t (please read the matter on the back first) and then fill out this page) The paper size is applicable to Chinese national standards ( CNS) Record 8 (210x297, 412858 A7, Consumers' Cooperative of the Central Standards Bureau, Ministry of Economic Affairs, Printed Collection B7, V7. Invention Description (ίο) Figure 1 shows the CMOS inverter input buffer used to explain one of the known technologies. Schematic diagram; Figure 2 shows a schematic diagram of a differential CMOS input buffer used to explain one of the prior art; Figure 3 shows a CMOS inverter input buffer with an adjusted trip point according to the present invention Schematic diagram of the circuit; FIG. 4 is a diagram illustrating the transfer characteristics of the input voltage and output voltage of the input buffer of the CMOS inverter according to the present invention; and FIG. 5 is a diagram illustrating the voltage adjustment circuit of a first embodiment of the present invention It is not intended, and FIG. 6 shows the CMOS inverter output used in the present invention. Schematic diagram of the first high-supply voltage adjustment circuit of one of the input buffer circuits: FIG. 7 shows a schematic diagram of the second high-supply voltage adjustment circuit for the input buffer circuit of the CMOS inverter in the present invention: FIG. 8 FIG. 9 is a schematic diagram showing an enabling circuit for a CMOS inverter input buffer circuit in the present invention; FIG. 9 is a schematic diagram showing a CMOS inverter input buffer circuit in combination with a hysteresis according to the present invention; and FIG. 10 It is a schematic diagram showing a CMOS inverter input buffer circuit combining one of the hysteresis phenomena of the present invention. Brief description of the drawings: P1-P channel MOS transistor, P2 ~ P channel MOS transistor, P3 ~ P channel MOS transistor, P4 ~ P-channel MOS transistor, N-channel N-channel M0S transistor, N2-N-channel M0S transistor 12 --------- 知 衣 ----- ^- Order -------% I-► (Please read the notes on the back of I before filling out this page) This paper size applies to Chinese national standards (CNS > A4 specifications (2〗 0XW7 mm) Central Ministry of Economic Affairs Printed bag of the British Bureau of Labor Standards Cooperative Co., Ltd. 41 £ 858_b7__V. Description of the invention (11) Body, N3 ~ N channel MOS Transistor, N4 ~ N-channel MOS transistor, INext ~ Input, OUTjnt ~ Output, 'ENABLE ~ Enable, High Supply ~ High Supply, Low Supply ~ Low Supply, Vrcf ~ Reference Voltage, 1W Internal inverter gate, Qi and Q3 ~ NMOS transistors, Q2 and Q4 ~ PMOS transistors, Q5 ~ NMOS transistors, Q6 ~ PMOS transistors, Vadj ~ adjust voltage circuit, ~ Output high voltage level, Vu ~ Enter the low voltage level, Vth. ~ Critical trip point, BUF1 ~ Inverter input buffer circuit, Vreg ~ Voltage regulator, Q9 ~ PMOS transistor, Q10 ~ PMOS transistor, ship, Q11 ~ NMOS transistor, Q12-NMOS transistor, Q13 ~ PMOS transistor, DIB ~ replica input buffer circuit, OP ~ amplifier, SCG ~ sampling CMOS gate. Embodiment: Refer to FIG. 3 to discuss the operation of the input buffer circuit. The inputs are the gates connected to the NMOS transistors Q1 and Q3 and the PMOS transistors Q2 and Q4. The input terminal is connected to an external circuit that can provide an input signal via an input / output pad. The input signal is subject to characteristic voltage level technologies, such as TTL, LVTTL, SSTL, and GTL. Electrical characteristic voltage level β PMOS The source of transistor Q2 is connected to a high supply voltage source. The drains of the PMOS transistors Q2 and Q4 are connected together and connected to the output and the drains of the NMOS transistors Q1 and Q3. The output is an internal circuit connected to the integrated circuit. The source of the NMOS transistor Q1 is connected to a low supply voltage source. 13 (Please read the note ^^ on the back of the page before filling this page) The paper size of the edition is applicable to the Chinese national standard (CNS > A4 size (210X297 mm) 412858 A7 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of the invention (12) The source of the PMOS transistor Q4 is connected to the drain of the PMOS transistor Q6, and the source of the PMOS transistor Q6 is connected to a high supply voltage source. The source of the NMOS transistor Q3 is connected To the drain of the NMOS transistor Q5. The source of the NMOS transistor Q5 is connected to a low supply voltage source. The gates of the NMOS transistor Q5 and the PMOS transistor Q6 are connected together and connected to a regulating voltage circuit Vadj » The above adjustment voltage circuit Vadj provides a voltage, and this voltage is close to the middle range between the voltage levels of the high supply voltage source and the low supply voltage source. In this case, the PMOS transistor Q6 and the NMOS transistor Q5 will be turned on A certain degree, and this degree is determined by the voltage level of the above-mentioned adjustment voltage circuit Vadj. Because the voltage level of the adjustment voltage circuit Vadj is about the middle range between the voltage levels of the high supply voltage source and the low supply voltage source Has an operating range, in which the conduction of PMOS transistor Q6 and NMOS transistor Q5 can be controlled at the same time, so this basic condition provides the most general adjustment of the buffer trip point. PMOS transistor Q6 and NMOS transistor The geometry of the crystal Q5 is larger than that of the PMOS transistor Q4 and the NMOS transistor Q3, so that the PMOS transistor Q6 and the NMOS transistor Q5 are maintained in a linear or "resistive" region during the operation of the input buffer circuit. It indicates that the PMOS transistor The operation equation of crystal Q6 and NMOS transistor Q5 is: Ids = K * {(Vgs_Vt) * VdsK1 / 2) * VDS2} where 14

---------- ^ ---- Order one ------ 1 rr (Please read the notes on the back before filling in this page J This paper size applies to China National Standard (CNS) A4 specifications (210X29? Mm) Printed by the Consumers Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 412858 at B7 Five 'Invention Description (13)

Ids: current from drain to source of transistor; K: constants related to mobility, gate capacitance and transistor size; Vgs: voltage from gate to source of transistor;

Vt. Is the voltage between the gate and the source of the transistor. This voltage will start the transistor to conduct; and:

Vds ‘is the voltage from the electrode to the source of the transistor. When the drain-to-source voltage VDS is small, the above equation can be regarded as linear, so the effective resistance of each transistor is: R = i_ ^ os_), R = K * < V〇S ~ VT) where R: The resistance transistor is at the trip point for the input buffer circuit. Because the 閛 and drain electrodes will be at the same potential, the PMOS transistors Q2 and Q4 and the NMOS transistors Q1 and Q3 are in a saturated state. For sub-micron field effect transistor processing, the saturation characteristics of the main conductive crystal are saturated, so the drain-to-source current is a linear function of the gate-to-source voltage VGS or is:

Ids = K * (Vgs-Vt) where K is the saturation gain constant. The source of NMOS transistor Q3 is connected in series with NMOS transistor Q5. Because the NMOS transistor Q5 is basically a resistor (represented by R5), the NMOS transistor Q5 will reduce the gate-to-source voltage VGS of the NMOS transistor by an amount proportional to the drain current. NMOS transistor Q3 liquid electrode 15 This paper size applies to Chinese national standards (CNS > A4 size (2 丨 0 · 〆297mm) ^ ------, I order ------% t ( (Please read the meaning of "6" before filling out this page) 412858 A7 B7 V. Description of the invention (14) The function of the source current is

Iq3DS = Kq3 * (Vq3GS-R5Iq3DS-Vq3T) I〇n κΦ

QJGS -v,

The result of the resistance R5 of QiTl NMOS transistor Q5 will reduce the effective gain factor of NMOS transistor Q3 as follows: ΚΦ ΚΦ The operation of printing NMOS transistors by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs is based on the standard saturation current equation gain factor KQ3 by The range controlled by the resistance R5 of the NMOS transistor Q5 is determined by the value of the resistance R5 of the NMOS transistor Q5. When the NMOS transistor Q5 is hardly turned on and the resistance R5 of the NMOS transistor Q5 is very large, the effective gain constant of the NMOS transistor Q3 is: and it will be almost zero. If the value of the resistance R5 of the NMOS transistor Q5 and the effective gain KQ3 of the NOMS transistor Q3 are close to zero, the NMOS transistor Q3 will produce the maximum effective gain KQ3. In this case, the gain constant will be equal to KQ3 for the NMOS transistor Q3 itself. »In order to make the value of the resistance R5 of the NMOS transistor Q5 relative to the gain constant of KQ3 for the NMOS transistor Q3 negligible, then the NMOS transistor Q3 In comparison, the NMOS transistor Q5 has a large width-to-length ratio β and the width-to-length ratio should not be infinite. For NMOS, the paper size of this paper applies the Chinese National Standard {CNS) A4 specification (210X297 mm) ^^^ 1 υ κι— ^^^^ 1 mu IL at IV one order,-·--(Please read t first #. Note on the back then fill out this page) A7 B7

V. Description of the invention (15) The actual range gain Kq3 of the crystal Q3 and the NMOS transistor Q5 can be from 0 (the NMOS transistor is not conducting) to 0.666 KQ3 (the NMOS transistor Q5 is conducting). Therefore, the entire effect of the resistor R5 of the NMOS transistor Q5 will change the gain constant Kq3 β of the NMOS transistor Q3 because of NM〇; Therefore, the gain is increased as follows: The source of the PMOS transistor Q4 is connected in series with the pmo'S transistor Q6 »Because the PMOS transistor Q6 is basically a resistor (represented by R6), the PMOS transistor is expected to be proportional to the electrodeless current To reduce the gate-to-source voltage VGS of the PMOS transistor Q4. The analysis of the gain KQ6 of the PMOS transistors Q4 and Q6 is the same as that of the above NMOS transistor Q3 and Q5. Therefore, the overall effect of the resistance R6 of the NMOS transistor Q6 will change the gain constant KQ4 of the PMOS transistor Q4. Because the resistance R6 of the PMOS transistor Q2 and the PMOS transistor Q6 is connected in parallel in the buffer circuit, the gain is increased as: KQ. I

K {Q (#Xianwen 谏 Notes on the back of the page before filling out this page) Order "ίέ Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs {«? 事, W [wq Now discuss the calculation of the trip point, for a simple In CMOS inverter, the critical voltage VT phase I of NMOS transistor and PMOS transistor in I is small at high supply voltage source (Vcc). Use the NMOS transistor to test the gain constant of the PMOS transistor to calculate the trip point. The expression is as follows: This paper size applies to China National Standards (CNS) Α4 specifications (2 丨 0 X 297 mm) 412858 A7 B7 V. Description of the invention (16) (rigid

Ks

Vc ~ (KN ^ KF) where v (trip > is the trip point voltage of the CMOS inverter printed by Shelley Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs; KNg is the gain constant of the NMOS transistor of the CMOS inverter; KP is the CMOS The gain constant of the PMOS transistor of the inverter. In addition to the effective gain constant replacing the above gain constant, the same equation will be applied to the input buffer of the invention. The calculation becomes: V (trip) __ K. {Q \ HQiRS} _ (^ L «5} + K. {QlllQ * tl ^ As in the design example above, if NMOS transistor Q1 and PMOS transistor Q2 are designed to have a gain constant κφ * KQ2 of the same value as K, and NMOS transistor Q3 and PMOS transistor The crystal Q4 is designed to have gain constants KQ3 and KQ4 of the same value as 2K. With respect to the 2K value, the resistance values R5 and R6 of the designed NMOS transistor Q5 and PMOS transistor Q6 are negligible. If these values are substituted for the above In the function, the adjustment range of the NMOS transistor and the PMOS transistor is equal, and the range is as follows: κ < K {Qu / QUtS} < 3 * κ ^ < K {Q2 // QAR6} < 3 * ^ So the adjustment range of v (trip) / vcc can be expressed as follows: l./4<V(trip)/Vcc<3/4 This will provide more than most The circuit requires a wider adjustment band. Due to the fact that it has a non-zero critical voltage and the size of the actual device, the above adjustment band will naturally be narrower. This adjustment band will not be larger than the high supply voltage source Vcc 18 This paper size is suitable for China National Standard (CNS) A4 Specification (210X297mm) --------- X ----- Order ------ i ί-(Please read the notes on the back of the asset before filling in this Page) 412858 A7 Printed by B7 Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (17) 25% Large> Generally, a good design will make an inverting device formed by NMOS transistor Q1 and PMOS transistor Q2 There is a trip point close to the design value of the interface specifications, and small adjustments are made using the adjustment values from NMOS transistors Q3 and Q5 and PMOS transistors Q4 and Q6. This reduces the sensitivity of the circuit to the adjustment voltage source Vadj To the minimum, and to maximize the noise edge of the voltage source Vadj. Now refer to Figure 4 to understand how the adjustment voltage affects the conversion characteristics of the voltage level of the input signal and the voltage level of the output signal. Section 4 Indicates the output signal on the vertical axis and the input signal on the horizontal axis Voltage level map of the digital signal. When the voltage level of the input signal is at a low voltage level (first voltage level (0)) 乂 „, the output voltage level is at a high voltage level (second voltage level (LDV ^. When the voltage level of the input signal rises to the critical trip point Vth. Level, the voltage level of the output signal will quickly change to the low voltage level (the first logic level (0)) »The voltage of the input signal will continue to rise to the high voltage level (the second logic state (l)) Vih. The difference between the threshold voltage level VthO and the voltage level Vih and between the voltage level Vii and the threshold level VthQ determines the noise margin of the input buffer circuit. Because of changes in semiconductor processing parameters, power supply voltage, or temperature, the critical trip point VthG may not be exactly at the critical trip point required by electrical characteristics such as TTL, LVTTL, SSTL, and GTL. In order to compensate the displacement at the critical trip point VthC, the adjustment voltage can be lowered to shift the critical trip point to the voltage level Vthl, or the adjustment voltage can be adjusted to be higher to shift the critical trip point to the voltage level Vth2. . 19 --------- ^ ----- ^ —— Order ------ t — I '{Please read the ins and outs on the back before filling out this page) This paper size applies to China National Standards (CNS) A4 Washing (210X297 mm) 412858 A7 B7 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, Co., Ltd. 5. Description of the Invention (18) Does the 5th circle show that there is no power adjustment circuit, and this The electric grinder adjustment circuit can provide the adjustment voltage Vadj for a plurality of input buffer circuits as shown in Fig. 3 "A duplicate input buffer circuit in the third circle has an input connected to a reference electric grinder source Vref. Scale down to minimize the DC power supply of the circuit. The reference voltage source vrCf can be located inside or outside the integrated circuit with an input buffer (as shown in Figure 3). This reference voltage source is equivalent to the expected trip point of the input buffer in the third circle, and is designed to be independent of changes in semiconductor processing parameters, power supply voltage, and temperature. The output of the duplicate input buffer circuit DIB is a non-inverting input (+) connected to the amplifier op. The inverting input (-) of the amplifier is connected to a sample CMOS gate SCG, and the CMOS gate is properly arranged to minimize DC power and its input is connected to its own output The gate is a duplicated internal circuit of the integrated circuit, and the integrated circuit has an input buffer circuit as shown in FIG. 3. By connecting the input of the sampling CMOS circuit to the output of the sampling CMOS inverter, the voltage on the inverting input of the amplifier is set to the critical voltage of the internal circuit. The output of the amplifier becomes the regulated voltage Vadj and is connected to a plurality of input buffer circuits in the third circuit. The output of the amplifier is also the regulated voltage Vadj connected to the replica input buffer. (The output of the replica input buffer circuit in Figure 3 will be set to the threshold voltage of the internal gate. The feedback from the replica input buffer circuit in Figure 3 to the amplifier will often set the adjustment voltage, so 20 This paper size is applicable to China National Standards (CNS) 8-4 specification U10X297 mm) --------- ^-^ ---- ^-Order ------- ^ 1-' (Please read this first and then on the back) i. Matters before filling out this page) 412858 A7 B7 V. Description of the invention (19) The output voltage of the replica input buffer circuit in Figure 3 will be at the threshold voltage of the internal gate. Referring now to the 6th and 7th series, a high supply voltage adjustment circuit of the CMOS inverter input buffer circuit of the present invention is shown. The inverter input buffer circuit BUF1 of the present invention may have a power supply for a voltage source, and the power supply voltage source is larger than a value that must be an interface of the internal circuit. If the power supply voltage source is large enough, the input buffer circuit BUF1 will consume excessive power. To solve this problem, a PMOS transistor is placed between the power supply voltage source (high supply voltage) and the high supply voltage terminal of the input buffer circuit BUF1 (as shown in Figure 6, the PMOS transistor Q9 will be considered the same The diode is connected so that the voltage at the high supply voltage terminal of the input buffer circuit BUF1 is the value of the power supply voltage source and is smaller than the threshold voltage VT of the PMOS transistor Q9. If the voltage at the high supply voltage terminal of the input buffer circuit is The voltage level is greater than the threshold voltage VT of the PMOS transistor Q9, then a voltage regulator Vreg will be placed between the high supply voltage terminal of the input buffer appliance BUF1 and the power supply voltage source (high supply voltage) (such as the first As shown in Figure 7: This voltage regulator will generate a lower voltage, LowerV, to supply the high supply voltage terminal of the input buffer circuit BUF1. Referring to FIG. 8 to discuss a method for controlling the start of the input buffer circuit BUF1 in the present invention. Enable circuit. PMOS transistor Q10 is placed between the high supply voltage and the high supply voltage terminal of the input buffer circuit BUF1. The enable signal on the enable terminal is connected to "Gate of PMOS transistor" 21 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 412858 A7 B7 V. Description of invention (20) NMOS transistor The drain of Q11 is connected to the output of the input buffer circuit BUF1, and its source is connected to the low supply voltage, and its gate is connected to the enable. If the enable is in the first logic state (0), it will cause the PMOS transistor Q10 to be turned on, so the input buffer BUF1 is started and the NMOS transistor Q11 is brought into a non-conducting state. However, if the enable signal is in the second logic state (1), it will The PMOS transistor Q10 is stopped to be turned on, thereby cancelling the start of the CMOS inverter, and the NMOS transistor Q11 is turned on, thereby effectively connecting the output terminal to a low supply voltage. The ninth chart shows the hysteresis adjustment of the first form. Input buffer The output terminal of the inverter circuit BUF1 is connected to the source of the NMOS transistor Q12 and the PMOS transistor Q13 and the input of the internal inverter gate h. The source of the NMOS transistor Q12 is connected to a low supply voltage source. The source of the PMOS transistor Q13 is connected to a high supply voltage source. The output of the internal inverter h is connected to the gate of the NMOS transistor Q12 and the PMOS transistor Q13. If the output terminal is in the first logic state (0) , The output to the internal inverter II is in the second logic state (1), which causes the NMOS transistor Q12 to be turned on, thereby effectively putting the output at a low supply voltage. When the input of the input buffer circuit BUF1 starts from the second When the logic state (1) changes to the first logic state (0), the input buffer circuit BUF1 will start to boost the voltage at the output terminal. This will cause the internal inverter to change state, so the on-state of the NMOS transistor will be suspended and the PMOS transistor will be turned on. Order at --- r I ----% I-'' (Please read first Note on the back of the treatment, please fill in this page again) This paper size is applicable to China National Standard (CNS) 8 4 specifications (210X297 mm) 412858 A7 Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs B7 V. Description of invention (21) Turning on this will cause a positive feedback so that the internal inverter enters the first logic state (0) and the output quickly becomes the second logic state (1). This change occurs at a voltage level, which is different from the voltage level determined by the adjustment voltage Vadj. If the input of the input buffer circuit BUF1 is in the second logic state (0) and is about to change to the second logic level, the hysteresis action is the same as described above, but in a different direction. The output level is determined by the geometry of the NOMS transistor Q12 and the PMOS transistor Q13. Reference is now made to Fig. 10 for another structure of an input buffer circuit incorporating hysteresis. The NMOS transistors Q1, Q3, and Q5 and the PMOS transistors Q2, Q4, and Q6 form the input buffer circuit as shown in Figure 3. "The NMOS transistor Q7 is connected to the common node of the NMOS transistors Q3 and Q5 and a high-voltage supply source. "When the input signal on the input terminal is in the first logic state (0) and the output is in the second logic state (1), the NMOS transistor Q7 is on, so between the NMOS transistors Q3 and Q5 A high supply voltage source is connected to the common node. When the input signal on the input terminal starts to change from the first logic state (0) to the second logic state (1), the NMOS transistor Q1 starts to conduct the port, thereby reducing the voltage on the output. Because the source of the NMOS transistor Q3 is at a high supply voltage level, the NMOS transistor remains off. This is slightly similar to that described in Figure 1 and will modify the trip point of the inverter \ established by the adjustment voltage Vadj. The PMOS transistor Q8 is connected between a common node between the PMOS transistors Q4 and Q6 and a high supply voltage source. When inputting 23 H-! HI- II on the input side:-^^ 1--In HTP 1---One eJ--,-(Please read the notes on the back before filling this page) This paper The scale is applicable to China's national standard rate (〇 ^), eight-four gauges (210 > < 297 gong) 41S858 A7 B7 V. Description of the invention (22) The signal is in the second logic state (1) and the output is in the first logic state In the state (0), the PMOS transistor Q8 is turned on, so that the common node between the PMOS transistor Q4 and Q6 will be connected to a low supply voltage source. When the input signal on the input terminal starts to change from the second logic state (1) to the first logic state, the PMOS transistor Q2 starts to conduct, thereby increasing the voltage on the output. Because the source of the PMOS transistor is at a low supply voltage source, the PMOS transistor Q4 will remain off. This is slightly similar to that described in Figure 1 and will modify the trip point of the inverter established by adjusting the voltage Vadj. Hysteresis is controlled by the geometric ratio of the NMOS transistors Q3 and Q7 and the geometric ratio of the PMOS transistors Q4 and Q8. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. ^^^^ 1 m ^ — mu ^^^ 1 ί ^ p ^ pf ^^^^ 1 m 1-"i (谙 Please read the 1 notes on the back before filling out this page) Staff of the Central Sample Rate Bureau of the Ministry of Economic Affairs The scale of the printed paper of the consumer cooperative is applicable to the Chinese National Standard (CNS) A4 standard (210X297 mm)

Claims (1)

412858 as C8 ---- ^ __ 6. The input buffer circuit in the patent application circuit, the round-in buffer circuit is coupled between the ^^ 2 high supply voltage source and the-low supply voltage source to receive an input signal Buffering the input signal and converting the input signal into an output signal acceptable to the internal circuit in the integrated circuit, which includes: " " (a) —input terminal 'which is connected to an input / output pad, The input / output pad is connected to an external circuit capable of generating the input signal; (b) a buffer output terminal, which is coupled to the internal circuit to transmit the output signal to the internal circuit; (c) a voltage The adjusting end is coupled to a voltage adjusting device to modify the buffer critical trip point of the first input signal, wherein the buffer critical trip point determines a round of input voltage level of the input signal, and at the input voltage level The output signal on the bit will change from the first output logic level to the second output logic level: (d) — high supply terminal, which is connected to the high supply voltage source; (e) — low supply terminal, which is connected to The low power supply Source; Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs --------- Install I J-- H (Please read the '5-ji.WK item on the back before filling this page) (f) a The first CMOS transistor in the first conduction mode has a gate connected to the input terminal, a drain connected to the output terminal of the buffer, and a source connected to the low supply terminal; (g) — second conduction Form a first MOS transistor, which has a gate connected to the input terminal, a drain connected to the buffer output terminal, and a source connected to the high supply terminal; (h) — Two MOS transistors with a gate connected to the input, and a drain connected to the output of the buffer »25 papers, medium solid two miscellaneous rate (CNS), 8 4lin (210X297) The Ministry of Standards and Technology Bureau of the Bayer Consumer Cooperative Co., Ltd. today ’s policy 4i2S5e cl D8 VI. Patent application scope and a source; (i) A second MOS transistor with a second conduction mode wants to have a connection to the input terminal. A gate, a pole connected to the buffer output terminal, and a source; The third MOS transistor in the conducting form has a gate connected to the voltage adjustment terminal, a drain electrode connected to the source of the second MOS transistor in the first conducting form, and a low-supply conducting form. (K) a third MOS transistor in a second conduction mode having a gate connected to the voltage adjustment terminal, and a drain connected to a source of the second MOS transistor in the second conduction mode And a source connected to the high supply side. 2. If the input buffer circuit of item 1 of the patent application scope, the input signal is a voltage signal selected from a group of voltage signals, and the group of voltage signals includes a TTL signal, an LVTTL signal, an SSTL signal, and a GTL signal. 3. The input buffer circuit according to item 1 of the patent application scope, wherein the voltage adjusting device comprises: (a) a replica input buffer circuit having an input terminal connected to a reference power source; (b) an amplifier, It has a non-inverting terminal coupled to the buffer output terminal of the replica input buffer circuit, an amplifier coupled to the voltage adjustment terminal of the replica input buffer circuit and the voltage adjustment terminal of the input buffer circuit. The output terminal and an inverting terminal; 26 --II-II- installed ------ 1 ~~ order < please read the precautions on the back before filling in this page) This paper size is not used in China Standard (CNS) Λ4 specification (210X297 mm) 412858 Α8 Β8 C8 D8 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. Application scope (C)-represents the inverter gate of the internal circuit, which has a An inverter input terminal connected to an inverter output terminal and the inverting terminal of the amplifier is set to an inverter critical level for the voltage level of the inverter gate at the inverting terminal. Bit. 4. If the input buffer circuit of item 1 of the patent application scope further includes a power saving device to reduce the voltage level of the high supply voltage source so as to minimize the power loss of the input buffer circuit, it is coupled to 5. Between the high-supply voltage source and the high-supply terminal 5. As in the patent application No. 4 of the punch circuit, wherein the power saving device includes a diode, which is connected to the MOS transistor in the second conduction mode, and The voltage level of the high supply voltage source is reduced by a voltage equal to the threshold voltage of the MOS transistor in one of the second conduction modes. 6. The input buffer circuit of item 4 of the patent application, wherein the power saving device is a voltage regulator that reduces the voltage level of the high supply voltage source to a desired low voltage. 7. If the input buffer circuit of item 4 of the patent application includes an enabling device, it is coupled between the high supply voltage source and the high supply terminal, and between the buffer output terminal and the low supply terminal. In the meantime, the input buffer circuit is enabled and disabled based on a logic level on an enable control terminal. 8. If the input buffer circuit of item 4 of the patent application includes a hysteresis device, which is coupled Between the buffer output end, the high supply end and the low supply end, to modify the critical trip point of the buffer, so for 27 (please read the note ^^ on the back before filling in this purchase) Standard Chinese Standard (CNS) A4 specification (210X297 mm) A8 BS CE D8 41285 $ 6. Application scope of patent The input voltage level changes from the first logic level to the second logic level and from the second logic The critical trip point of the buffer from the level change to the first logic level is different. The hysteresis device includes: (a) —a fourth MOS transistor, which is one of the first conduction modes, and has a side connection. To the source of the low supply, The drain and a gate of the output terminal of the amplifier; (b) a fourth MOS transistor, which is a second conduction mode, which has a source lightly connected to the high supply terminal, and a drain connected to the buffer output terminal And a gate; and (c) a hysteretic control gate having a gate connected to the output of the buffer, and a gate of a fourth MOS transistor that is coupled to the first and second conduction modes And an inverting device capable of inverting an output signal on the buffer output terminal, wherein if the output signal is at a first logic level, the fourth MOS transistor of the first conduction mode is “Continuity” If the output signal is at the second logic level, the fourth MOS transistor of the second conduction form is on, and when the input signal starts to change between the first logic level and the second logic level, the first The fourth MOS transistor with one conduction mode and the second conduction mode will modify the critical trip point of the buffer. 9. If the input buffer circuit of the first patent application scope includes a hysteresis device, which is used to modify the buffer Critical trip point The change of the critical trip point for the input voltage level from the first logic level to the second logic level is different from the change of the input voltage level from the second logic level to the first logic level, wherein the hysteresis device Includes the 28th paper standard applicable to the China National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling out this page) r Printed by the Central Standards Bureau of the Ministry of Economic Affairs and the Consumer Industry Cooperatives « 2658 AB, CD The Central Standards Bureau of the Ministry of Economic Affairs and the Consumers' Cooperative printed the fifth MOS transistor in the second conduction mode. The source of the fifth MOS transistor in the second conduction mode is connected to the second conduction mode. The wave electrode of the third MOS transistor, the drain of the fifth MOS transistor in the second conduction mode is coupled to the low supply terminal, and the gate of the fifth MOS transistor in the second conduction mode is coupled. Connected to the buffer output terminal, if the output signal is at the first logic level, the fifth MOS transistor in the second conduction mode will be turned on, and the source of the third MOS transistor in the second conduction mode is effectively coupled To Supply terminal, and if the output terminal is at a second logic level, the MOS transistor making five second conduction aspect will not conducting, resulting in differences in the critical point of the buffer. 10. The input buffer circuit according to item 1 of the patent application scope further includes a hysteresis device for modifying the critical trip point of the buffer, so that the critical trip point of the buffer is adjusted from the first logic level to the input voltage level. The change of the bit to the second logic level is different from the change of the input voltage level from the second logic level to the first logic level, wherein the hysteresis device includes a fifth MOS transistor in a first conduction mode, and the first conduction The source of the fifth MOS transistor in the first form is coupled to the drain of the third MOS transistor in the first conducting form, and the drain of the fifth MOS transistor in the first conducting form is connected to the high supply terminal, and The gate of the fifth MOS transistor in the first conduction mode is coupled to the buffer output terminal. If the output signal is at the second logic level, the fifth MOS transistor in the first conduction mode will be turned on. And effectively couples the source of the third MOS transistor to the high supply end, and if the output signal is at the first logic level, the fifth MOS transistor in the first conduction form will not be turned on, thus causing The 29 books Zhang scale is applicable to Chinese girl family standard (CNS) A4 wash (210X297 mm)% Backnote 1 Binding A8 B8 C8 D8 412S5S Patent application buffer limit critical! ^ Different ^^ 1 In ^^ 1 ^^ 1 ^^ 1 ^^ 1 I—--1 ^ 1 ^^ 1 Irί t Ir— ^^ 1 {Please read the note ^^ on the back before filling this page) The integrated circuit has a threshold voltage-adjustable input buffer Circuit 'The input buffer circuit is coupled between a high supply voltage source and a low supply voltage source in order to receive an input signal and convert the input signal into an output signal acceptable to the internal circuit in the integrated circuit. It includes: (a) a buffer comprising: an input terminal 'which is coupled to an input / output 塾 connected to an external circuit and the external circuit will generate the input signal; a buffer wheel output terminal which Connected to the internal circuit so as to transmit the output signal to the internal circuit; an electrical adjustment terminal, which is connected to a voltage adjustment device to modify a buffer trip point of the round-in signal, wherein the buffer criticality determines the Input voltage level And on the input voltage level, the output signal will change from a first output logic level to a second output logic level; a high supply end coupled to the high supply voltage source; a low supply end , Which is coupled to the low supply voltage source; the first standard MOS transistor of the first conduction mode, which is a first conduction mode of the first MOS transistor, which is connected to the input terminal, and connected to the low The source of the supply terminal; a first MOS transistor of a second conductive form having a gate connected to the input terminal, a drain connected to the buffer output terminal, and a source connected to the high supply terminal ; A second MOS transistor of the first conduction form, which has a series of 30 paper sizes (CNS) A4 size (210X297 mm) 412658 A8 B8 C8 D8 Printing policy of the Bureau of Consumer Products Cooperative 6. The patent application scope is connected to the gate of the input terminal, a drain connected to the buffer output terminal, and a source; a second MOS transistor of the second conduction form, its A gate electrode connected to the input terminal, a drain electrode connected to the output terminal of the buffer, and a source electrode; a third MOS transistor in the first conduction mode has a gate connected to the voltage adjustment terminal; A drain connected to the source of the second MOS transistor Zhao Zhi of the first conduction mode, and a source connected to the low supply terminal; and a third MOS transistor of the second conduction mode, which has A gate connected to the voltage adjustment terminal, a drain connected to the source of the second MOS transistor in the second conduction mode, and a source connected to the high supply terminal; and (b) a voltage adjustment device , Which is coupled to the voltage adjustment terminal to modify a buffer threshold of the input signal, wherein the buffer threshold determines an input voltage level of the input signal, and at the input voltage level the output signal will be from a first The turn-out level is shifted to a second input-two level, which includes: a copy of the puncher circuit having an input terminal connected to a reference voltage; an amplifier having a buffer coupled to the input buffer A non-inverting terminal of the buffer output terminal of the replica of the circuit, an amplifier output terminal connected to the voltage adjusting terminal of the replica of the input buffer circuit and the voltage adjusting terminal of the input buffer circuit, and an inverting terminal; 31 (Please read the notes on the reverse side before filling out this page)%? R This paper size is applicable to the Chinese National Standard (CNS > A4 size (2 丨 0X297 mm)) 412858 as B8 C8 ______D8 6. Apply for patent Fangu 17. If the input buffer circuit of the patent application item η includes a hysteresis device, it is coupled to the buffer output, high supply and low supply To modify the critical trip point of the buffer, so that the critical trip point of the buffer for the input voltage level is changed from the first logic level to the second logic level is different from the input voltage level from the second The logic level is changed to the first logic level, wherein the hysteresis device includes: (a) the fourth MOS transistor in the first conduction mode, which has a source coupled to the low supply end, A drain electrode coupled to the buffer output terminal and a gate electrode; (b) a fourth MOS transistor in the second conduction mode, which has a source electrode coupled to the high supply terminal and a coupling A drain to the buffer output and a gate; and (c) a hysteretic control gate having a wheel-in terminal coupled to the buffer output, a first conduction pattern and a second conduction An output terminal of the gate of the fourth MOS transistor and an inverting device for inverting the output signal at the buffer output terminal, wherein if the output signal is at the first logic level The fourth MOS transistor in the first conduction mode will be turned on. If the output signal is at a second logic level, the fourth MOS transistor in the second conduction mode will be turned on. When the input signal starts at When the first logic level and the second logic level change, the fourth MOS transistor of the first conduction form and the second conduction form will modify the critical trip point of the buffer. 18. If the input buffer circuit of the 11th patent application scope includes a hysteresis device to modify the critical trip point of the buffer, so the 33 paper standards are applicable to China National Standard (CNS) A4 (210X297) (Mm) ^^ 1 HI ^^^ 1 ml f4 ^^^ 1 .J (Please read the back of 59 first < note the ^ -item before filling out this page) Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs AS BS C8 m 6. The patent application scope buffer critical trip point is different from the first logic level to the first logic level when the input voltage level is changed from the first logic level to the second logic level. Wherein the hysteresis device includes a fifth MOS transistor of the second conduction mode, which has a source coupled to a drain of the third MOS transistor of the second conduction mode, and a source coupled to the low The drain terminal of the supply terminal and a gate coupled to the output terminal of the buffer, wherein if the output signal is at the first logic level, the fifth MOS transistor in the second conduction mode will be turned on, and Effectively the third MOS transistor in the second conduction mode The source is coupled to the low supply end, and if the output signal is at the second logic level, the fifth MOS transistor in the second conduction mode will not be turned on, thus causing the buffer critical point s difference. 19. The input buffer circuit according to item 11 of the patent application scope further includes a hysteresis device for modifying the critical trip point of the buffer, so that the critical trip point of the buffer changes the input voltage level from the first The change from the logic level to the second logic level is different from the change from the second logic level to the first logic level, wherein the hysteresis device includes a fifth MOS transistor that is one of the first conduction modes and has a A source coupled to the drain of the third MOS transistor in the first conduction mode, a drain coupled to the high supply terminal, and a gate coupled to the buffer output terminal, where if the output signal Is at the second logic level, the fifth MOS transistor in the first conduction mode will be turned on, and the source of the third MOS transistor in the first conduction mode is effectively connected to the high supply terminal , And if the output signal is at the first logic level, the first continuity is 34 412858 (please read the precautions on the back before filling this page) This paper uses China National Standard (CNS) A4 specification U10X297. Centimeters) 41285 8 A8 B8 C8 D8 VI. The fifth MOS transistor in the form of a patent application will not be turned on ', thus causing the buffer to be critical. The point is a 20 * 2 ^^ ¥ whole circuit, which is connected in a integrated circuit. To a plurality of input buffer circuits to modify a threshold voltage level. At the threshold voltage level, an input voltage to the input buffer circuit will cause an output signal from the input buffer circuit to change from a first The logic device is transferred to a second logic device and includes: (a) a copy of the input buffer circuit having an input connected to a reference voltage; (b) an amplifier having a connection to the input A non-inverting terminal of the buffer output terminal of the copy of the buffer circuit and an amplifier output terminal coupled to the voltage adjusting terminal of the copy of the input buffer circuit and the voltage adjusting terminal of the input buffer circuit, and An inverting terminal; (c) an inverter gate representing the internal circuit and having an inverter input terminal coupled to an inverter output terminal and the inverting terminal of the amplifier Wherein a voltage level on the inverting terminal is set to a critical level inverter. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives *. (Please read the notes on the back ^ | ^ before filling out this page) 21. If you apply for a voltage adjustment circuit in the scope of patent application No. 20, the input buffer circuit Each input buffer circuit is coupled between a high supply voltage source and a low supply voltage source, and can receive the input signal and convert the input signal into an internal circuit in the integrated circuit The output signal accepted. 22. For example, the voltage adjustment circuit in the scope of patent application No. 21, where each input heater circuit includes: 35 This paper size applies to China National Standard (CNS) A4 specification (2Ϊ0 × 297 public director) A8 B8 CS D8 Printed by the Consumers' Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs. 6. Scope of Patent Application (a) — The input terminal is coupled to an input / output pad connected to an external circuit, and the external circuit will generate the input signal. (B) a buffer output terminal, which is coupled to the internal circuit to forward the output signal to the internal circuit; (c) a voltage adjustment terminal, which is coupled to a voltage adjustment device for repair Change a critical trip point of a buffer of the input signal, wherein the buffer critically determines an input voltage level of the input signal, and at the input voltage level the output signal will change from a first output logic level to A second output logic; (d) a high supply terminal, which is coupled to the high supply voltage source; (e) a low supply terminal, which is coupled to the low supply voltage source; (f) a first conduction mode A first MOS transistor having a gate connected to the input terminal, a drain connected to the buffer output terminal, and a source connected to the low supply terminal; (g) —of the second conduction mode A first MOS transistor having a gate connected to the input terminal, a drain connected to the buffer output terminal, and a source connected to the high supply terminal; (h) a A second MOS transistor having a gate connected to the input terminal, a drain connected to the buffer output terminal, and a source; (i) a second MOS transistor in the second conduction mode, wherein Has a gate connected to the input, A drain and a source connected to the output end of the buffer; G) a third MOS transistor in the first conduction mode, which has a 36 (please read the precautions on the back before filling this page) r Γ This paper size uses China National Standards (CNS) A4 (210X297 mm) printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs A8412858 ll___D8 _6. The scope of the patent application is connected to the gate of the voltage adjustment terminal, one to A drain of the source of the second MOS transistor of the first conduction mode, and a swim electrode connected to the low supply terminal; and (k) a third MOS transistor of one of the two conduction modes, which has a A gate connected to the voltage adjustment terminal, a drain connected to the source of the second MOS transistor in the second conduction mode, and a source connected to the high supply terminal. 23_ The voltage adjustment circuit of claim 21, wherein the input signal is selected from a group of voltage signals, and the group of voltage signals includes TTL signals, LVTTL signals, SSTL signals, and GTL signals. 24. The voltage adjusting circuit according to the scope of the patent application, further comprising a power saving device for reducing a voltage level of the high supply voltage source so as to minimize the power loss of the input buffer circuit. The power saving device Connected between the high supply voltage source and the high supply terminal. 25. The voltage adjusting circuit according to claim 24, wherein the power saving device includes a diode connected to the MOS transistor of the second conduction mode to pass a MOS voltage equal to one of the second conduction mode. A threshold voltage of the crystal to reduce the voltage level of the high supply voltage source. 26. For example, the voltage adjustment circuit of the scope of application for patent 24, wherein the power saving device is a voltage regulator, and the voltage regulator will reduce the voltage level of the high supply voltage source to a desired low voltage. 27. For example, the voltage adjustment circuit of the scope of application for patent No. 21 further includes an enabling device 'which is connected between the high supply voltage and the high supply terminal with 37 ^^ 1 ^^ 1 — ^ 1 -11 ^^ 1 ^^^ 1 1-^^^ 1 In ^^^ 1 ^^ 1 ^ ι_ · When (please read the precautions on the back before filling this page) This paper uses the Chinese national standard (CNS > A4 size) (210X297 mm) 412858 P8__D8 6. The scope of patent application and between the buffer output terminal and the low supply terminal, the input buffer circuit is enabled based on a logic level on an enable control terminal and 28. For example, the voltage adjustment circuit of the 21st patent application scope further includes a hysteresis device, which is coupled between the buffer output end, the high supply end and the low supply end to modify the buffer critical jump. The trip point is such that the critical trip point of the buffer for the input voltage level is changed from the first logic level to the second logic level is different from the input voltage level changed from the second logic level to the first logic level , Wherein the hysteresis device includes: (a) the fourth MOS transistor in the first conduction mode, It has a source coupled to the low supply end, a drain coupled to the buffer output, and a gate; (b) a fourth MOS transistor in the second conduction mode, which has a coupling To the source of the high supply, a drain coupled to the output of the buffer, and a gate; and Yin Ben, a shelling consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs * H ^^ 1 ^^ 1 ί---I ^^ 1 (please read down note t on the back before filling this page) (c) a hysteretic control gate with an input terminal coupled to the buffer output terminal, a first conduction mode and An output terminal of the gate of the fourth MOS transistor in the second conduction mode, and an inverting device for inverting the output signal at the output terminal of the buffer, wherein if the output signal is at the first Logic level, the fourth MOS transistor in the first conduction mode will be turned on, if the output signal is at a second logic level, the fourth MOS transistor in the second conduction mode will be turned on, when the input When the signal starts to change between the first logic level and the second logic level, the first The fourth MOS transistor in the conduction mode and the second conduction mode will modify the critical trip point of the buffer. 38 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 412858 A8 B8 C8 D8 The scope of patent application 29. For example, the voltage adjustment circuit of the scope of patent application 21 includes a hysteresis device to modify the critical trip point of the buffer, so that the critical threshold of the buffer is adjusted from the first voltage level to the input voltage level. Changing a logic level into the second logic level is different from changing from the second logic level to the first logic level, wherein the hysteresis device includes a fifth MOS transistor of the second conduction mode, A source coupled to the drain of the third MOS transistor in the second conduction mode, a drain coupled to the low supply terminal, and a gate coupled to the buffer output, wherein if The output signal is at the first logic level, the fifth MOS transistor in the second conduction mode will be turned on, and the source of the third MOS transistor in the second conduction mode is effectively coupled. To Low supply terminal, and if the output signal is different at the second logic level, the fifth MOS transistor of the second conduction will not form the conductive, thereby causing critical point in the buffer. (Please read the note t on the back before filling this page) T Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm)