TW432629B - Method for forming self-aligned contact opening by etching with gas containing fluorine - Google Patents

Method for forming self-aligned contact opening by etching with gas containing fluorine Download PDF

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TW432629B
TW432629B TW87110744A TW87110744A TW432629B TW 432629 B TW432629 B TW 432629B TW 87110744 A TW87110744 A TW 87110744A TW 87110744 A TW87110744 A TW 87110744A TW 432629 B TW432629 B TW 432629B
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Taiwan
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layer
contact opening
patent application
scope
insulating layer
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TW87110744A
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Chinese (zh)
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Bi-Lin Chen
Shiang-Yuan Jeng
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Vanguard Int Semiconduct Corp
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Abstract

In a process of forming a MOSFET, particularly a self-aligned contact opening of DRAM, the use of a silicon nitride gate side wall or silicon nitride gate cover is acceptable, in which the bitline contact opening is located between two adjacent wordlines, and each contact opening has a silicon nitride side wall. The etching of the contact opening requires the use of a reactive ion etching method having a very high selectivity to the oxide/nitride. In order to etch out a self-aligned contact opening with a width lower than 0.35 mu m in a high density DRAM, a special step must be used to prevent the occurrence of a polymer cross-linking on the remaining insulation material in the contact window. When the insulation layer penetrated by the contact opening is made of a silicate glass, e.g. a BPSG on a silicon oxide layer, this problem will be even more serious. The present invention discloses the use of an etching gas consisting of octafluoro cyclobutane, CH3F and a small amount of oxygen with a critical concentration to cleanly etch out a self-aligned contact opening without causing the silicon nitride sidewall insulator from being corroded. The added oxygen can prevent the polymer in the narrower region in the self-aligned contact from cross-linking.

Description

經濟部中央樣準局員工消費合作杜印繁 ;_Ζ4 326 2 9 ___ Β7 五、發明説明(i ) 一~'-- 本發明是有關於半導體元件之製程,且特別是有關 於在製造次微米金氧半場效應電晶體過程中蝕刻形成自 動對準接觸開口之方法。 習知技藝之說明: 積體電路晶片之製造包括在單晶矽晶圓表面形成半 導體元件。金氧半場效應電晶體之半導體元件先形成於 單晶基底晶圓之表面後,再形成一複晶矽閘極於基底上 ,作為離子怖植之罩幕,接著以控制電極所控制的離子 怖植法形成一自動對準於金氧半電晶體之閘電極的源極 以及汲極擴散區。 自動對準於複晶矽閘極之原理經過許多修改後,已 經發展出可改善元件性能以及穩定度製程,且特別是使 用邊牆結構的複晶矽閘極,其可使怖植離子沿邊牆之兩 側穿透基底表面,並且擴散於通道區之邊緣,可用以控 制短通道效應。這些金氧半場效應電晶體製程之優點已 經導致多種形式的高性能次微米尺寸的元件。而廣泛用 在次微米金氡半場效應電晶體技術的淡摻雜汲極(ldd) 結構則是此邊牆裁縫(taii〇ring)的重要例子。 複晶矽導體上所使用的絕緣邊牆以及覆蓋物也可以 用來形成自動對準於金氧半場效應主動元件的自動對準 接觸開口(SAC)’其步驟主要是利用反應性離子蝕刻法非 等向性蝕刻出垂直方向的牆狀開口,一般此開口均是貫 穿絕緣層’例如氧化矽或是不同的矽酸鹽玻璃。 自動對準接觸開口可利用不同的方式加以製造,一 --1------- —_______ ^ 本紙張尺賴(2_ 297/& ) - (請先W讀背面I注意事ΪΜ-再填究本頁) 訂 線- 經濟部中央標準扃貝工消費合作社印装 Γ 14 326 2 9 Λ? Β7 五、發明説明(2 ) 般均是沿複晶矽閘電極之邊緣形成一絕緣邊踏,此邊牆 在接觸開口以及該複晶矽層間作為絕緣的間隙物。如第1 圖所示’其顯示晶圓上之兩相鄰的金氧半場效應電晶體 的剖面圖。該圖式顯示一種傳統的動態隨機存取記憶胞 的設計(DASH cell),複晶矽閘電極18是作為DRAM之 字元線;源極/>及極12、14則是利用邊牆結構2 7以及習 知的LDD製程所完成。在後續的製程中,位元線12完 成後則可形成一連接及極14之儲存電容器。 然後’以習知的微影程序以及姓刻技術定義出字元 線以及邊牆27以及保護層24 ^其中,字元線包括有石夕 化鎢20以及一位在其上的薄氧化矽層22。邊牆27以及 上保護層24係由氮化矽所構成。接著,依序沉積一氧化 矽所構成之絕緣層26以及一矽酸鹽玻璃28例如磷發玻 璃或蝴碌石夕玻璃於晶圓10上。碎酸鹽玻璃廣28並以習 知的平坦化方法’例如化學機械研磨法,進行平坦化處 理。然後,以習知的微影程序形成具特定圖案之光阻層 30 ’其並在位元線接觸開口預定處形成一露出矽酸鹽玻 璃層28表面的開口 32 ’其中開口 32之範圍可大於在複 晶矽表面預定的接觸開口區域。 接著’以習知的反應性離子蝕刻法定義開口 32下所 裸露的絕緣層26、28,以形成—位元線接觸開口。反 應性離子蝕刻製程中的蝕刻氣體以及參數調整為在垂直 牆狀的開口蝕刻過程中對氧化矽有較高的蝕刻選擇性, 也就是氧化矽對氮化矽具有較高的蝕刻速率比。第2圖 本紙張尺度適用中國國家標準(CNS } A4現格(210X297公釐} (請先閲讀背面之注意事項再填寫本頁) ir 經濟部中央標隼局員工消費合作社印裝 r P432G 2 9 at _________Β7 五、發明説明(3 ) ~ 所示之開口 32是在對氮化矽邊牆27以及裸露的氮化矽 覆蓋物24之上層部分具有足夠高蝕刻速率選擇性的情 況下所形成。而標號36則是一在餘刻製程中所形成的聚 合物層。在不適當的氮化矽邊牆27以及裸露的氮化矽覆 蓋物24之上層部分的蝕刻速率選擇條件下,將會導致氮 化矽被侵蝕,並進而造成位元線以及字元線間發生短路 現象,如第3圖所示之裸露的字元線上角落34。 直到最近,蝕刻速率選擇性大於8:1的非等向性蝕 刻技術尚未出現。在目前的技術中,元件尺寸的特徵是 在0.25μιη的層面,其在接觸開口钱刻過程中要達到足夠 尚钱刻選擇性而又不會發生嚴重的敍刻邊緣效應則將會 相當困難’例如接觸開口底部之氧化物去除不完全將會 造成不可接受的接觸電阻值。Du Yinfan, Consumer Co-operation of the Central Bureau of Prospecting, Ministry of Economic Affairs; _Z4 326 2 9 ___ Β7 V. Description of the Invention (i) 1 ~ '-This invention relates to the manufacturing process of semiconductor components, and especially to the manufacture of sub-microns Method for automatically aligning contact openings by etching during metal-oxygen half-field effect transistors. Description of conventional techniques: The manufacture of integrated circuit wafers includes the formation of semiconductor elements on the surface of a single crystal silicon wafer. The semiconductor element of the metal-oxide half-field effect transistor is first formed on the surface of the single crystal substrate wafer, and then a compound silicon gate is formed on the substrate as a mask of ion implantation, and then the ion implantation is controlled by the control electrode. The implantation method forms a source and a drain diffusion region which are automatically aligned with the gate electrode of the metal-oxide semiconductor transistor. The principle of automatically aligning the polycrystalline silicon gates After many modifications, a process has been developed to improve component performance and stability. In particular, the polycrystalline silicon gates using a side wall structure can allow implanted ions along the side walls. Both sides penetrate the substrate surface and diffuse at the edges of the channel area, which can be used to control the short channel effect. The advantages of these metal-oxide half-field effect transistor processes have led to many forms of high-performance sub-micron-sized components. The lightly doped drain (ldd) structure, which is widely used in the sub-micron gold-alloy half-field effect transistor technology, is an important example of this side wall tailoring. Insulating side walls and coverings used on polycrystalline silicon conductors can also be used to form a self-aligning contact opening (SAC) that is automatically aligned with the metal-oxide half-field effect active element. Isotropic etching etches wall-like openings in the vertical direction. Generally, these openings penetrate through the insulation layer, such as silicon oxide or different silicate glass. The automatic alignment of the contact openings can be made in different ways, one --------------- _______ ^ This paper rule relies on (2_ 297 / &)-(Please first read the back I attention matter ΪΜ- Fill out this page again) Threading-Printed by the Central Standard of the Ministry of Economic Affairs, Coconut Consumer Cooperative Γ 14 326 2 9 Λ? Β7 V. Description of the Invention (2) Generally, an insulating edge is formed along the edge of the polycrystalline silicon gate electrode Step, this side wall acts as an insulating gap between the contact opening and the polycrystalline silicon layer. As shown in Fig. 1 ', it shows a cross-sectional view of two adjacent metal-oxide half-field effect transistors on a wafer. The figure shows a traditional DASH cell design. The compound silicon gate electrode 18 is used as the word line of the DRAM. 2 7 and the completion of the conventional LDD process. In the subsequent process, after the bit line 12 is completed, a storage capacitor connected to the pole 14 can be formed. Then 'define the character line, side wall 27 and protective layer 24 by the conventional lithography process and the last name engraving technique. ^ Among them, the character line includes Shixi tungsten 20 and a thin silicon oxide layer on it. twenty two. The side wall 27 and the upper protective layer 24 are made of silicon nitride. Next, an insulating layer 26 composed of silicon monoxide and a silicate glass 28 such as phosphorous glass or butterfly glass are sequentially deposited on the wafer 10. The shattered salt glass 28 is subjected to a planarization process by a conventional planarization method ', such as a chemical mechanical polishing method. Then, a conventional photolithography process is used to form a photoresist layer 30 ′ with a specific pattern, and an opening 32 ′ is formed to expose the surface of the silicate glass layer 28 at a predetermined position where the bit line contacts the opening. The range of the opening 32 may be greater than A predetermined contact opening area on the surface of the polycrystalline silicon. Next, the exposed insulating layers 26, 28 under the opening 32 are defined by a conventional reactive ion etching method to form a bit line contact opening. The etching gas and parameters in the reactive ion etching process are adjusted to have a higher etching selectivity for silicon oxide during the vertical wall-like opening etching process, that is, silicon oxide has a higher etching rate ratio to silicon nitride. Figure 2 This paper size applies the Chinese national standard (CNS) A4 (210X297 mm) (please read the notes on the back before filling out this page) ir Printed by the Consumers' Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs, P432G 2 9 at _________ Β7 V. Description of the Invention (3) ~ The opening 32 shown is formed under the condition that the silicon nitride sidewall 27 and the exposed silicon nitride cover 24 have a sufficiently high etching rate selectivity. The reference number 36 is a polymer layer formed in the remaining process. Under the conditions of inappropriate etching rate selection of the silicon nitride sidewall 27 and the exposed silicon nitride cover 24, nitrogen will be caused. Silicon silicon is eroded, which in turn causes short circuits between bit lines and word lines, as shown at corner 34 of the exposed word line in Figure 3. Until recently, the etch rate selectivity was greater than 8: 1 anisotropy. Etching etching technology has not yet appeared. In the current technology, the feature size of the element is at the level of 0.25 μηη, which must achieve sufficient selectivity without serious engraving edges during the contact opening engraving process. It should be quite difficult to 'the bottom of the opening, for example, a contact oxide will result in incomplete removal of the contact resistance unacceptable value.

Marks等人在美國專利5,423,945號中揭示降低墊聚 合物中的氟含量以及電漿中游離的氟含量,可減少聚合 物的分解。藉由在電漿中加入氟的清除劑例如矽或碳離 子,所形成的聚合物將成為富含碳且不易分解的聚合物 。在此例中,加入氟清除劑後,可使得氧化矽對氮化矽 的蝕刻選擇性達到1 5:1。 一般相信在含氟化碳餘刻劑的反應性離子蚀刻電衆 所形成的聚合物與蝕刻非等向性以及蝕刻速率選擇性有 關°例如在氧化矽的蝕刻過程中,所形成的聚合物會被 釋出的氧氣所快速分解;然而,在提供氬化矽作為塾層 後’氮化矽區域上之氧氣的濃度較低,且聚合物不易分 本纸張尺度適用中^^準(CNS )祕見21〇χ2_楚) '' (.銪先閱讀背面之注意事項再填寫本頁) 訂 線 P4 32 6 2 〇 Λ7 經濟部中央標準局貝工消费合作社印裝 五、發明説明(4 )解。 為了達到如第2圖所示的高蝕刻速率選擇性,必須 調整钱刻氣體以及反應性離子蝕刻參數以在氮化守層上 提供一相當穩定的聚合物。殘餘的聚合物36可在蝕刻操 作結束前先去除。不夠穩定的聚合物將會使氮化矽被侵 姓,而產生如第3圖所示的結構。 隨著元件密度的增加以及尺寸的縮小,在蝕刻定義 自動對準接觸開口時必須面臨新的難題。特別是〇 範圍的接觸開口尺寸,在以高氧化矽/氮化矽蝕刻選擇性 定義接觸開口時,要將接觸開口底部内的絕緣材料完全 清除將會出現困難。形成於氮化矽上的重聚合物將會干 擾β除接觸開口底部造成架橋反應使得開口縮小的絕緣 材料的進行,並進而使蝕刻終止。而接觸開口底部的殘 餘氧化物將會造成不可接受的接觸電阻值。 第4Α圖顯示一利用光阻層3〇所定義出來的位元線 接觸開口 40的剖面圖,除複晶矽字元線間的間隔縮小外 ,其他的電路佈局則與第1圖所示的結構類似。定義自 動對準接觸開口上部用的光阻40之開口寬度dl約為 0.25〜〇,3Hm。然而,在自動對準接觸開口底部的氮化 石夕邊牆27間的距離d2則約為^化山或更小。 第4Β圖顯示蝕刻貫穿氮化矽層28以及氧化矽層% 後,形成的接觸開口的剖面圖。當如第4Β圖所示般#刻 穿透氧化石夕層26時,因為氧切/破璃介面間的具有拓 樸不協調性,故裸露的氧切層26與中間保留部位湯 ---- 7 说尺度適用中國國家標準(CNS ) Λ4規格(——--------- (請先閲讀背面之注意事項再填寫本頁) 線! ·—I— B-^i 經济部中央標準局M-T消贤合竹社印紫 A7 _LE43Z£-2_9_________ 五、發明説明(5) 的聚合物形成速率將不相同。矽酸鹽玻璃28A是以比氧 化矽層16低10%的速率進行蝕刻。 接者’請參照第4 C圖’繼續前述的钱刻步驟,定義 出氮化矽覆蓋層24,氮化矽邊牆結構27,以及位在氮 化矽結構27上的聚合物層36。 最後’請參照第4D圖’隨著氮化石夕邊牆結構2 7間 的開口寬度縮小’氮化矽上的厚聚合物將會使開口產生 架橋且會阻止钱刻氣體進入其底下的氧化♦ /石夕酸鹽玻 璃38 ’導致自動對準接觸開口底部清除不完全,而使得 接觸開口因為殘留的材料38而產生不可接受的高接觸 電阻值^Marks et al., In U.S. Patent No. 5,423,945, disclose that reducing the fluorine content in the pad polymer and the free fluorine content in the plasma can reduce polymer decomposition. By adding a fluorine scavenger such as silicon or carbon ions to the plasma, the resulting polymer will become a carbon-rich and non-decomposable polymer. In this example, after the addition of a fluorine scavenger, the etching selectivity of silicon oxide to silicon nitride can reach 15: 1. It is generally believed that the polymers formed by reactive ion etching of carbon fluoride containing etching agents are related to the anisotropy of the etching and the selectivity of the etching rate. For example, during the etching of silicon oxide, the polymer formed will The released oxygen is rapidly decomposed; however, after the silicon argon layer is provided as the hafnium layer, the concentration of oxygen on the silicon nitride region is low, and the polymer is not easy to be divided into paper standards. (CNS) See my secret 21〇χ2_ Chu) '' (. 铕 Read the notes on the back before filling in this page) Thread P4 32 6 2 〇Λ7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (4) solution. In order to achieve high etch rate selectivity as shown in Figure 2, the etch gas and reactive ion etch parameters must be adjusted to provide a fairly stable polymer on the nitrided layer. Residual polymer 36 may be removed before the etching operation is completed. A less stable polymer will invade the silicon nitride, resulting in the structure shown in Figure 3. As component density increases and size shrinks, new challenges must be faced in the definition of etching to automatically align contact openings. Especially for the contact opening size in the range of 0, it will be difficult to completely remove the insulating material in the bottom of the contact opening when defining the contact opening with a high silicon oxide / silicon nitride etching selectivity. The heavy polymer formed on the silicon nitride will interfere with β except the contact with the bottom of the opening, which causes a bridging reaction to cause the opening of the insulating material to shrink, and further terminates the etching. Residual oxides in contact with the bottom of the opening will cause unacceptable contact resistance values. FIG. 4A shows a cross-sectional view of the bit line contact opening 40 defined by the photoresist layer 30. Except for the reduction in the space between the polycrystalline silicon word lines, the other circuit layout is the same as that shown in FIG. Structure is similar. The opening width dl of the photoresist 40 for automatically aligning the upper portion of the contact opening is defined to be about 0.25 to 0.3 Hm. However, the distance d2 between the nitrided stone side walls 27 at the bottom of the auto-alignment contact opening is about 10,000 or less. FIG. 4B shows a cross-sectional view of the contact opening formed after etching through the silicon nitride layer 28 and the silicon oxide layer%. When the #etched layer penetrates the oxidized stone layer 26 as shown in FIG. 4B, because of the inconsistency between the oxygen-cutting / glass-breaking interface, the exposed oxygen-cutting layer 26 and the soup in the middle-reserved area --- -7 The standard is applicable to Chinese National Standard (CNS) Λ4 specifications (——--------- (Please read the precautions on the back before filling this page) Line! · —I— B- ^ i Ministry of Economic Affairs Central Standards Bureau MT Xiaoxian Hezhu Society Printing Purple A7 _LE43Z £ -2_9 _________ V. Description of the invention (5) The polymer formation rate will be different. The silicate glass 28A is performed at a rate 10% lower than the silicon oxide layer 16 Etching. “Please refer to FIG. 4C” to continue the aforementioned step of money engraving, and define the silicon nitride cover layer 24, the silicon nitride sidewall structure 27, and the polymer layer 36 on the silicon nitride structure 27. Finally, please refer to Figure 4D. As the width of the openings between the side walls of the nitrided stone walls decreases, the thick polymer on the silicon nitride will bridge the openings and prevent the engraved gas from oxidizing underneath it. ♦ / Shi Xiate glass 38 'caused the automatic alignment of the bottom of the contact opening was not completely removed, which caused the contact opening due to Unacceptably high contact resistance for residual material 38 ^

Dunfield在美國專利第4,793,897號中揭示一種使 用含氟及乳氣之钱刻混含氣體電裝,使得在選擇性姓刻 氮化矽過程中對氧化矽具有高選擇性^蝕刻混合氣體中 含有三氟化氮、四氟化矽、以及氧氣。三氟化氮是氮化 矽的主要蝕刻氣體’而氧氣則會與四氟化矽中的矽結合 以選擇性的在氧化矽的底下形成另一氧化矽層,以增加 蝕刻氣體對氡化層的選擇性。Dunfield in U.S. Patent No. 4,793,897 discloses a method for engraving mixed gas containing fluorine and milk gas, so that it has high selectivity to silicon oxide during selective silicon nitride etching. The etching mixed gas contains three metals. Nitrogen fluoride, silicon tetrafluoride, and oxygen. Nitrogen trifluoride is the main etching gas of silicon nitride, and oxygen will combine with silicon in silicon tetrafluoride to selectively form another silicon oxide layer under the silicon oxide to increase the etching gas against the halide layer. Of selectivity.

Thomquist在美國專利第4,568 41〇號中揭示一種包 括有二氟化氮之蝕刻氣體以在含氧化矽情況下蝕刻氮化 矽的方法。 發明概要: 本發明的特徵之一是提供一種改良式形成積體電路 之自動對準接觸開口的方法。 本紙張尺度適用中國國家標牟(CNS ) A4現格(2]〇χ297公瘦) m I n |( il- n - -1 . - I I I I-----n- T m n In HI I K -T {谇先閱讀背面之注意事項再填蹲本頁) 第87110744號 專利說明書修正頁Thomquist, U.S. Patent No. 4,568,410, discloses a method including an etching gas containing nitrogen difluoride to etch silicon nitride in the presence of silicon oxide. SUMMARY OF THE INVENTION One of the features of the present invention is to provide an improved method for automatically aligning contact openings in a integrated circuit. This paper scale is applicable to China National Standards (CNS) A4 (2) 〇297297 thin) m I n | (il- n--1.-III I ----- n- T mn In HI IK- T (Please read the precautions on the back before filling this page) No. 87110744 Revised Patent Specification

U & ~ A7 B7 修正日期:90/〇2/08 文;> 經濟部智慧財產局員工消費合作社印製 五、發明說明(6 ) 本發明之另一特徵是提供一種利用反應性離子蝕刻 法製作具有氮化矽邊牆之自動對準接觸開口的方法,其 中該些開口間的寬度係低於〇. 15μιη。 本發明之另一特徵是提供一種利两反應性離子蝕刻 法在DRAM積體電路中的相鄰字元線間形成自動對準接觸 開口的方法,其中該字元線具有氮化矽覆蓋層以及氮化 矽邊牆’且該些開口間的寬度係低於〇 15叩。 本發明之另一特徵是提供一種利用反應性離子蝕刻 法以形成自動對準於閘極柱之開口且可減少閘極-接觸 開口間發生短路的方法。 上述的該些特徵中’均是利用八氟環丁烷、氟化甲 烷、氧氣、以及氬氣所構成之攜帶氣體所構成之蝕刻氣 體元成自動對準接觸開口的姓刻,其中所加入的少量氧 乳適用以降低聚合物掉入寬度較窄的開口内,以防止擠 壓變形。此外,少量的氧氣也被發現可改善蝕刻停止於 氮化石夕介面的能力’並進而減少閘極__對〜位元線間發生 接觸短路的危機。氧氣流速在此關鍵的製程中必須限制 在一較小的範圍内。 圖式之簡單說明: 為使本發明之優點以及特徵更明顯易僅,玆將配合 較佳實施例以及相關圖式詳細說明如下。 第1〜3圖顯示習知一種DRAM的自動對準接觸開口 之剖面製程。 第4A〜4D圖顯示習知一種製作線寬為深次微米的 -ϋ I n ϋ - (請先®讀背面之注意事項再填寫本頁) . 線 r4 32 6 ? 9 A7 B7 經"'-部中央標率局貝工消费合作社印來 五、發明説明(7 ) DRAM胞的自動對準接觸開口的剖面製程。 第5A〜5F圖顯示根據本發明之製程以製作線寬為 深次微米的dram胞的自動對準胞的實施例之剖面製程 〇 較佳實施例: 在本發明的較佳實施例中,DRAM胞結構具有自動 對準於兩相鄰字元線之接觸位元線,其中接觸開口之寬 度少於I50nm ,而相鄰字元線間的間隔則約為3〇〇nm。 首先,請參照第5A圖,提供一矽晶圓1〇,其次形 成一厚度約50〜i50nm的掺雜過的複晶矽層18於閘極 氧化層16上。其中,摻雜過的複晶矽層18可為組合物 形式,其可額外含有一由金屬矽化物所構成之導電層2〇 ,例如矽化鎢(WSix)。此複晶矽層18可利用眾所皆知的 化學氣相沉積法形成’然後再以離子怖植法將雜質怖植 進沉積的複晶矽層内,而形成一摻雜過的複晶矽層18 ^ 然後,利用化學氣相沉積法再沉積一厚度約2〇〜5〇nm 的氧化矽層22於導電層2〇上,其中氧化矽層22例如可 為四乙氧基矽層。接著,再以習知的矽甲烷以及氨氣作 為前驅物,利用化學氣相沉積法形成一厚度約150〜 250nm的氮化矽層24於氧化矽層22上。 然後,先形成一光阻圖案25於氮化矽層24上,接 著再以光阻圖案為蝕刻罩幕,利用非等向性離子蝕刻法 定義出金氧半場效應電晶體之閘極柱以及字元線^目前 ,次微米DRAM的字元線間的間隔一般是介於〇 2〜 請 先 聞 背 之1 注U & ~ A7 B7 Revision date: 90 / 〇2 / 08 Text; > Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) Another feature of the present invention is to provide a method using reactive ion etching 15μιη。 Method of making automatic alignment contact openings with silicon nitride sidewalls, wherein the width between the openings is less than 0.15μιη. Another feature of the present invention is to provide a method for forming an automatic alignment contact opening between adjacent word lines in a DRAM integrated circuit by a two-reactive ion etching method, wherein the word line has a silicon nitride cover layer and Silicon nitride sidewalls' and the width between these openings is less than 0.15 mm. Another feature of the present invention is to provide a method using a reactive ion etching method to form an opening that is automatically aligned with the gate post and can reduce the occurrence of short circuits between the gate and the contact opening. Among the above-mentioned features, the etching gas composed of a carrier gas composed of octafluorocyclobutane, fluorinated methane, oxygen, and argon is used to automatically align the last name of the contact opening. A small amount of oxygen milk is suitable to reduce the polymer falling into narrow openings to prevent crush deformation. In addition, a small amount of oxygen has also been found to improve the ability of the etch to stop at the nitride nitride interface ’and thereby reduce the risk of contact shorts between the gates and bit lines. The oxygen flow rate must be limited to a small range in this critical process. Brief description of the drawings: In order to make the advantages and features of the present invention more obvious, the preferred embodiments and related drawings are described in detail below. Figures 1 to 3 show a cross-sectional process of a conventional DRAM for automatically aligning contact openings. Figures 4A ~ 4D show a conventional method for making a line with a depth of sub-micron -ϋ I n ϋ-(Please read the notes on the back before filling this page). Line r4 32 6? 9 A7 B7 Warp " ' -Printed by the Ministry of Standards and Technology Bureau, Shellfish Consumer Cooperative, V. Invention Description (7) Cross-section process of automatic alignment of DRAM cells with contact openings. Figures 5A to 5F show a cross-sectional process of an embodiment of an automatic alignment cell for making a dram cell with a line width of a deep sub-micron according to the manufacturing process of the present invention. The cell structure has contact bit lines automatically aligned with two adjacent word lines, wherein the width of the contact opening is less than I50 nm, and the interval between adjacent word lines is about 300 nm. First, referring to FIG. 5A, a silicon wafer 10 is provided, and a doped polycrystalline silicon layer 18 having a thickness of about 50 to 50 nm is formed on the gate oxide layer 16. Wherein, the doped polycrystalline silicon layer 18 may be in the form of a composition, which may additionally include a conductive layer 20 composed of a metal silicide, such as tungsten silicide (WSix). The polycrystalline silicon layer 18 can be formed by a well-known chemical vapor deposition method, and then an impurity implantation method is used to implant impurities into the deposited polycrystalline silicon layer to form a doped polycrystalline silicon layer. Layer 18 ^ Then, a silicon oxide layer 22 with a thickness of about 20˜50 nm is deposited on the conductive layer 20 by using a chemical vapor deposition method. The silicon oxide layer 22 may be, for example, a tetraethoxy silicon layer. Next, a conventional silicon methane and ammonia gas are used as precursors, and a silicon nitride layer 24 having a thickness of about 150 to 250 nm is formed on the silicon oxide layer 22 by a chemical vapor deposition method. Then, a photoresist pattern 25 is formed on the silicon nitride layer 24, and then the photoresist pattern is used as an etching mask, and the gate pillars and words of the gold-oxygen half field effect transistor are defined by anisotropic ion etching. Element line ^ At present, the space between the character lines of sub-micron DRAM is generally between 0 ~ 2.

I 養 訂 10 本紙張尺度適用中國國家標準(CNS ) 公餐 A7 B7 »432629 五、發明説明(8) 0.3μιη 間。 其次’請參照第5 Β圖,去除光阻圖案2 5後, 獲得一利用反應性離子姓刻法所形成字元線5 〇。 利用能量約20〜40KeV的砷離子以1〇12 1014atoms/cm2的劑量進行離子怖植,形成一淡雜質推雜 的汲極區15 ^ 然後’請參照第5C圖,字元線結構5〇侧壁之氮化 碎邊牆27可先利用化學氣相沉積法形成一厚度相當於 想要的邊牆厚度之氬化矽層適順性地覆蓋於第5b圖所 示之結構表面,然後再以反應性離子蝕刻法回蝕刻去除 多餘的氮化矽層,而在字元線結構50側壁形成一氮化矽 邊牆27。其中為降低介面壓力,可在沉積氮化矽層前先 沉積一薄墊氧化層(未顯示)。邊牆27的功能不只是用來 定義淡摻雜源極(LDD)結構,其也可被用來區分自動對 準接觸開口以及複晶矽閘極和LDD區。在目前的DRam 設計尺寸中,氮化矽邊牆27的厚度约為5〇〜1〇〇nm。 邊牆27形成後,利用能量約20〜40KeV的珅離子 以1014〜l〇i6atoms/cm2的劑量對晶圓進行離子怖植,形 成一較深且濃度較高的濃雜質摻雜的汲極區12、M, 完成帶有字元線50之金氧半場效應電晶體。 接著’請參照第5D圖,形成一厚度約goo〜1 〇〇〇 A 之絕緣層29於晶圓1〇上,其可由如圖所示般由低壓化 學氣相沉積的氧化矽所構成之下絕緣層26以及化學氣 相沉積的磷矽玻璃或者硼磷矽玻璃所構成之上絕緣層28 ^氏張尺度適祕(训x297: {諳先閱讀背面之注意事項再填寫本頁)I fix 10 This paper size applies to Chinese National Standards (CNS) Public meals A7 B7 »432629 V. Description of the invention (8) 0.3μm. Secondly, please refer to FIG. 5B. After removing the photoresist pattern 25, a character line 50 formed by the reactive ion surname engraving method is obtained. Ion implantation was performed using arsenic ions with an energy of about 20 to 40 KeV at a dose of 1012 1014 atoms / cm2 to form a lightly doped dopant region 15 ^ and then 'Please refer to FIG. 5C, word line structure 50 side The nitrided and broken side wall 27 of the wall can first be formed by chemical vapor deposition to form a silicon argon layer with a thickness corresponding to the thickness of the desired side wall to cover the structure surface shown in FIG. 5b smoothly, and then use Reactive ion etching etch-back removes the excess silicon nitride layer, and a silicon nitride sidewall 27 is formed on the sidewall of the word line structure 50. To reduce the interface pressure, a thin pad oxide layer (not shown) can be deposited before the silicon nitride layer is deposited. The function of the side wall 27 is not only used to define a lightly doped source (LDD) structure, but it can also be used to distinguish between auto-aligned contact openings and polycrystalline silicon gates and LDD regions. In the current DRam design size, the thickness of the silicon nitride sidewall 27 is about 50˜100 nm. After the side wall 27 is formed, the wafer is ion-implanted at a dose of 1014 to 10i6 atoms / cm2 with thorium ions having an energy of about 20 to 40 KeV to form a deeper and higher concentration impurity-doped drain region. 12, M, complete the metal-oxygen half field effect transistor with word line 50. Next, please refer to FIG. 5D, and form an insulating layer 29 on the wafer 10 with a thickness of about goo ~ 1000A, which may be composed of silicon oxide formed by low-pressure chemical vapor deposition as shown in the figure. Insulation layer 26 and chemical vapor deposition of phosphosilicate glass or borophosphosilicate glass on top of the insulation layer 28 ^ Zhang Zhang size appropriate (training x297: {: read the precautions on the back before filling in this page)

、1T 經Μ部中决標準局負工消費合竹ίι印來 -------------------.____ 經漭部中决標??-局Μ Λ消贽合竹杜印裝 Γρ^ / __14 326 2 9 B7__ 五、發明説明(9) 所構成;或者絕緣層29整層均由氧化矽所構成。利用化 學氣相沉積法所形成的絕緣薄膜已在習知技藝中被廣泛 應用。 然後,在絕緣層28沉積後,可重複性地對絕緣層28 施一平坦化處理例如化學機械研磨法,以去除拓樸性的 特徵。然後,再以習知的微影程序形成一具特定圖案之 光阻層30於平坦化的絕緣層上,其中並在預定形成接觸 開口處形成有一露出絕緣層28之開口 40。接著,將晶 圓放置在高密度電漿蚀刻機内之反應室中(HDp etcher ;、 1T It was printed by the offenders of the Ministry of Standards of the Ministry of Standards and Consumption. -------------------.____ The final prize of the Ministry of Economics of the Ministry of Standards ??-Bureau Μ Λ Elimination of combined bamboo and printed seals Γρ ^ / __14 326 2 9 B7__ V. Composition of the invention (9); or the entire insulating layer 29 is composed of silicon oxide. Insulation films formed by chemical vapor deposition have been widely used in the art. Then, after the insulating layer 28 is deposited, the insulating layer 28 may be repeatedly subjected to a flattening treatment such as a chemical mechanical polishing method to remove the topological characteristics. Then, a conventional photolithography process is used to form a photoresist layer 30 with a specific pattern on the planarized insulating layer, and an opening 40 exposing the insulating layer 28 is formed at a predetermined contact opening. Next, the crystal circle is placed in a reaction chamber (HDp etcher) in a high-density plasma etching machine;

Appied Materials,Inc· of Santa Clara CA)。 將反應室内的壓力抽到約l〇-4 torr或者更低時便可 開始進行姓刻步驟。蝕刻用的蝕刻氣體是由流速約為1〇 〜15 SCCM之該八氟環丁院’流速約為5〜15 SCCM之 CHJ,以及流速約為!〜3 SCCM之氧氣以及流速約5〇 100 SCCM之攜帶氣體一氬氣所構成,且此高密度電 毁敍刻機之能量密度約4.6瓦/cm2。在此反應條件下, 可形成垂直邊牆且氧化物比氮化物之蝕刻比約為2〇:ι。 當使用八氟環丁烷以及CH3F但無氧氣的條件下, 反應性離子蝕刻法對氡化矽/氬化矽的蝕刻選擇性約為 3〇:1。然而’因為接觸開口的小尺寸將會使殘餘的絕緣 材料保留在開口内’故為完全的清除此開口,蝕刻氣體 中將至少需要1 SCCM的氧氣。換句話說,若蝕刻條件 與上述之說明相同’但氧氣流速超過3 SCCM時,保持 在不夠穩定的狀態的聚合物將會有害的侵蝕氬化矽覆蓋 本紙張尺度逼用中) - —--- (請先閱讀背面之注意事項再填寫本頁;jAppied Materials, Inc. of Santa Clara CA). When the pressure in the reaction chamber is reduced to about 10-4 torr or lower, the last name engraving step can be started. The etching gas used for etching is composed of the octafluorocyclobutane courtyard with a flow rate of about 10 to 15 SCCM and a flow rate of about 5 to 15 SCCM and CHJ, and the flow rate is about! It consists of ~ 3 SCCM of oxygen and a carrier gas of about 100 SCCM-argon, and the energy density of this high-density destroyer is about 4.6 W / cm2. Under this reaction condition, a vertical sidewall can be formed and the etching ratio of the oxide to the nitride is about 20: ι. When octafluorocyclobutane and CH3F are used without oxygen, the etching selectivity of the reactive ion etching method to the silicon trioxide / silicon argon is about 30: 1. However, ‘because the small size of the contact opening will leave residual insulating material in the opening’, in order to completely remove this opening, at least 1 SCCM of oxygen will be required in the etching gas. In other words, if the etching conditions are the same as the above description, but when the oxygen flow rate exceeds 3 SCCM, the polymer maintained in an insufficiently stable state will deleteriously erode the silicon argon covering the paper. -(Please read the notes on the back before filling this page; j

r 32 6 2 Q A7 ^ B7 一 — —~ ~ '— 五、發明説明(i〇) 層/邊牆結構24/27。因此,為了使蝕刻的結構為想要的 結果,小心地控制氧氣流速將是相當必要的。 第5E圖顯示在經過反應性離子蝕刻步驟後,接觸開 口的型態剖面圖。接著,利用已知光阻拔除方法,去除 殘餘的聚合物36以及殘餘的光阻30。 最後’請參照第5 F圖,利用習知的插检製程,形成 一金屬插栓42於自動對準接觸開口 40内,其中插栓42 例如可為多晶矽插栓或金屬插栓。除上述之製程外,本 發明更可繼續其他額外用以形成DRAM胞的製程,其包 括在絕緣層28以及金屬插栓42上形成位元線,以及在 接觸主動區14上形成儲存電容器(未顯示 本發明已利用實施例配合相關圖式將本發明的特徵 以及内容詳細說明如上’然在此所提及的實施例僅是用 以方便說明起見’其並非用以限定本發明。因此任何熟 習此技藝者’在不脫離本發明之精神和範圍内,所作的 各種更動與潤飾,均落在本發明的專利範圍内。 經消部中央標準局員τ,消費合作社印絜 3 ;適 度 尺一说 β |本 準 摞 家 國 國r 32 6 2 Q A7 ^ B7 I — — ~ ~ '— V. Description of the invention (i〇) Layer / side wall structure 24/27. Therefore, to make the etched structure the desired result, careful control of the oxygen flow rate will be quite necessary. Fig. 5E shows a sectional view of the contact opening after the reactive ion etching step. Next, the residual photoresist 36 and the residual photoresist 30 are removed by a known photoresist removal method. Finally, referring to FIG. 5F, a conventional plug inspection process is used to form a metal plug 42 in the automatic alignment contact opening 40. The plug 42 can be, for example, a polycrystalline silicon plug or a metal plug. In addition to the above processes, the present invention can continue other additional processes for forming DRAM cells, which include forming bit lines on the insulating layer 28 and the metal plug 42 and forming a storage capacitor (not shown) on the active contact area 14 It is shown that the present invention has used the embodiments in conjunction with the related drawings to describe the features and contents of the present invention in detail. 'The embodiments mentioned herein are for convenience only' and are not intended to limit the present invention. Therefore, any Those skilled in the art ', without departing from the spirit and scope of the present invention, make various modifications and retouches that fall within the patent scope of the present invention. Member of the Central Standards Bureau of the Ministry of Economic Affairs τ, Consumer Cooperative Seal 3; Moderate Ruler One Say Beta | Ben Jun

Ns 規 釐 公 7 9 2Ns Gauge 7 9 2

Claims (1)

第871 10744號申請專利範圍修正 _ B8Amendment of Patent Application No. 871 10744 _ B8 申請專利範圍 修正日期188#2.#9 EI修止 補充 •一種形成自動對準於接近金氧半場效應電晶體閘 極半導體單元之接觸窗的方法,其步驟包括: (a) 提供一具有垂直牆狀的閘極柱以及一主動半導體 單元之矽晶圓,其中該閘極柱具有一絕緣覆蓋層、一邊 牆結構,且該主動半導體單元係位在接近該邊牆處; (b) 沉積一第一絕緣層於該矽晶圓上; (c) 沉積一第二絕緣層該矽晶圓上; (d) 對該第二絕緣層施一平坦化處理; (e) 沉積一光阻層於該第二絕緣層上; (f) 利用該光阻層定義出一接觸開口; (g) 利罔反應性離子钱刻法以及含有八氟環丁烧、 亂化甲烷(CHJ)以及氧氣混合物以及氬氣作為攜帶氣體 的輻射頻率電漿蝕刻該第二絕緣層以及該第一絕緣層, 形成一接觸開口: (h) 去除殘餘的聚合物; ⑴去除該光阻層;以及 ⑴沉積一導電材料層於該接觸開口内,而後形成一 自我對準接觸開口。 2·如申請專利範圍第1項所述之方法,其中該第一 絕緣層是氧化石夕。 3.如申請專利範圍第1項所述之方法,其中該第二 邑緣層疋選自氧化石夕、鱗玻璃以及硼鱗石夕玻璃所構成之 族群。 4.如申請專利範圍第1項所述之方法,其中該絕 nllllul· — — ----I--^訂!—-線--- f请先閱謂背面之注意事碩再填寫本頁) 經濟部智慧財產局員工消費合作社印製 \4 I A8Patent application scope revision date 188 # 2. # 9 EI repair supplement • A method of forming a contact window automatically aligned to a metal-oxide semiconductor field-effect transistor gate semiconductor unit, the steps include: (a) providing a vertical A wall-shaped gate post and a silicon wafer of an active semiconductor unit, wherein the gate post has an insulating cover layer and a side wall structure, and the active semiconductor unit is located near the side wall; (b) depositing a A first insulating layer on the silicon wafer; (c) depositing a second insulating layer on the silicon wafer; (d) applying a planarization treatment to the second insulating layer; (e) depositing a photoresist layer on On the second insulating layer; (f) using the photoresist layer to define a contact opening; (g) a reactive ion engraving method and a mixture containing octafluorocyclobutane, chaotic methane (CHJ) and oxygen, and Argon is used as a carrier frequency plasma to etch the second insulating layer and the first insulating layer to form a contact opening: (h) removing residual polymer; (i) removing the photoresist layer; and (ii) depositing a conductive material. Layer inside the contact opening Then forming a self-aligned contact opening. 2. The method according to item 1 of the scope of patent application, wherein the first insulating layer is oxidized stone. 3. The method according to item 1 of the scope of patent application, wherein the second euphemum layer is selected from the group consisting of oxidized stone, glass, and boron glass. 4. The method as described in item 1 of the scope of patent application, wherein the absolute nllllul · — — ---- I-^ subscribe! —- 线 --- f Please read the note on the back before filling in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs \ 4 I A8 a IT h. 石夕 層 m? 6 2 9 六、申請專利範圍 (d)形成一具特定圖案之第一 〜吊 光阻層於該第—" 矽層上以定義出彼此相鄰的字元線; 11介 ⑷依序非等向性#刻該[氮切層,該 以及該導電層,然後形成彼此相_字元線; (f) 佈植第一劑量的雜質原子; (g) 去除該第一光阻層; ⑻沉積—第二氮切層於上述步驟所形成之結相 表面; (!)非等向性蝕刻該第二氮化石夕層,並且沿該字元鱗 之邊緣形成一邊牆; (j)佈植第二劑量的雜質原子,而後形成一半導體單 ---------------- Λ---- -~\靖先閱讀背面之没意事項再填寫本I) 元 上 (k) 沉積一絕緣層於該矽晶圓上: (l) 對戎絕緣層施一平坦化處理; (m) 形成一具特定圖案之第二光阻層於該絕緣肩 訂· -線. 元線間定| 經濟部智慧財產局員工消費合作社印製 (η)利用該第二光阻圖案在兩相鄰的 出一位元線接觸開口; (〇)利用反應性離子蝕刻法以及含有八氟環丁烷 氟化甲烷(CH3F)以及氧氣混合物以及氬氣作為攜帶氣胥 的輻射頻率電漿蝕刻該第二絕緣層以及該第一絕緣層, 形成一接觸開口; (P)去除殘餘的聚合物; (q)去除該光阻層; 16 本紙張尺度適用中國园家標4MCNSM4規格⑵0,297公爱) AS B8 C8 D8 P432629 ▽、申請專利範圍 (r)沉積—導電材料層於該接觸開Π内,而後形成一 自我對準接觸開口; (S)形成一位元線於該位元線接觸開口上;以及 ⑴於该矽晶圓上形成儲存電容器。 如申請專利範圍第12項所述之方法,其十該第 一絕緣層是氧化矽。 Μ.如申請專利範圍第Π項所述之方法,其中該第 二絕緣層是選自氧化矽、磷玻璃以及硼磷矽玻璃所構成 之族群。 15·如申請專利範圍第12項所述之方法,其中該接 觸開口之寬度約為0.1〜〇.4|im。 16. 如申請專利範圍第ι2項所述之方法,其中該邊 牆結構之厚度約為50〜i〇〇nm。 17. 如申請專利範圍第12項所述之方法,其中該兩 相鄰的字元線間的距離約為0.18〜0.35μπι。 18_如申請專利範圍第a項所述之方法,其中該八 氟環丁烷之流速約為1〇〜15 SCCM,該氯仿之流速約為 5〜15 SCCM,而該氧氣之流速約為1〜3 SCCM。 19. 如申請專利範圍第12項所述之方法,其中該氬 氣在反應室内之總壓力被調整於2〜mtorr。 20, 如申請專利範圍第12項所述之方法’其中該導 電材料是鎢插塞。 17 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -mlltlmll— V .^ ·1111111 ·ίιιΙΙ1 {請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製a IT h. Shi Xi layer m? 6 2 9 VI. The scope of patent application (d) forms a first ~ hanging photoresist layer with a specific pattern on the "—" silicon layer to define adjacent words Element line; 11 介 ⑷Order non-isotropicity # Carved the [nitrogen cut layer, the and the conductive layer, and then formed a phase line with each other _ character line; (f) implanted the first dose of impurity atoms; (g) Remove the first photoresist layer; ⑻ deposition-a second nitrogen cutting layer on the junction surface formed in the above steps; (!) Anisotropically etch the second nitride layer, and along the edge of the character scale Forming a side wall; (j) implanting a second dose of impurity atoms, and then forming a semiconductor single ---------------- Λ -----~ Unintentionally fill in this I) (k) Deposit an insulating layer on the silicon wafer: (l) Apply a planarization treatment to the insulating layer; (m) Form a second photoresist with a specific pattern Layer on this insulation shoulder-line. Yuan line is set | Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (η) Use this second photoresist pattern to make two Yuan line contact openings (0) etching the second insulating layer and the first insulating layer using a reactive ion etching method and plasma containing octafluorocyclobutanefluorinated methane (CH3F), an oxygen mixture, and argon as a radiation frequency plasma carrying a radon, Form a contact opening; (P) remove the residual polymer; (q) remove the photoresist layer; 16 this paper size is applicable to the Chinese garden house standard 4MCNSM4 specification ⑵0,297 public love) AS B8 C8 D8 P432629 ▽, scope of patent application (r) deposition-a layer of conductive material is formed in the contact opening, and then a self-aligned contact opening is formed; (S) a bit line is formed on the bit line contact opening; and a silicon wafer is formed on the silicon wafer Storage capacitor. According to the method described in claim 12 of the patent application scope, ten of the first insulating layers are silicon oxide. M. The method as described in item Π of the patent application scope, wherein the second insulating layer is selected from the group consisting of silicon oxide, phosphor glass, and borophosphosilicate glass. 15. The method according to item 12 of the scope of application for a patent, wherein the width of the contact opening is about 0.1 ~ 0.4 | im. 16. The method as described in item 2 of the scope of patent application, wherein the thickness of the side wall structure is about 50 to 100 nm. 17. The method according to item 12 of the scope of patent application, wherein a distance between the two adjacent character lines is about 0.18 to 0.35 μm. 18_ The method described in item a of the scope of the patent application, wherein the flow rate of the octafluorocyclobutane is about 10 to 15 SCCM, the flow rate of the chloroform is about 5 to 15 SCCM, and the flow rate of the oxygen is about 1 ~ 3 SCCM. 19. The method according to item 12 of the scope of patent application, wherein the total pressure of the argon gas in the reaction chamber is adjusted to 2 to mtorr. 20. The method according to item 12 of the scope of patent application, wherein the conductive material is a tungsten plug. 17 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -mlltlmll— V. ^ · 1111111 · ίιΙΙ1 {Please read the precautions on the back before filling out this page} Employee Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Printed by a cooperative
TW87110744A 1998-07-02 1998-07-02 Method for forming self-aligned contact opening by etching with gas containing fluorine TW432629B (en)

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