TW432629B - Method for forming self-aligned contact opening by etching with gas containing fluorine - Google Patents

Abstract

In a process of forming a MOSFET, particularly a self-aligned contact opening of DRAM, the use of a silicon nitride gate side wall or silicon nitride gate cover is acceptable, in which the bitline contact opening is located between two adjacent wordlines, and each contact opening has a silicon nitride side wall. The etching of the contact opening requires the use of a reactive ion etching method having a very high selectivity to the oxide/nitride. In order to etch out a self-aligned contact opening with a width lower than 0.35 mu m in a high density DRAM, a special step must be used to prevent the occurrence of a polymer cross-linking on the remaining insulation material in the contact window. When the insulation layer penetrated by the contact opening is made of a silicate glass, e.g. a BPSG on a silicon oxide layer, this problem will be even more serious. The present invention discloses the use of an etching gas consisting of octafluoro cyclobutane, CH3F and a small amount of oxygen with a critical concentration to cleanly etch out a self-aligned contact opening without causing the silicon nitride sidewall insulator from being corroded. The added oxygen can prevent the polymer in the narrower region in the self-aligned contact from cross-linking.

Description

Du Yinfan, Consumer Co-operation of the Central Bureau of Prospecting, Ministry of Economic Affairs; _Z4 326 2 9 ___ Β7 V. Description of the Invention (i) 1 ~ '-This invention relates to the manufacturing process of semiconductor components, and especially to the manufacture of sub-microns Method for automatically aligning contact openings by etching during metal-oxygen half-field effect transistors. Description of conventional techniques: The manufacture of integrated circuit wafers includes the formation of semiconductor elements on the surface of a single crystal silicon wafer. The semiconductor element of the metal-oxide half-field effect transistor is first formed on the surface of the single crystal substrate wafer, and then a compound silicon gate is formed on the substrate as a mask of ion implantation, and then the ion implantation is controlled by the control electrode. The implantation method forms a source and a drain diffusion region which are automatically aligned with the gate electrode of the metal-oxide semiconductor transistor. The principle of automatically aligning the polycrystalline silicon gates After many modifications, a process has been developed to improve component performance and stability. In particular, the polycrystalline silicon gates using a side wall structure can allow implanted ions along the side walls. Both sides penetrate the substrate surface and diffuse at the edges of the channel area, which can be used to control the short channel effect. The advantages of these metal-oxide half-field effect transistor processes have led to many forms of high-performance sub-micron-sized components. The lightly doped drain (ldd) structure, which is widely used in the sub-micron gold-alloy half-field effect transistor technology, is an important example of this side wall tailoring. Insulating side walls and coverings used on polycrystalline silicon conductors can also be used to form a self-aligning contact opening (SAC) that is automatically aligned with the metal-oxide half-field effect active element. Isotropic etching etches wall-like openings in the vertical direction. Generally, these openings penetrate through the insulation layer, such as silicon oxide or different silicate glass. The automatic alignment of the contact openings can be made in different ways, one --------------- _______ ^ This paper rule relies on (2_ 297 / &)-(Please first read the back I attention matter ΪΜ- Fill out this page again) Threading-Printed by the Central Standard of the Ministry of Economic Affairs, Coconut Consumer Cooperative Γ 14 326 2 9 Λ? Β7 V. Description of the Invention (2) Generally, an insulating edge is formed along the edge of the polycrystalline silicon gate electrode Step, this side wall acts as an insulating gap between the contact opening and the polycrystalline silicon layer. As shown in Fig. 1 ', it shows a cross-sectional view of two adjacent metal-oxide half-field effect transistors on a wafer. The figure shows a traditional DASH cell design. The compound silicon gate electrode 18 is used as the word line of the DRAM. 2 7 and the completion of the conventional LDD process. In the subsequent process, after the bit line 12 is completed, a storage capacitor connected to the pole 14 can be formed. Then 'define the character line, side wall 27 and protective layer 24 by the conventional lithography process and the last name engraving technique. ^ Among them, the character line includes Shixi tungsten 20 and a thin silicon oxide layer on it. twenty two. The side wall 27 and the upper protective layer 24 are made of silicon nitride. Next, an insulating layer 26 composed of silicon monoxide and a silicate glass 28 such as phosphorous glass or butterfly glass are sequentially deposited on the wafer 10. The shattered salt glass 28 is subjected to a planarization process by a conventional planarization method ', such as a chemical mechanical polishing method. Then, a conventional photolithography process is used to form a photoresist layer 30 ′ with a specific pattern, and an opening 32 ′ is formed to expose the surface of the silicate glass layer 28 at a predetermined position where the bit line contacts the opening. The range of the opening 32 may be greater than A predetermined contact opening area on the surface of the polycrystalline silicon. Next, the exposed insulating layers 26, 28 under the opening 32 are defined by a conventional reactive ion etching method to form a bit line contact opening. The etching gas and parameters in the reactive ion etching process are adjusted to have a higher etching selectivity for silicon oxide during the vertical wall-like opening etching process, that is, silicon oxide has a higher etching rate ratio to silicon nitride. Figure 2 This paper size applies the Chinese national standard (CNS) A4 (210X297 mm) (please read the notes on the back before filling out this page) ir Printed by the Consumers' Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs, P432G 2 9 at _________ Β7 V. Description of the Invention (3) ~ The opening 32 shown is formed under the condition that the silicon nitride sidewall 27 and the exposed silicon nitride cover 24 have a sufficiently high etching rate selectivity. The reference number 36 is a polymer layer formed in the remaining process. Under the conditions of inappropriate etching rate selection of the silicon nitride sidewall 27 and the exposed silicon nitride cover 24, nitrogen will be caused. Silicon silicon is eroded, which in turn causes short circuits between bit lines and word lines, as shown at corner 34 of the exposed word line in Figure 3. Until recently, the etch rate selectivity was greater than 8: 1 anisotropy. Etching etching technology has not yet appeared. In the current technology, the feature size of the element is at the level of 0.25 μηη, which must achieve sufficient selectivity without serious engraving edges during the contact opening engraving process. It should be quite difficult to 'the bottom of the opening, for example, a contact oxide will result in incomplete removal of the contact resistance unacceptable value.

Marks et al., In U.S. Patent No. 5,423,945, disclose that reducing the fluorine content in the pad polymer and the free fluorine content in the plasma can reduce polymer decomposition. By adding a fluorine scavenger such as silicon or carbon ions to the plasma, the resulting polymer will become a carbon-rich and non-decomposable polymer. In this example, after the addition of a fluorine scavenger, the etching selectivity of silicon oxide to silicon nitride can reach 15: 1. It is generally believed that the polymers formed by reactive ion etching of carbon fluoride containing etching agents are related to the anisotropy of the etching and the selectivity of the etching rate. For example, during the etching of silicon oxide, the polymer formed will The released oxygen is rapidly decomposed; however, after the silicon argon layer is provided as the hafnium layer, the concentration of oxygen on the silicon nitride region is low, and the polymer is not easy to be divided into paper standards. (CNS) See my secret 21〇χ2_ Chu) '' (. 铕 Read the notes on the back before filling in this page) Thread P4 32 6 2 〇Λ7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (4) solution. In order to achieve high etch rate selectivity as shown in Figure 2, the etch gas and reactive ion etch parameters must be adjusted to provide a fairly stable polymer on the nitrided layer. Residual polymer 36 may be removed before the etching operation is completed. A less stable polymer will invade the silicon nitride, resulting in the structure shown in Figure 3. As component density increases and size shrinks, new challenges must be faced in the definition of etching to automatically align contact openings. Especially for the contact opening size in the range of 0, it will be difficult to completely remove the insulating material in the bottom of the contact opening when defining the contact opening with a high silicon oxide / silicon nitride etching selectivity. The heavy polymer formed on the silicon nitride will interfere with β except the contact with the bottom of the opening, which causes a bridging reaction to cause the opening of the insulating material to shrink, and further terminates the etching. Residual oxides in contact with the bottom of the opening will cause unacceptable contact resistance values. FIG. 4A shows a cross-sectional view of the bit line contact opening 40 defined by the photoresist layer 30. Except for the reduction in the space between the polycrystalline silicon word lines, the other circuit layout is the same as that shown in FIG. Structure is similar. The opening width dl of the photoresist 40 for automatically aligning the upper portion of the contact opening is defined to be about 0.25 to 0.3 Hm. However, the distance d2 between the nitrided stone side walls 27 at the bottom of the auto-alignment contact opening is about 10,000 or less. FIG. 4B shows a cross-sectional view of the contact opening formed after etching through the silicon nitride layer 28 and the silicon oxide layer%. When the #etched layer penetrates the oxidized stone layer 26 as shown in FIG. 4B, because of the inconsistency between the oxygen-cutting / glass-breaking interface, the exposed oxygen-cutting layer 26 and the soup in the middle-reserved area --- -7 The standard is applicable to Chinese National Standard (CNS) Λ4 specifications (——--------- (Please read the precautions on the back before filling this page) Line! · —I— B- ^ i Ministry of Economic Affairs Central Standards Bureau MT Xiaoxian Hezhu Society Printing Purple A7 _LE43Z £ -2_9 _________ V. Description of the invention (5) The polymer formation rate will be different. The silicate glass 28A is performed at a rate 10% lower than the silicon oxide layer 16 Etching. “Please refer to FIG. 4C” to continue the aforementioned step of money engraving, and define the silicon nitride cover layer 24, the silicon nitride sidewall structure 27, and the polymer layer 36 on the silicon nitride structure 27. Finally, please refer to Figure 4D. As the width of the openings between the side walls of the nitrided stone walls decreases, the thick polymer on the silicon nitride will bridge the openings and prevent the engraved gas from oxidizing underneath it. ♦ / Shi Xiate glass 38 'caused the automatic alignment of the bottom of the contact opening was not completely removed, which caused the contact opening due to Unacceptably high contact resistance for residual material 38 ^

Dunfield in U.S. Patent No. 4,793,897 discloses a method for engraving mixed gas containing fluorine and milk gas, so that it has high selectivity to silicon oxide during selective silicon nitride etching. The etching mixed gas contains three metals. Nitrogen fluoride, silicon tetrafluoride, and oxygen. Nitrogen trifluoride is the main etching gas of silicon nitride, and oxygen will combine with silicon in silicon tetrafluoride to selectively form another silicon oxide layer under the silicon oxide to increase the etching gas against the halide layer. Of selectivity.

Thomquist, U.S. Patent No. 4,568,410, discloses a method including an etching gas containing nitrogen difluoride to etch silicon nitride in the presence of silicon oxide. SUMMARY OF THE INVENTION One of the features of the present invention is to provide an improved method for automatically aligning contact openings in a integrated circuit. This paper scale is applicable to China National Standards (CNS) A4 (2) 〇297297 thin) m I n | (il- n--1.-III I ----- n- T mn In HI IK- T (Please read the precautions on the back before filling this page) No. 87110744 Revised Patent Specification

U & ~ A7 B7 Revision date: 90 / 〇2 / 08 Text; > Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) Another feature of the present invention is to provide a method using reactive ion etching 15μιη。 Method of making automatic alignment contact openings with silicon nitride sidewalls, wherein the width between the openings is less than 0.15μιη. Another feature of the present invention is to provide a method for forming an automatic alignment contact opening between adjacent word lines in a DRAM integrated circuit by a two-reactive ion etching method, wherein the word line has a silicon nitride cover layer and Silicon nitride sidewalls' and the width between these openings is less than 0.15 mm. Another feature of the present invention is to provide a method using a reactive ion etching method to form an opening that is automatically aligned with the gate post and can reduce the occurrence of short circuits between the gate and the contact opening. Among the above-mentioned features, the etching gas composed of a carrier gas composed of octafluorocyclobutane, fluorinated methane, oxygen, and argon is used to automatically align the last name of the contact opening. A small amount of oxygen milk is suitable to reduce the polymer falling into narrow openings to prevent crush deformation. In addition, a small amount of oxygen has also been found to improve the ability of the etch to stop at the nitride nitride interface ’and thereby reduce the risk of contact shorts between the gates and bit lines. The oxygen flow rate must be limited to a small range in this critical process. Brief description of the drawings: In order to make the advantages and features of the present invention more obvious, the preferred embodiments and related drawings are described in detail below. Figures 1 to 3 show a cross-sectional process of a conventional DRAM for automatically aligning contact openings. Figures 4A ~ 4D show a conventional method for making a line with a depth of sub-micron -ϋ I n ϋ-(Please read the notes on the back before filling this page). Line r4 32 6? 9 A7 B7 Warp " ' -Printed by the Ministry of Standards and Technology Bureau, Shellfish Consumer Cooperative, V. Invention Description (7) Cross-section process of automatic alignment of DRAM cells with contact openings. Figures 5A to 5F show a cross-sectional process of an embodiment of an automatic alignment cell for making a dram cell with a line width of a deep sub-micron according to the manufacturing process of the present invention. The cell structure has contact bit lines automatically aligned with two adjacent word lines, wherein the width of the contact opening is less than I50 nm, and the interval between adjacent word lines is about 300 nm. First, referring to FIG. 5A, a silicon wafer 10 is provided, and a doped polycrystalline silicon layer 18 having a thickness of about 50 to 50 nm is formed on the gate oxide layer 16. Wherein, the doped polycrystalline silicon layer 18 may be in the form of a composition, which may additionally include a conductive layer 20 composed of a metal silicide, such as tungsten silicide (WSix). The polycrystalline silicon layer 18 can be formed by a well-known chemical vapor deposition method, and then an impurity implantation method is used to implant impurities into the deposited polycrystalline silicon layer to form a doped polycrystalline silicon layer. Layer 18 ^ Then, a silicon oxide layer 22 with a thickness of about 20˜50 nm is deposited on the conductive layer 20 by using a chemical vapor deposition method. The silicon oxide layer 22 may be, for example, a tetraethoxy silicon layer. Next, a conventional silicon methane and ammonia gas are used as precursors, and a silicon nitride layer 24 having a thickness of about 150 to 250 nm is formed on the silicon oxide layer 22 by a chemical vapor deposition method. Then, a photoresist pattern 25 is formed on the silicon nitride layer 24, and then the photoresist pattern is used as an etching mask, and the gate pillars and words of the gold-oxygen half field effect transistor are defined by anisotropic ion etching. Element line ^ At present, the space between the character lines of sub-micron DRAM is generally between 0 ~ 2.

I fix 10 This paper size applies to Chinese National Standards (CNS) Public meals A7 B7 »432629 V. Description of the invention (8) 0.3μm. Secondly, please refer to FIG. 5B. After removing the photoresist pattern 25, a character line 50 formed by the reactive ion surname engraving method is obtained. Ion implantation was performed using arsenic ions with an energy of about 20 to 40 KeV at a dose of 1012 1014 atoms / cm2 to form a lightly doped dopant region 15 ^ and then 'Please refer to FIG. 5C, word line structure 50 side The nitrided and broken side wall 27 of the wall can first be formed by chemical vapor deposition to form a silicon argon layer with a thickness corresponding to the thickness of the desired side wall to cover the structure surface shown in FIG. 5b smoothly, and then use Reactive ion etching etch-back removes the excess silicon nitride layer, and a silicon nitride sidewall 27 is formed on the sidewall of the word line structure 50. To reduce the interface pressure, a thin pad oxide layer (not shown) can be deposited before the silicon nitride layer is deposited. The function of the side wall 27 is not only used to define a lightly doped source (LDD) structure, but it can also be used to distinguish between auto-aligned contact openings and polycrystalline silicon gates and LDD regions. In the current DRam design size, the thickness of the silicon nitride sidewall 27 is about 50˜100 nm. After the side wall 27 is formed, the wafer is ion-implanted at a dose of 1014 to 10i6 atoms / cm2 with thorium ions having an energy of about 20 to 40 KeV to form a deeper and higher concentration impurity-doped drain region. 12, M, complete the metal-oxygen half field effect transistor with word line 50. Next, please refer to FIG. 5D, and form an insulating layer 29 on the wafer 10 with a thickness of about goo ~ 1000A, which may be composed of silicon oxide formed by low-pressure chemical vapor deposition as shown in the figure. Insulation layer 26 and chemical vapor deposition of phosphosilicate glass or borophosphosilicate glass on top of the insulation layer 28 ^ Zhang Zhang size appropriate (training x297: {: read the precautions on the back before filling in this page)

、 1T It was printed by the offenders of the Ministry of Standards of the Ministry of Standards and Consumption. -------------------.____ The final prize of the Ministry of Economics of the Ministry of Standards ??-Bureau Μ Λ Elimination of combined bamboo and printed seals Γρ ^ / __14 326 2 9 B7__ V. Composition of the invention (9); or the entire insulating layer 29 is composed of silicon oxide. Insulation films formed by chemical vapor deposition have been widely used in the art. Then, after the insulating layer 28 is deposited, the insulating layer 28 may be repeatedly subjected to a flattening treatment such as a chemical mechanical polishing method to remove the topological characteristics. Then, a conventional photolithography process is used to form a photoresist layer 30 with a specific pattern on the planarized insulating layer, and an opening 40 exposing the insulating layer 28 is formed at a predetermined contact opening. Next, the crystal circle is placed in a reaction chamber (HDp etcher) in a high-density plasma etching machine;

Appied Materials, Inc. of Santa Clara CA). When the pressure in the reaction chamber is reduced to about 10-4 torr or lower, the last name engraving step can be started. The etching gas used for etching is composed of the octafluorocyclobutane courtyard with a flow rate of about 10 to 15 SCCM and a flow rate of about 5 to 15 SCCM and CHJ, and the flow rate is about! It consists of ~ 3 SCCM of oxygen and a carrier gas of about 100 SCCM-argon, and the energy density of this high-density destroyer is about 4.6 W / cm2. Under this reaction condition, a vertical sidewall can be formed and the etching ratio of the oxide to the nitride is about 20: ι. When octafluorocyclobutane and CH3F are used without oxygen, the etching selectivity of the reactive ion etching method to the silicon trioxide / silicon argon is about 30: 1. However, ‘because the small size of the contact opening will leave residual insulating material in the opening’, in order to completely remove this opening, at least 1 SCCM of oxygen will be required in the etching gas. In other words, if the etching conditions are the same as the above description, but when the oxygen flow rate exceeds 3 SCCM, the polymer maintained in an insufficiently stable state will deleteriously erode the silicon argon covering the paper. -(Please read the notes on the back before filling this page; j

r 32 6 2 Q A7 ^ B7 I — — ~ ~ '— V. Description of the invention (i〇) Layer / side wall structure 24/27. Therefore, to make the etched structure the desired result, careful control of the oxygen flow rate will be quite necessary. Fig. 5E shows a sectional view of the contact opening after the reactive ion etching step. Next, the residual photoresist 36 and the residual photoresist 30 are removed by a known photoresist removal method. Finally, referring to FIG. 5F, a conventional plug inspection process is used to form a metal plug 42 in the automatic alignment contact opening 40. The plug 42 can be, for example, a polycrystalline silicon plug or a metal plug. In addition to the above processes, the present invention can continue other additional processes for forming DRAM cells, which include forming bit lines on the insulating layer 28 and the metal plug 42 and forming a storage capacitor (not shown) on the active contact area 14 It is shown that the present invention has used the embodiments in conjunction with the related drawings to describe the features and contents of the present invention in detail. 'The embodiments mentioned herein are for convenience only' and are not intended to limit the present invention. Therefore, any Those skilled in the art ', without departing from the spirit and scope of the present invention, make various modifications and retouches that fall within the patent scope of the present invention. Member of the Central Standards Bureau of the Ministry of Economic Affairs τ, Consumer Cooperative Seal 3; Moderate Ruler One Say Beta | Ben Jun

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Claims (1)

Amendment of Patent Application No. 871 10744 _ B8 Patent application scope revision date 188 # 2. # 9 EI repair supplement • A method of forming a contact window automatically aligned to a metal-oxide semiconductor field-effect transistor gate semiconductor unit, the steps include: (a) providing a vertical A wall-shaped gate post and a silicon wafer of an active semiconductor unit, wherein the gate post has an insulating cover layer and a side wall structure, and the active semiconductor unit is located near the side wall; (b) depositing a A first insulating layer on the silicon wafer; (c) depositing a second insulating layer on the silicon wafer; (d) applying a planarization treatment to the second insulating layer; (e) depositing a photoresist layer on On the second insulating layer; (f) using the photoresist layer to define a contact opening; (g) a reactive ion engraving method and a mixture containing octafluorocyclobutane, chaotic methane (CHJ) and oxygen, and Argon is used as a carrier frequency plasma to etch the second insulating layer and the first insulating layer to form a contact opening: (h) removing residual polymer; (i) removing the photoresist layer; and (ii) depositing a conductive material. Layer inside the contact opening Then forming a self-aligned contact opening. 2. The method according to item 1 of the scope of patent application, wherein the first insulating layer is oxidized stone. 3. The method according to item 1 of the scope of patent application, wherein the second euphemum layer is selected from the group consisting of oxidized stone, glass, and boron glass. 4. The method as described in item 1 of the scope of patent application, wherein the absolute nllllul · — — ---- I-^ subscribe! —- 线 --- f Please read the note on the back before filling in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs \ 4 I A8 a IT h. Shi Xi layer m? 6 2 9 VI. The scope of patent application (d) forms a first ~ hanging photoresist layer with a specific pattern on the "—" silicon layer to define adjacent words Element line; 11 介 ⑷Order non-isotropicity # Carved the [nitrogen cut layer, the and the conductive layer, and then formed a phase line with each other _ character line; (f) implanted the first dose of impurity atoms; (g) Remove the first photoresist layer; ⑻ deposition-a second nitrogen cutting layer on the junction surface formed in the above steps; (!) Anisotropically etch the second nitride layer, and along the edge of the character scale Forming a side wall; (j) implanting a second dose of impurity atoms, and then forming a semiconductor single ---------------- Λ -----~ Unintentionally fill in this I) (k) Deposit an insulating layer on the silicon wafer: (l) Apply a planarization treatment to the insulating layer; (m) Form a second photoresist with a specific pattern Layer on this insulation shoulder-line. Yuan line is set | Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (η) Use this second photoresist pattern to make two Yuan line contact openings (0) etching the second insulating layer and the first insulating layer using a reactive ion etching method and plasma containing octafluorocyclobutanefluorinated methane (CH3F), an oxygen mixture, and argon as a radiation frequency plasma carrying a radon, Form a contact opening; (P) remove the residual polymer; (q) remove the photoresist layer; 16 this paper size is applicable to the Chinese garden house standard 4MCNSM4 specification ⑵0,297 public love) AS B8 C8 D8 P432629 ▽, scope of patent application (r) deposition-a layer of conductive material is formed in the contact opening, and then a self-aligned contact opening is formed; (S) a bit line is formed on the bit line contact opening; and a silicon wafer is formed on the silicon wafer Storage capacitor. According to the method described in claim 12 of the patent application scope, ten of the first insulating layers are silicon oxide. M. The method as described in item Π of the patent application scope, wherein the second insulating layer is selected from the group consisting of silicon oxide, phosphor glass, and borophosphosilicate glass. 15. The method according to item 12 of the scope of application for a patent, wherein the width of the contact opening is about 0.1 ~ 0.4 | im. 16. The method as described in item 2 of the scope of patent application, wherein the thickness of the side wall structure is about 50 to 100 nm. 17. The method according to item 12 of the scope of patent application, wherein a distance between the two adjacent character lines is about 0.18 to 0.35 μm. 18_ The method described in item a of the scope of the patent application, wherein the flow rate of the octafluorocyclobutane is about 10 to 15 SCCM, the flow rate of the chloroform is about 5 to 15 SCCM, and the flow rate of the oxygen is about 1 ~ 3 SCCM. 19. The method according to item 12 of the scope of patent application, wherein the total pressure of the argon gas in the reaction chamber is adjusted to 2 to mtorr. 20. The method according to item 12 of the scope of patent application, wherein the conductive material is a tungsten plug. 17 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -mlltlmll— V. ^ · 1111111 · ίιΙΙ1 {Please read the precautions on the back before filling out this page} Employee Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Printed by a cooperative