"B43254 4 5078twf.doc/006 五、發明說明（/ ) 本發明是有關於一種積體電路的製造方法，且特別是 有關於一種金氧半場效電晶體（MOSFET)的製造方法。 目前的積體電路製程，是在完成電晶體的製作之後， 形成介電層覆蓋基底與電晶體，以作爲元件之間的隔離。 但是如此一來電晶體之閘極與源極/汲極之間會因爲存在 著導體-介電物質-導體的結構而產生寄生電容 (Parasitic Capacitor)。寄生電容會增大元件的電阻-電 容時間延遲（R-C Delay Time)，進而減慢元件的操作速 度。 寄生電容的大小與位於閘極與源極/汲極之間的介電 物質有關，而在閘極與源極/汲極之間的介電物質通常爲 用以隔離元件的介電層與間隙壁。介電層的材質通常爲氧 化矽（Si〇2)，而間隙壁則爲氧化矽或氮化矽（Si3N4)。這兩 種材質的介電常數都相當大（氧化矽爲3.9,而氮化矽爲 7.0) ’因此存在於閘極與源極/汲極之間的寄生電容相當 大，因而對元件的操作速度有相當不利的影響。 有鑑於此，本發明提供一種降低寄生電容的方法，可 以有效的降低存在於電晶體之閘極與源極/汲極之間的寄 生電容，減小元件的電阻-電容時間延遲，以增快元件的 操作速度。 本發明提供一種降低寄生電容的方法，藉由在閘極兩 側的介電層中形成介電常數較低的空氣間隙（Air Gap)， 來降低閘極與源極/汲極之間的寄生電容。而形成此空氣 間隙的方法係先提供一個半導體基底，並於基底上形成聞 3 本紙張尺度遶用中國國家標準（CNS)AI規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 机--------訂·--Γ ------線— 經濟部智慧財產局員工消費合作社印製 B43254 4 5078twf.doc/006 經濟部智慧財產局員工消費合作社印製 五、發明說明（及） 氧化層。接著’於閘氧化層上形成閘極，並於閘極兩側的 基底中形成輕摻雜汲極結構。之後，形成與基底共形的襯 氧化層，並形成間隙壁緊接於閘極兩側的襯氧化層。其 中’間隙壁的材質爲氮化矽。接著，於間隙壁外側的基底 中形成源極/汲極與輕摻雜汲極結構相連。之後，於基底 上形成第一介電層。其中，第一介電層的高度略低於間隙 壁之上端，因此間隙壁將暴露出部分表面。以濕式蝕刻法 移除間隙壁，以於閘極與介電層中形成開口小而底部大的 孔洞=之後，以階梯覆蓋能力較差的薄膜沉積方式形成第 二介電層以將此孔洞封住，並覆蓋整個基底。在此步驟 中，雖然有部分第二介電層也塡入此孔洞中，但是孔洞並 未被第二介電層所塡滿，因而使得所形成之第二介電層中 具有空氣間隙。 由於以上述方法所形成的空氣間隙中充滿空氣，且空 氣的介電常數相當低（空氣的介電常數約爲1)，因此大幅 降低了介於閘極與源極/汲極之間之介電物質的介電常 數，進而有效的降低寄生電容。 本發明的主要特徵爲在閘極兩側形成類似間隙壁的空 氣間隙，利用空氣介電常數較低的特性來降低閘極與源極 /汲極之間的寄生電容。 本發明的另一特徵爲形成表面高度略低於間隙壁上端 的第一介電層，移除間隙壁以形成開口小而底部大的孔洞 之後，再以階梯覆蓋能力較差的薄膜沉積方法形成第二介 電層，以使第二介電層在不會將孔洞塡滿的情況下就將孔 4 (清先閱讀背面之注意事項再填寫本頁) 衣 訂！！線| -n a— n . $纸張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） Γ ·432544 5078twf.doc/〇〇6 五、發明說明（$ ) 洞封住。如此一來，即形成形狀類似間隙壁的空氣間隙。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖至弟1D圖係繪τκ根據本發明較佳實施例，一. 種降低寄生電容之方法的剖面流程圖。 圖示之標號說明： 100 :基底 102 :閘氧化層 104 :閘極 106 :輕摻雜汲極結構 108 :襯氧化層 110 :間隙壁 112 :源極/汲極 114 :第一介電層 116 :孔洞 118 :第二介電層 120 :空氣間隙 竇施例 請參照第1A圖，在半導體基底100上形成閘氧化層 102 ’並於閘氧化層102上形成閘極104。其中，形成閘極 104的方法比如爲先形成一層複晶矽全面覆蓋閘氧化層 1〇2，再以微影蝕刻的方式定義出閘極104。接著，於閘極 5 本紙張又度適用中國國家標準（CNS)A4覘格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) ^·!!!1 訂·！-----— . 經濟部智慧財產局負工消費合作杜印製 Γ ·432544 5078tvvt'.doc/006 五、發明說明（） 104兩側的基底100中形成輕摻雜汲極結構106。之後， (請先閱讀背面之注意事項再填寫本頁) 形成與基底100共形的襯氧化層108，並形成間隙壁Π0 緊接於閘極104兩側的襯氧化層108外側。其中，形成間 隙壁110的方法則比如爲先形成一層氮化矽全面覆蓋基底 100，再進行回蝕刻（Etch Back)步驟。接著，於間隙壁108 外側的基底100中形成源極/汲極112。 經濟部智慧財產局員工消費合作社印製 請參照第1B圖，於基底100上形成第一介電層114。 其中第一介電層114的表面略低於間隙壁110上端的高 度，也就是使得間隙壁110暴露出部分表面。形成此第一-介電層114的方法比如爲先沉積一層厚度大約爲5000埃 至8000埃的氧化矽全面覆蓋基底100，接著，以化學機械 硏磨法（CMP)硏磨這層氧化矽，利用時間的控制，以決定 硏磨的終點之後，再回蝕刻此氧化矽層直至其表面的高度 低於間隙壁110上端大約400埃至500埃。在此步驟中， 由於閘極104與間隙壁110的材質與第一介電層丨14不 同，因此閘極104與間隙壁110在化學機械硏磨的過程中 並不會被損壞。但是襯氧化層108位於閘極104上的部分 則因爲跟第一介電層114具有相同的材質而被移除。而所 形成之第一介電層114的厚度則可以藉由控制回蝕刻的時 間來加以掌握。 請參照第1C圖，移除間隙壁110，以於閘極104與第 一介電層U4之間形成開口小而底部較大的孔洞Π6。其 中，移除間隙壁110的方法比如爲濕式蝕刻法。在此步驟 中，由於間隙壁110的材質不同於第一介電層114與襯氧 6 本紙張尺度適用中國國家標準（CNS)A.l規格（210 X 297公釐） r 鼸43254 4 5078lwf'doc/006 經濟部智慧財產局員工消費合作社印製 五、發明說明（e) 化層108,因此將間隙壁110完全移除後，第一介電層114 與襯氧化層108仍將保有原來的厚度與形狀’這也就是形 成孔洞Π6的原因。 請參照第1D圖，形成第二介電層Π8,在不將孔洞116 塡滿的前提下，將孔洞丨16(繪示於第1C圖中）封住，並全 面覆蓋基底100,以形成空氣間隙丨20。基於此考量，形 成第二介電層118的方法必須採用階梯覆蓋能力較差的薄 膜沉積技術來進行。形成第二介電層118的方法比如爲以 電發加強化學氣相沉積法（Plasma Enhanced Chemical Vapor Deposition ; PECVD)沉積一層氧化矽。 在此步驟中，由於孔洞116的開口較小而底部較大， 因此在形成第二介電層118時雖然會在孔洞Π6中也有部 分的第二介電層118，但是在第二介電層118將孔洞116 封住時，仍然會形成空氣間隙120。由此可知，在形成第 一介電層Π4時，第一介電層114的高度控制相當重要， 必須配合形成第二介電層118之技術的階梯覆蓋能力，以 使第二介電層U 8不塡滿孔洞116，就將孔洞116封住， 以達到形成空氣間隙120的目的。 由上述可知，本發明的主要特徵爲在閘極兩側形成類 似間隙壁的空氣間隙，利用空氣之介電常數較低的特性來 降低閘極與源極/汲極之間的寄生電容。 而本發明的另一特徵爲形成表面高度略低於間隙壁上 端的第一介電層，移除間隙壁以形成開口小而底部大的孔 洞之後，再以階梯覆蓋能力較差的薄膜沉積方法形成第二 7 ----------- 裝.一-------11111111 I (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用令囷國家標準（CNS)A4規格（210 X 297公釐） 疆4 3254 4 5078twf.doc/006 A7 B7 五、發明說明（G ) 介電層，以使第二介電層在不會將孔洞塡滿的情況下就將 孔洞封住。如此一來，即形成形狀類似間隙壁的空氣間 隙。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 ------------^ - I ---ί — 訂---I I.--I 線“ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐）" B43254 4 5078twf.doc / 006 V. Description of the Invention (/) The present invention relates to a method for manufacturing an integrated circuit, and more particularly to a method for manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET). In the current integrated circuit manufacturing process, a dielectric layer is formed to cover the substrate and the transistor after the transistor is manufactured, so as to isolate the components. However, such a parasitic capacitance is generated between the gate and source / drain of an incoming crystal because of the conductor-dielectric substance-conductor structure. Parasitic capacitance increases the resistance-capacitance time delay (R-C Delay Time) of the device, which in turn slows down the operation speed of the device. The size of the parasitic capacitance is related to the dielectric substance between the gate and the source / drain, and the dielectric substance between the gate and the source / drain is usually a dielectric layer and a gap for isolating components. wall. The material of the dielectric layer is usually silicon oxide (SiO2), and the spacer is silicon oxide or silicon nitride (Si3N4). The dielectric constants of these two materials are quite large (3.9 for silicon oxide and 7.0 for silicon nitride) 'Therefore, the parasitic capacitance between the gate and source / drain is quite large, and therefore the operating speed of the component Have a considerable adverse effect. In view of this, the present invention provides a method for reducing parasitic capacitance, which can effectively reduce the parasitic capacitance existing between the gate and source / drain of the transistor, reduce the resistance-capacitance time delay of the element, and increase the speed. Element operating speed. The invention provides a method for reducing parasitic capacitance. By forming an air gap (Air Gap) with a lower dielectric constant in a dielectric layer on both sides of a gate, the parasitic between the gate and the source / drain is reduced. capacitance. The method of forming this air gap is to first provide a semiconductor substrate and form a substrate on the substrate. The paper size is around the Chinese National Standard (CNS) AI specification (210 X 297 mm) (Please read the precautions on the back before (Fill in this page) Machine -------- Order · --Γ ------ Line—Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economy B43254 4 5078twf.doc / 006 Printed by the cooperative V. Description of invention (and) Oxidation layer. Next, a gate is formed on the gate oxide layer, and a lightly doped drain structure is formed in the substrate on both sides of the gate. After that, a lining oxide layer conforming to the substrate is formed, and a lining oxide layer having a spacer wall immediately adjacent to both sides of the gate electrode is formed. The material of the 'partition wall' is silicon nitride. Next, a source / drain is formed in the substrate outside the gap wall to be connected to the lightly doped drain structure. After that, a first dielectric layer is formed on the substrate. The height of the first dielectric layer is slightly lower than the upper end of the gap wall, so the gap wall will expose part of the surface. The gap wall is removed by a wet etching method to form a small opening and a large bottom hole in the gate and the dielectric layer. Then, a second dielectric layer is formed by a thin film deposition method with poor step coverage to seal the hole. Live and cover the entire substrate. In this step, although part of the second dielectric layer is also inserted into the hole, the hole is not filled with the second dielectric layer, so that the formed second dielectric layer has an air gap. Because the air gap formed by the above method is filled with air, and the dielectric constant of the air is quite low (the dielectric constant of the air is about 1), the dielectric between the gate and the source / drain is greatly reduced. The dielectric constant of the electric substance, thereby effectively reducing the parasitic capacitance. The main feature of the present invention is to form an air gap similar to a gap wall on both sides of the gate, and use the characteristic of low air dielectric constant to reduce the parasitic capacitance between the gate and the source / drain. Another feature of the present invention is to form a first dielectric layer whose surface height is slightly lower than the upper end of the gap wall. After removing the gap wall to form a hole with a small opening and a large bottom, a thin film deposition method with poor step coverage is used to form the first dielectric layer. Two dielectric layers, so that the second dielectric layer will fill the holes 4 without filling the holes (please read the precautions on the back before filling this page). !!线 | -n a— n. $ The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Γ · 432544 5078twf.doc / 〇〇6 The description of the invention ($) The hole is sealed. In this way, an air gap having a shape similar to a partition wall is formed. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A to The 1D diagram is a cross-sectional flowchart of a method for reducing parasitic capacitance according to a preferred embodiment of the present invention. Description of the symbols in the figure: 100: substrate 102: gate oxide layer 104: gate electrode 106: lightly doped drain structure 108: liner oxide layer 110: spacer wall 112: source / drain 114: first dielectric layer 116 : Hole 118: Second dielectric layer 120: Example of air gap sinus Please refer to FIG. 1A, a gate oxide layer 102 ′ is formed on the semiconductor substrate 100 and a gate electrode 104 is formed on the gate oxide layer 102. The method for forming the gate 104 is, for example, firstly forming a layer of polycrystalline silicon to completely cover the gate oxide layer 102, and then defining the gate 104 by means of lithographic etching. Then, the 5 pieces of paper on the gate electrode are again applicable to the Chinese National Standard (CNS) A4 grid (210 X 297 mm) (Please read the precautions on the back before filling this page) ^ · !!! 1 Order ·! -----—. Du Du printed by the Consumer and Intellectual Property Bureau of the Ministry of Economic Affairs Γ · 432544 5078tvvt'.doc / 006 V. Description of the invention () A lightly doped drain structure 106 is formed in the substrate 100 on both sides of the 104. After that (please read the precautions on the back before filling this page), form a liner oxide layer 108 conforming to the substrate 100, and form a spacer Π0 just outside the liner oxide layer 108 on both sides of the gate 104. The method for forming the spacer 110 is, for example, forming a layer of silicon nitride to completely cover the substrate 100, and then performing an Etch Back step. Next, a source / drain 112 is formed in the substrate 100 outside the spacer 108. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to FIG. 1B to form a first dielectric layer 114 on the substrate 100. The surface of the first dielectric layer 114 is slightly lower than the height of the upper end of the spacer 110, that is, the surface of the spacer 110 is exposed. The method of forming the first-dielectric layer 114 is, for example, firstly depositing a layer of silicon oxide with a thickness of about 5000 angstroms to 8000 angstroms to completely cover the substrate 100, and then, honing the silicon oxide layer by chemical mechanical honing (CMP), After controlling the time to determine the end of the honing, the silicon oxide layer is etched back until the height of the surface of the silicon oxide layer is about 400 angstroms to 500 angstroms below the upper end of the spacer 110. In this step, since the materials of the gate electrode 104 and the spacer 110 are different from those of the first dielectric layer 14, the gate electrode 104 and the spacer 110 are not damaged during the CMP process. However, the portion of the liner oxide layer 108 on the gate electrode 104 is removed because it has the same material as the first dielectric layer 114. The thickness of the formed first dielectric layer 114 can be determined by controlling the etch-back time. Referring to FIG. 1C, the spacer 110 is removed to form a small hole Π6 with a small opening between the gate 104 and the first dielectric layer U4. Among them, a method of removing the spacer 110 is, for example, a wet etching method. In this step, the material of the spacer 110 is different from the first dielectric layer 114 and the oxygen lining. 6 The paper size applies the Chinese National Standard (CNS) Al specification (210 X 297 mm) r 鼸 43254 4 5078lwf'doc / 006 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (e) The layer 108, so after the spacer 110 is completely removed, the first dielectric layer 114 and the liner oxide layer 108 will still retain the original thickness and Shape 'This is why the holes Π6 are formed. Referring to FIG. 1D, a second dielectric layer Π8 is formed, and the holes 116 (shown in FIG. 1C) are sealed without completely covering the holes 116, and the substrate 100 is completely covered to form air. Clearance 丨 20. Based on this consideration, the method of forming the second dielectric layer 118 must be performed using a thin film deposition technique with poor step coverage. A method of forming the second dielectric layer 118 is, for example, depositing a layer of silicon oxide by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. In this step, since the opening of the hole 116 is small and the bottom is large, although the second dielectric layer 118 may also have a portion of the second dielectric layer 118 in the hole Π6, the second dielectric layer 118 is formed in the second dielectric layer 118. When the hole 116 is sealed by 118, an air gap 120 is still formed. It can be seen that when forming the first dielectric layer Π4, the height control of the first dielectric layer 114 is very important, and the step coverage capability of the technology for forming the second dielectric layer 118 must be matched to make the second dielectric layer U 8 Without filling the hole 116, the hole 116 is sealed to achieve the purpose of forming the air gap 120. As can be seen from the above, the main feature of the present invention is to form an air gap similar to a gap wall on both sides of the gate, and to use the characteristic of low dielectric constant of air to reduce the parasitic capacitance between the gate and the source / drain. Another feature of the present invention is to form a first dielectric layer whose surface height is slightly lower than the upper end of the gap wall. After removing the gap wall to form a hole with a small opening and a large bottom, it is formed by a thin film deposition method with poor step coverage. Second 7 ----------- Loading. One ------- 11111111 I (Please read the precautions on the back before filling out this page) This paper is applicable to the national standard (CNS) A4 specification (210 X 297 mm) Xinjiang 4 3254 4 5078twf.doc / 006 A7 B7 V. Description of the invention (G) Dielectric layer, so that the second dielectric layer will be filled without holes. The hole was sealed. As a result, an air gap having a shape similar to a gap wall is formed. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. ------------ ^-I --- ί — Order --- I I .-- I Line "(Please read the notes on the back before filling this page) Intellectual Property Bureau of the Ministry of Economic Affairs The paper size printed by the employee consumer cooperative is applicable to the national standard (CNS) A4 specification (210 X 297 mm)