TW432286B - Bus retry read method - Google Patents

Abstract

The present invention relates to a bus retry read method including the following procedures. When a host sends a ""read"" request to a target through a bus, and if the target is not ready yet, the target will send a ""stop"" signal as an instruction to request the host to stop reading data. Then, the target will keep a target ready signal in a non-driving status to instruct the host to retry read. At the same time when the target sends out a ""stop"" signal, an address signal containing clock numbers will also be sent out to request the host to carry out retry read after the clock numbers are counted.

Description

__ 132286 V. Description of the invention (1) The present invention relates to a method for bus retry (Re try), especially a method for bus retry data read (Retry Read). Early personal computer systems mainly used a single bus to transfer data between different bus devices in the system. Typical buses include an ISA bus with a 16-bit data width and an EISA bus with a 32-bit data width. At present, these buses are limited in bus width and speed, so it is difficult to increase the bus speed. In addition, there is a bus that can be applied to a computer system that includes a processor and the aforementioned I SA and EI SA buses (hereinafter referred to as expansion buses). Such buses are generally called peripheral component interconnect buses ( PC I: peripheral component interconect bus), its special * 11 is capable of data transmission at a faster speed. At present, the computer system using the PC I bus is mainly added a host system / PCI bus bridge (HOST / PCI bus bridge; hereinafter referred to as the main bridge), which is controlled by the PC I bus, the central processing unit, and the main memory ( ma i η memory) data transfer, PCI / expansion bus bridge (PCI / EXP ANS I 0N bus bridge hereinafter referred to as the expansion bridge) is controlled in pc [data transfer between the bus and exchange. This gift arrangement allows the components on the PC to send data to the main memory through the main bridge, or to receive data from the master and old style; the components on the expansion bus can use the expansion bridge and Pc J The bus can transmit data to and from the components on the PC I bus, and can also transmit data to and from the processor and the master via the main bridge, expansion bridge, and PC I bus. For example, the personal computer system 10 shown in FIG.

Page 4 ___4 32286 V. Description of the invention (2) The components include the central processing unit 12, the main system bus 14, the main system / PC I bus bridge 16 (hereinafter referred to as the main bridge), and the PC I bus 1 8, PC I / expansion bus bridge 20 (hereinafter referred to as the expansion bridge), and expansion bus 22.

Among them, the processor 12 provides various processing signals, performs calculation and control operations, and tasks generally performed by the processor. In addition, the processor 12 is coupled to the host system bus (host bus) 1 4 and the main bridge 16 provides the interface between the host system bus M and the PCI bus 18. As for the PCI bus specification 1 In 1999, the 2.1 modified version of the bus device 26 and the expansion bridge 20 are coupled to the PCI bus 18, and the high-frequency bus device 26 generally includes input / output devices, such as graphics devices (graphics I dev ice) 26a 'LAN 26b, or small computer system interface device (SCSI) 2 6c, etc. In addition, 'typical low-frequency bus devices such as basic I / O function devices (28 based on I / O function device) consume the expansion bus 2 2' Among them, only bus devices with active memory access capabilities can As a PCI bus master device 'A bus device that does not have the ability to actively access memory can only be used as a Pπ bus slave device (PCI bus slave). 1 bridge 1 6 — generally including a cutting unit (arbit ra ο ο :). For a bus device that has access to physical power, the arbitration unit is used to arbitrate between various competitive situations The access requirements between the bus devices to determine that control over the PC I bus 18 can be obtained. For example, when there are different pc 1 bus devices that need to access the memory, they will each issue a request signal to the arbitration unit 'The arbitration unit will approve the PC I bus 1 8 to the bus device that won arbitration according to the arbitration agreement' At this time, the bus device becomes-4 32286 V. Description of the invention (3) Only PC I bus master control device with control right. Take the PC I bus master control device 27 connected to the PC I bus 18 as an example. Its characteristic is generally that it has a processor to operate according to its internal timing cycle rate and can be used on the PC I bus. Perform initialization and control operations. In addition, the functions performed by the main bridge 16 include, in addition to the communication between the processor 12 and the PCI bus, and the arbitration of the control requirements of the PC I bus 18, it also includes the memory 2 4 / processor 12 And memory 24 / PCI bus 18 communication0

The expansion bridge 20 is coupled to the PC I bus 18 and the expansion bus 22 to perform data parental switching, control signals, and addresses between devices respectively coupled to the PC I bus 18 and the expansion bus 22 The signal ^ expansion bridge 20 also includes an arbitration unit, which is used to arbitrate the requirements of each bus device 28 coupled to the expansion bus 22, where the expansion bus 22 and the bus device 28 are in accordance with ISA, EISA or MCA The standard. Among them, as shown in FIG. 2, the pci interface between the main bridge 16 and the expansion bridge 20 is taken as an example, which includes a multi-site address / data bus signal AD and a bit enable 1 · CB; interface control_ Control signals, such as the control signal, including the E-flow schedule cycle frame signal FRAME #, the host device ready signal IRDY #, the target device ready signal TRDY #, the device selection signal DEVSEL #, and Stop signal STOP #; Arbitration signal, such as PCI approval signal PGNT # and PCI request signal PREQ #. In addition, as shown in Table 1, on the P C I architecture, it generally includes arbitration status, address status, and data status.

Page 6 432286 V. Description of the invention (4) Same logic potential states, such as low potential L, high potential Η and floating state X. table-

Signal name Custom status Address status Data status FRAME # XLU The last item is Η IRDY # X Η L DEVSEL # X Η L CBE X instruction iris byte enable AD X address t section STOP # X Η Repeat Try or Η TRDY # X Η L PREQ # demand signal LL PGNT # 椋 quasi signal LL Among them, the bus cycle frame signal FRAME #, which indicates that a read or write cycle operation with the address status starts, and is in place During the address state, the address signal AD [3 1: 0] contains a valid address, and the bit enable signal CBE # contains a valid bus command. In addition, the master control device ready signal IR Μ # indicates that the master control device is ready to accept the treasure during the data reading cycle, and% indicates that the valid data is in the address signal AD [3 during the data entry cycle. 1: 0]. In contrast, the selected device ready signal TRDY # indicates that the valid data is already on the address signal AD [3 1: 0] during the data reading cycle, and indicates that the selected device has been in the data writing cycle. Ready to accept data. As for the device selection signal DEVSEL #, it is used to show that the driven device has decoded its address as a destination.

Page 7

V. Description of the invention (5) A selected device previously accessed. Take the reading data as an example. When the data selected by the center is selected by the main bridge, the data is read by the main bridge 16 as the main control device i, and the control power of the J bus is selected through the jealous selection. , ^ 1: (se 1 ec t ed dpvirp) Such as the expansion bridge 20 to read data to the central processing unit 12. d0V1Ce): However, because the stop signal ST0P # is issued, it instructs the host control device 16 to stop the transmission of the current bus by 2o :: r: ctlon) 'Therefore, when the selected device 2o cannot complete the main control device 16 When the request is taken, it will use the stop signal ST〇p # to initialize the termination status of the GmUate) bus transmission action (ter [nati⑽ / he transaction), where the selected device 20 initializes and terminates the large target initiated termination. One way is to retry 6Y), that is, before any data transmission, when the selected device 20 cannot process the data because it is in a state where the materials are not ready, it can temporarily terminate the data reading request. Please refer to Figs. 1 and 2 and refer to Fig. 3, which shows the sequence of the first day and the second day of the retry cycle. According to the timing diagram in Figure 3, the signal sampling is selected at the rising edge of the pc I timing signal i% LK. Each turn Pe 丨 timing pavilion number PCU 4 rising edge is a wide vertical dotted line marked with a low level of logic 0. The driving signal is marked with # at the end of the letter 5 tiger name%. First, when the central processing unit 12 wants to read the data of the fork selection device such as the expansion bridge 20, the master control device such as the main bridge 6 issues a bus cycle frame signal FRAME :; at the timing cycle PCLK2, which indicates a state of the accompanying address The read cycle operation starts, and then the master control device is ready to signal in the timing cycle PCLK3.

Page 8 1 ^ 2286 V. Description of the invention (6) The main control device is ready to accept data, and the timing period PCLK4 is issued by the device selection signal devsel # select ^ ^ = 丨 the selected device currently being accessed . Wang Zhang Qiwei, however, chose to set 20 because he was unable to complete the master control and set 16 to two η :: because he was not ready for the data. He decided to stop sending PCLK4 / so 'It is also in the timing cycle. STOP? 'As the selected device 2 is installed 16 stop f currently refers to the bus transfer action (仏 transaction), 仏 ^' This X selection device 2 still maintains the ready signal Li # is high, the state is fat : The state is completed in the timing cycle PCLK4 ', but the selected signal 20 has not driven the ready signal TRDY # (not pulled down). Therefore, during the sequence cycle PCLK4 >, no data is transmitted. Because of this, the $ selection device 20 fired at the timing cycle and issued a stop 5 tiger STOP # and kept the borrowed e. Τ4 i f " it ke A is also in preparation. L is in a high potential state ', so the master control device is set to' 6. The selected device 20 is unwilling to transmit any data. After that, the master control device 16 must be prepared at the master control device, no pull sink & cyclic frame signal FRAME #, because T ' , Stop the frame letter shooting discussion E # in the time series week data state Lishi A # ^ has not yet been pulled up, so the last 3 state :: completed in the daily order cycle PCU5. Then, since the data processing has been completed, the text selection device 20 has no data in the time period of the processing of the poor material during the time period p "丨 buckle * μ production station and device selection signal βΕνδΕΙ ^ sequence week LK6 pull up h only k number ST㈣. Send

Page 9 _4 32286 V. Description of the invention (7), and the master control device 16 needs to repeat the retry reading request again. One of the aforementioned problems is that because the master device does not know when the selected device can accept its read request, it must constantly retry the read request to process the data, which not only often occupies the PCI bus, but also wastes a lot waiting time. The traditional solution is to use BI 0S to write a timer (11 mer) program, which estimates a predetermined time in advance and requires the master control device to retry the reading after this predetermined time.

However, the problem is that the predetermined time estimated in advance is not the actual waiting time that the selected device can accept the reading of the master device. For example, when the predetermined time is set to 40 ns and the master device is required to retry after this predetermined time Read request, but in fact, the selected device can only accept its read request at 41ns. At this time, the main control device must wait 4Ons before retrying the read request. The efficiency of the central processing unit decreases. In order to solve the above-mentioned problem, the present invention further provides a method for reading the bus retry data, which includes the following steps. When a master control device sends a read data request to the <selected device through confluence ~ if it is still selected, the device will send a stop signal as the selected device. The device requested an instruction from the master device to stop reading data. At this time, the selected device keeps a ready signal of the selected device in a non-driven state to instruct the main control device to retry reading. When the selected device sends a stop signal, it also sends out an address signal containing a timing measurement (c 1 0 c k n u m b e r) to request the master control device to retry reading after this timing measurement. 3

Page 10_4 32286 V. Description of the invention (8) The timing measurement range can be set according to the number of bits of the address signal, where the address signal is 32 bits (equivalent to 2 3 2 X PC I bus) Timing cycle range), and this timing measurement value is the time to wait before the selected device accepts the read request from the master device. In the following, an embodiment of a method for reading a PCI bus retry data according to the present invention is illustrated with reference to the drawings. Brief Description of Drawings Figure 1 is a block diagram showing a computer system with a PC I bus and an expansion bus. Fig. 2 is a schematic diagram showing signals of a part of the PC interface. Figure 3 shows the timing diagram of the traditional retry cycle. Fig. 4 is a timing chart showing a retry period in one embodiment according to the present invention. Timing chart showing the traditional data transmission on PC I bus. Fig. 5 is a flowchart showing a method for reading data from the bus retry of the present invention. [Symbols] Processor ~ 1 2; main bus ~ 1 4; main bridge ~ 16; memory ~ 24; PCI bus ~ 18;-graphics device ~ 26a; local network small power: brain system interface device 6c; PCI bus master device ~ 27; bus device ~ 2 8; expansion bridge ~ 2 0: expansion bus ~ 22. Example Please refer to FIG. 5, which shows a flowchart of a method for reading data from a bus retry in the present invention. The steps are as follows: First, according to step S50, a master control device passes a bus to a

Page 丨 1 4 32286 V. Description of the invention (9) 'The selected public place issued a data reading request: FRAME #, IRDY #. Next 'according to step S52, if the selected device is not yet ready, the selected device sends a stop signal STOP #. Then according to step S54, the selected device keeps the selected device ready signal TRDY # in the non-driving state. Then according to step S56 ', an address signal AD [3 1: 〇] containing timing measurement (ci0ck) is simultaneously sent to request the master control device to perform a retry read request after this timing measurement. .

Wherein, the present invention is applicable to data transmission of a bus, such as data transmission of a PcI bus or an accelerated graphics port (AGP: accelerated graphics port). For the convenience of description, the PCI bus is used in this embodiment. Example. ′ A Please refer to FIG. 1 and FIG. 2 and refer to FIG. 4, which shows a timing chart of a retry period in the embodiment of the present invention. First, when the central processing unit 12 wants to read the data of the selected device such as the expansion bridge 20, the master control device such as the master = · 1_6 issues the bus cycle frame signal f with the 吟 #, # pp ^ in the sequence cycle pCLK2. The action of the reading cycle of the address resentment started, and then in the time sequence, "W Tu device coolly said 1 RD Y #, its reading in the data .. fetch cycle 2 is the table indicating that the main control device is ready to accept data 'The selected device then sends a Pesel selection signal Devsel # in one cycle of PCLK4.' The selected device is accessed for the purpose of claiming it.-The second selected device is also determined because its data is not ready. Γ 3 ^ Requirement of control device 'Therefore, it also issued L number 31' 0 &quot; at the timing cycle PCLK4, thinking that the selected device requires the main control device to stop

Page 12 132286 V. Description of the invention (丨 0) Data transmission instructions before ‘Meanwhile’ This selected device still keeps TRDY # in a high potential state. At this point in the text, an invalid signal is used, such as the address signal △]) [3]: 0r When the selected device issues a stop signal STOP #, it simultaneously sends out an address signal containing a clock number (clock number). AD [31: 〇] requires the host device to retry reading after this timing measurement, where the timing measurement range is within 232 bits, and the timing measurement value is the selected device ^ may &quot; acceptor The waiting time before the control device reads the request. That is, within the range of χ, the selected device can calculate the timing measurement value of the issued address signal AD according to the aforementioned waiting time. Subsequently, the first data state was completed in the timing cycle pCLK4, but the ready device was not driven by the selected device ^ "# (or not pulled to a low potential") This address was not issued by the tiger, that is, During the timing cycle pclk4, no address data is transmitted, and because ^ AD [31 〇] is an invalid signal here, it can be used to simultaneously issue a timing measurement ( clock number) address signal AD [31: 〇] to require the master control device to re-enter the &amp; retry reading requirement at a time equivalent to this timing ^ amount: σ In addition, 'Because the selected device is in the timing cycle PCLK4 sends a stop signal stop # and keeps the ready signal 7 [? 1 ^ # in a high potential state. Therefore, the master control device knows that the selected device is unwilling to transmit any data. After the definition, the main control device must first pull up the bus cycle sash signal FRAME # before the master control device is ready for the signal IRDY #. Therefore, in this example, the bus cycle sash signal FRAME # is in the timing cycle. PCLK5 is pulled up while

Page 13 V. Description of the invention (11) 432286 Because the bus cycle sash signal FRAME # is pulled up in the timing cycle pcU5, the 'stop signal STOP # has not been pulled up', so the last data state is completed in the timing cycle PCLK5. Then, since the data processing has been completed, the selected device pulls up the stop signal stop # and the set selection signal DEVSEL # at the timing cycle PCLK6. '' Among which 'No data was transmitted during the data processing

However, 'the master control device will not repeat the retry reading request within the timing measurement range set according to the aforementioned required waiting time, so 玎 avoid the PCI bus being occupied at any time' At the same time, when the master control device repeats again When retrying the read request, the selected device is already in a state where it can accept the read request and can prevent the data read from failing again.露 如上 ， 然 其 益 # is used without departing from the essence of the present invention, so the guarantor of the present invention shall prevail. Although the present invention has been disclosed with a preferred embodiment to limit the present invention, anyone who is familiar with this technique, within the scope of God and God, should be able to make a little bit more and protect the scope as the scope of the attached patent application.

Claims (1)

432286 6. Scope of patent application 1. A method for reading data from a bus retry, including the following steps: When a master control device selects a device through the bus to a selected device that is not ready, it shall be regarded as the receiving device. When the selection device requests the data request, if the device sends a stop signal, the instruction to stop reading data instructs the device to be selected to protect the cancer, to indicate that the main control device should not be installed on the device to be selected. Measure again after the measurement 2. If the scope of the patent application is measured according to the address 3. If the number of bits of the patent application signal is 32 digits 4. If the patent application is measured as the selected device / Vs, seven η Shi inch 丨 day J ^ 5. If the patent application paradigm is PC I bus. 6. If the patent application model is AGP bus. Sending the read-selected-installed master control device including the timing device and the address and the timing before the timing needs to hold a signal of the selected device ready to retry reading; and when the stop signal is issued, Send an address signal to request the master to test the request. The method described in item 1, wherein the number of bits of the signal is set. The method described in item 2 above. The method described in item 1, wherein the read request of the master control device is accepted. The method described in item 1, wherein the method described in item 1, wherein the confluence 7. —kind of confluence The method for retrying data reading is as follows: Page 15 432286 432286 t. When the scope of the patent application is complete, the selection device requires the selected state to indicate that the central processing unit of the selection device is set after the measurement (c 1 ck sequence measurement). When reading the selected master control device and ensuring that the master control device is selected, and then re-accept the master to borrow a master device and request data through the PC I bus, if the selected device has not yet The device sends a stop signal as an indication of the selected device to stop reading the data; holds the signal of the selected device ready to retry reading without driving; and Η sends a stop signal containing the timing when the stop signal is issued Address signal to request the master control device to read the request, wherein the timing measurement is the waiting time required before the control device reads the request. 8. As described in item 7 of the scope of patent application, The main control device is a main bridge. 9. The method according to item 7 of the scope of patent application, wherein the selected device is an expansion bridge. 10. The method according to item 7 of the scope of the patent application, wherein the stop signal from the selected device is in a low potential state. Π. The method described in item No. of the scope of the patent application: It is rather that the selected device keeps the ready signal of the selected device at a high potential state. Page 16