A7 B7 427064 4 k： / U 6 4 五、發明説明（j ) [發明的範圍】 本發明係有關一種具有自動重置功能之暫態干擾偵測 電路，用以偵測電路中電源端（VDD)及接地端（GND) 的電位瞬間異常變化，俾即時執行系統的重置動作。 【發明背景】 按，一般之電子電路若未設有保護裝置，在運 作時其供應之電壓會因外界之干擾訊號，或其電路 板中之元件間產生之電磁效應，而造成電壓不穩定 現象，使得其間之各元件被迫處在一個不穩定的電 壓環境下運作，使得系統發生誤動作，甚至是當機、 元件損壞：爲解決此一問題，較早期係在電路中有 裝設一手動重置元件（如：按鈕開關）者，係是靠 操作者根據其經驗來對系統之現態進行判斷，以決 定是否該驅動該重置元件，以重置該系統。較早期 之自動重置系統請參閱「第1圖」，其係爲習知重 置電路之電路示意圖，該電路多被應用在積體電路 (Integrated Circuit, 1C)上，包括：一檢知單元 14 ; 一電阻12 ;—電容13 ;以及一與該檢知單元14連 接之觸發電路15;其中該電阻12之一端接於電源 端10，另一端則接於該檢知單元14的輸入端141， 並與該電容13'串聯之，同時並於前述之連接處形成 —A節點16.，而且該電容13之另一端則是與接地 端11相接，同時在調整其後級之觸發電路15的遲 滯區後，就可在當電源端10之電壓發生變化時，控 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210Χ297公釐） -------------- 裝----^--訂------^ I (請先Μ讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 427064 經濟部中央標隼局貝工消費合作社印裝 • A7 _B7_ 五、發明説明（z) 制系統重置期間的電源電壓之變化量：然而在該傳 統的電路中，只能偵測到電源端10與接地端11之 間有關直流電源之特性的變化（例如電源打開（Power on )時的自動重置功能），其較佳者也只能偵測到 在微秒（minute-second，ms)期間的電壓變化；因 此，在系統電路板上進行靜電放電（Electrostatic Discharge，ESD)、電源線的暫態干擾（Electrical Fast Transient/Burst，EFT )測試；以及現今之大型系統 或高密度之積體電路中，傳統之重置電路對於在毫 微秒（nano-second, ns)期間因雜訊的產生所造成的 電壓變化，將無法有確實的對應動作（如：系統重 置、電壓補償），致使系統中的元件不能正常工作； 爰是， 【發明之槪述】 本發明之目的在於解決當電路中之電源端及接 地端間的電壓發生暫態雜訊干擾時，能及時對系統 進行重置，以避免電路中的元件不正常工作，係包 括：複數個偵測單元；一與該偵測單元連接之電位 參考單元，以及一與該偵測單元連接之具有決策輸 出端的狀態判讀單元，藉由該偵測單元的監督’使 得電路中之電壓在十個毫微秒（ns )之時間內發生 的異常電壓變化，能其被及時查覺而立即由該狀態 判讀單元產生一重置訊號’使系統中的各元件能於 穩定的電壓下正常工作。 4 本紙張尺度遥用中國國家橾準]CNS ) A4規格U10X297公ϋ " ---i-----—寒-------IT------.^ (請先«讀背面之注意事項再填寫本頁) Α7 經濟部中央標嗥局員工消費合作社印製 Β7 五、發明説明（3 ) 【圖式簡單說明】 第1圖，係爲習知重置電路之電路示意圖。 第2圖，係爲本發明具有自動重置功能之暫態干擾偵測電 路方塊示意圖。 第3-1圖，係爲本發明具有重置功能之第一偵測單元電路 示意圖。 第3-2圖，係爲本發明具有重置功能之第二偵測單元電路 示意圖。 第3-3圖，係爲本發明具有設定功能之第三偵測單元電路 示意圖。 第3 -4圖，係爲本發明具有設定功能之第四偵測單 元電路示意圖。 【發明之詳細說明】 請參閱「第2圖」，係爲本發明具有自動重置功能 之暫態干擾偵測電路方塊示意圖，包括有：複數個具有重 置（Reset )功能的第一偵測單元21 ;複數個具有重置功 能的第二偵測單元22 ;複數個具有設定（Set)功能的第 三偵測單元23;複數個具有設定功能的第四偵測單元24 : 第一電位參考單元211;第二電位參考單元221;第三電 位參考單元2：U ;第四電位參考單元241 ;以及一具有決 .策輸出端201的狀態判讀單元20;其中上述之各偵測單 元（21、22、23.、24)係爲分別藉由其所屬之第一、第二' 第三、第四狀態輸出端（216、226、236、246 )與該狀態 判讀單元20連接；請參閱「第3-i圖」，係爲本發明具 5 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） I-------—裝-------.U------ (請先閱讀背面之注意事項再填寫本頁) A A7 B7 經濟部中夬標準局員工消費合作社印製 五、發明説明（4·) 有重置功能之第一偵測單元電路示意圖，係是由一反或閘 (NOR Gate) 212及一與之並聯的反閘（Not Gate) 213所 構成’並在該第一偵測單元21之第一偵測端215連接有 與系統的電源端10連接之該第一電位參考單元211，同 時更具有一弟一重置端214用以在當電源開啓（p〇wer on Reset)時，使該第一偵測單元21提供一爲”Logic Low”的 値給狀態判讀單元20，其中與之耦合之該第一電位參考 單元211則是在當電源端10瞬間發生變化時，能將雜訊 (Noise)傳至該第一偵測單元21的內部，使其改變現有 之輸出狀態値；請參閱「第3-2圖」，係爲本發明具有重 置功能之第二偵測單元電路示意圖，其元件組成亦是由一 反或閘222及一與之並聯之反閘223所構成，唯該第二偵 測單元22之第二偵測端225連接有與系統的接地端11連 接之該第二電位參考單元221，此外更具有一第二重置端 224用以在實行線上電源重置程序時，提供一爲”Logic Low”的値給該第二偵測單元22，與之耦合之該第二電位 參考單元221則是提供接地端11發生瞬間變化時耦合的 路徑，讓該第二偵測單元22現有之輸出狀態的値：受雜 訊的干擾而改變。 請參閱「第3-3及第3-4圖」，係爲本發明具有設定 功能之第三、第四偵測單元電路示意圖，係包含有：一反 及閘（NAND Gate) (232、242)及一與該反及聞（232、 242 )並聯之反閘（233、243 )，而該第三、第四電位參 考單元（231、241)與該第三、第四偵測單元（23、24) 6 - - - - * ........ —I— 1---- . I -------n (請先閲讀背面之注意事項再填寫本頁) 訂 本纸張尺度速用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 427064 , A7 _____—_B7_ 五、發明説明（y) 耦合的方式則分別如「第3-3及第3-4圖」中之該第一、 第二電位參考單元（211'221)的連接方式且功能亦相同， 而該第三' 第四偵測單元（23、24 )與該第一，第二偵測 單元（21、22)的差異主要在於，該第三、第四偵測單元 (23、24)的電路結構，係分別具有第一、第二設定端（234、 244 )’用以使該第三、第四偵測單元（23、24 )之初始 値被設成”Logic High”；此外，上述之電位參考單元（211、 221、231、241 )係爲一耦合電容。 因此，請再參閱「第2圖」，當在系統在運作或對其 電路板做線上之靜電放電，以及電源線的暫態千擾時，其 電源端10和接地端11間的電位會因雜訊的干擾，而有瞬 間電位變化的現象發生，該瞬間之電位變化約持續十個毫 微秒（ns)左右，且其電位的變化係是於正、負電位間來 回擺盪數次，故上述重置電路中之第一、第二偵測單元 (21、22)將依據前述電位的瞬間變化，藉由其內之基底 (Substrate)及井區（Well)中電荷之流失度，改變其目 前之第一輸出端之輸出狀態，其中第一、第二偵測單元 (21、22 )之輸出狀態變爲”Logic High” ；同理，該第三、 第四偵測單元（23、24)之輸出狀態也將因雜訊的干擾而 變爲”Logic Low”，同時再經由與上述各偵測單7C ( 21、22、 23、24 )連接之該狀態判讀單元20，統合後自其決策端201 輸出端產生一爲”Logic High”的重置訊號’而使系統或積 體電路進行重置的動作’同時並再將第一、第二偵測單元 (21、22)之輸出狀態回復爲”Logic Low” ’第三、第四 7 本紙張尺度適用中國國家標隼（CNS ) A4規格（2丨0X 297公釐〉 . 1—. 1 裝 訂 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作杜印製 【圖式符號說明】 10電源端 11接地_ 12電阻 13電容 14檢知單元 141輸入端 15觸發單元 16A節點 20狀態判讀單元 201決策輸出端 4270 6 4 A7 B7 五、發明説明（厶） 偵測單元（23、24 )之輸出狀態回復爲”Logk High”，其 中該狀態判讀單元20係由與第一、第二偵測單元（2卜22) 連接之或閘（202、203 )和與第三、第四偵測單元（23、 24 )連接反及閘（204、205 );以及連接前述之或閘（202、 203)與反及閘（ 204、205)之多輸端或閘206所構成者。 總結，由於上述之偵測單元之電路係由邏輯閘所組 成，所以該反或閘可以一或閘之輸出端串聯一反閘所構 成：該反及閘可以一及閘之輸出端串聯一反閘所構成；而 該反閘則可以一輸入端均共接於一節點之反或閘或反及閘 所替代；故本發明所述僅爲較佳實施例而已，並非用來限 定本發明實施例之範圍，而仍可變化其形態與細節，且不 脫離本發明之精神而達成，並能由熟悉此項技藝之人士可 了解。 202或閘 203或閛 204反及閘 205反及閘 206多輸入端或閘 21第一偵測單元 211第一電位參考單元 212反或閘 213反閘 214第一重置端 本紙悵尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ----------1 裝-------ir------組 {請先閲讀背面之注意事項再填寫本頁) 427064 B7 五、發明説明（7) 215第一偵測端 233反閘 216第一輸出端 234第三重置端 22第二偵測單元 235第三偵測端 221第二電位參考單元 236第三輸出端 222反或閘 24第四偵測單元 223反閘 241第四電位參考單元 224第二重置端 242反或閘 225第二偵測端 243反閘 226第二輸出端 244第四重置端 23第三偵測單元 245第四偵測端 231第三電位參考單元 246第四輸出端 232反或閘 ίιιί---—裝----^--訂----11-線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 9 本紙張尺度適用中國國家標隼（CNS ) Μ規格（2〖0X297公釐）A7 B7 427064 4 k: / U 6 4 V. Description of the invention (j) [Scope of the invention] The present invention relates to a transient interference detection circuit with an automatic reset function for detecting a power supply terminal (VDD ) And the potential of the ground (GND) momentarily change abnormally, and the reset action of the system is performed immediately. [Background of the invention] According to the press, if the general electronic circuit is not provided with a protective device, the voltage it supplies during operation will cause voltage instability due to external interference signals or electromagnetic effects between components in its circuit board. In order to solve the problem, the components in the circuit are forced to operate in an unstable voltage environment, causing the system to malfunction, or even to crash, and the components are damaged. In order to solve this problem, a manual override was installed in the circuit earlier. Those who place components (such as push-button switches) rely on the operator to judge the current state of the system based on their experience to determine whether the reset component should be driven to reset the system. For earlier automatic reset systems, please refer to "Figure 1", which is a schematic circuit diagram of a conventional reset circuit. This circuit is mostly used in integrated circuits (1C), including: a detection unit 14; a resistor 12; a capacitor 13; and a trigger circuit 15 connected to the detection unit 14; one of the resistors 12 is connected to the power terminal 10, and the other end is connected to the input terminal 141 of the detection unit 14. , And is connected in series with the capacitor 13 ', and at the same time, it is formed at the connection point-A node 16. The other end of the capacitor 13 is connected to the ground terminal 11, and the trigger circuit 15 of the subsequent stage is adjusted After the hysteresis zone is reached, when the voltage at the power supply terminal 10 changes, the paper size is controlled by the Chinese National Standard (CNS) A4 specification (210 × 297 mm) ------------- -Install ---- ^-Order ------ ^ I (Please read the notes on the back before filling this page) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 427064 Central Standards Bureau of the Ministry of Economic Affairs Industrial and consumer cooperative printing • A7 _B7_ V. Description of the invention (z) Variation of power supply voltage during reset of system : However, in this traditional circuit, only changes in the characteristics of the DC power supply between the power terminal 10 and the ground terminal 11 can be detected (such as the automatic reset function when the power is turned on), which is better It can only detect the voltage change during the minute-second (ms); therefore, the system circuit board performs Electrostatic Discharge (ESD), power line transient interference (Electrical Fast Transient / Burst) , EFT) test; and in today's large-scale systems or high-density integrated circuits, the traditional reset circuit will not be able to change the voltage caused by noise during the nano-second (ns) period. There are certain corresponding actions (such as: system reset, voltage compensation), which cause the components in the system to not work properly; 爰 Yes, [Introduction of the invention] The purpose of the present invention is to solve the problem when the power and ground terminals When the transient voltage interference occurs in the voltage, the system can be reset in time to prevent the components in the circuit from working abnormally, including: a plurality of detection units; one and the detection unit The connected potential reference unit and a status reading unit with a decision output terminal connected to the detection unit, and the voltage in the circuit occurs within ten nanoseconds (ns) by the supervision of the detection unit. The abnormal voltage change can be detected in time and a reset signal is generated immediately by the state reading unit, so that each component in the system can work normally under a stable voltage. 4 This paper uses the national standard of China] CNS) A4 specification U10X297 public address " --- i ------- cold ------- IT ------. ^ (Please first «Read the precautions on the back and fill out this page) Α7 Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economics B7 V. Description of the invention (3) [Simplified illustration of the diagram] Figure 1 is a circuit of a conventional reset circuit schematic diagram. Figure 2 is a block diagram of a transient interference detection circuit with an automatic reset function according to the present invention. Figure 3-1 is a schematic diagram of a first detection unit circuit with a reset function according to the present invention. Figure 3-2 is a schematic diagram of a second detection unit circuit with a reset function according to the present invention. Figures 3-3 are schematic diagrams of the third detection unit circuit with a setting function of the present invention. Figures 3-4 are schematic diagrams of the fourth detection unit circuit with a setting function of the present invention. [Detailed description of the invention] Please refer to "Figure 2", which is a block diagram of a transient interference detection circuit with an automatic reset function according to the present invention, including: a plurality of first detections with a reset function Unit 21; a plurality of second detection units 22 with a reset function; a plurality of third detection units 23 with a set function; a plurality of fourth detection units 24 with a set function: a first potential reference A unit 211; a second potential reference unit 221; a third potential reference unit 2: U; a fourth potential reference unit 241; and a state judging unit 20 having a decision output terminal 201; each of the above-mentioned detection units (21 , 22, 23., 24) are respectively connected to the status reading unit 20 through the first, second, third, and fourth status output terminals (216, 226, 236, 246); "Figure 3-i" is for the present invention with 5 paper sizes applicable to China National Standards (CNS) A4 specifications (210X297 mm) I ---------------------. U ------ (Please read the notes on the back before filling out this page) A A7 B7 Employees' Consumption Cooperation Printed by the company 5. Invention description (4 ·) Circuit diagram of the first detection unit with reset function, which is composed of a NOR Gate 212 and a Not Gate 213 connected in parallel. The first potential reference unit 211 is connected to the first detection terminal 215 of the first detection unit 21 and is connected to the power supply terminal 10 of the system. When the power is turned on (power on Reset), the first detection unit 21 is provided with a “Logic Low” chirp to the state reading unit 20, and the first potential reference unit 211 coupled to the first detection unit 21 is When the power terminal 10 changes instantaneously, it can transmit noise to the inside of the first detection unit 21, so that it can change the current output state. Please refer to "Figure 3-2", which is the present invention Circuit diagram of the second detection unit with reset function. Its component composition is also composed of a reverse OR gate 222 and a parallel reverse gate 223. Only the second detection terminal of the second detection unit 22 225 is connected to the second potential reference unit 221 connected to the ground terminal 11 of the system. A second reset terminal 224 is used to provide a “Logic Low” cymbal to the second detection unit 22 during the online power reset procedure, and the second potential reference unit 221 coupled thereto is provided. The path coupled when the ground terminal 11 changes instantaneously causes the existing output state of the second detection unit 22 to be changed by interference from noise. Please refer to "Figures 3-3 and 3-4", which are schematic diagrams of the third and fourth detection unit circuits with a setting function of the present invention, including: a NAND gate (232, 242 ) And an anti-brake (233, 243) connected in parallel with the anti-induction (232, 242), and the third and fourth potential reference units (231, 241) and the third and fourth detection units (23, 23) 、 24) 6----* ........ —I— 1 ----. I ------- n (Please read the notes on the back before filling this page) Quick use of paper standard Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 427064, A7 _______B7_ V. Description of the invention (y) The coupling methods are as shown in the “3rd” -3 and Figures 3-4 "The first and second potential reference units (211'221) are connected in the same manner and function, and the third and fourth detection units (23, 24) and the The difference between the first and second detection units (21, 22) is mainly that the circuit structures of the third and fourth detection units (23, 24) have first and second setting terminals (234, 244, respectively). ) 'To make the The initial thresholds of the third and fourth detection units (23, 24) are set to "Logic High". In addition, the above-mentioned potential reference unit (211, 221, 231, 241) is a coupling capacitor. Therefore, please refer to the "Figure 2" again. When the system is operating or the circuit board is subject to electrostatic discharge, and the power line is subject to transient disturbances, the potential between its power supply terminal 10 and ground terminal 11 may vary. The transient potential changes occur at this moment. The potential change at this moment lasts about ten nanoseconds (ns), and the potential change is swinging back and forth between the positive and negative potential several times, so the above The first and second detection units (21, 22) in the reset circuit will change their current based on the instantaneous changes in the aforementioned potentials and the degree of charge loss in the substrate and well area. The output state of the first output terminal, wherein the output states of the first and second detection units (21, 22) become "Logic High"; similarly, the third and fourth detection units (23, 24) The output status will also be changed to "Logic Low" due to noise interference. At the same time, the status judgment unit 20 connected to each of the above detection orders 7C (21, 22, 23, 24) will make its own decision after integration. The output of terminal 201 generates a reset signal 'Logic High' System or integrated circuit to perform the reset operation. At the same time, the output status of the first and second detection units (21, 22) will be restored to "Logic Low". Standard (CNS) A4 specification (2 丨 0X 297 mm>. 1—. 1 gutter (please read the precautions on the back before filling this page) Printed by the staff of the Central Bureau of Standards of the Ministry of Economic Affairs [Illustration symbols Description] 10 Power terminal 11 Ground_ 12 Resistor 13 Capacitor 14 Detection unit 141 Input terminal 15 Trigger unit 16A Node 20 State reading unit 201 Decision output 4270 6 4 A7 B7 V. Description of the invention (厶) Detection unit (23, 24) The output status is returned to "Logk High", wherein the status reading unit 20 is composed of OR gates (202, 203) connected to the first and second detection units (22, 22) and third and fourth The detection unit (23, 24) is connected to the reverse gate (204, 205); and the multiple input terminal or gate 206 connected to the aforementioned OR gate (202, 203) and the reverse gate (204, 205). Summary Because the circuit of the above detection unit is composed of logic gates, The OR gate can be composed of an OR gate in series with a reverse gate: the OR gate can be composed of an AND gate output in series with a reverse gate; and the reverse gate can have an input terminal connected in common to a node It is replaced by the anti-OR gate or the anti-AND gate; therefore, the present invention is only a preferred embodiment, and is not intended to limit the scope of the embodiment of the present invention, but its form and details can be changed without departing from the spirit of the present invention It is achieved and can be understood by those familiar with the art. 202 or gate 203 or 閛 204 anti-gate 205 anti-gate 206 multi-input terminal or gate 21 first detection unit 211 first potential reference unit 212 anti-or gate 213 anti-gate 214 first reset terminal National Standard (CNS) A4 Specification (210X297 mm) ---------- 1 Pack --------- ir ------ Group {Please read the notes on the back before filling in this (Page) 427064 B7 V. Description of the invention (7) 215 First detection terminal 233 Reverse brake 216 First output terminal 234 Third reset terminal 22 Second detection unit 235 Third detection terminal 221 Second potential reference unit 236 Third output terminal 222 reverse OR gate 24 fourth detection unit 223 reverse gate 241 fourth potential reference unit 224 second reset terminal 242 reverse OR gate 225 second detection terminal 243 reverse gate 226 second output terminal 244 fourth The reset terminal 23, the third detection unit 245, the fourth detection terminal 231, the third potential reference unit 246, and the fourth output terminal 232 are reverse-OR gated. (Please read the notes on the back before filling out this page) Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 9 This paper size is applicable to China National Standard (CNS) Μ specifications (2 〖0X29 7 mm)